Barrier layer for electrical contact areas

Abstract

The power switching device includes: a semiconductor layer structure including an active region and an active region, the active region including a plurality of unit cells, and the active region including a gate pad on the semiconductor layer structure and a gate bonding pad on the gate pad and electrically connected to the gate pad; an isolation layer between the gate pad and the gate bonding pad; and a barrier layer between the gate pad and the isolation layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 863,642, filed April 30, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to semiconductor devices, and more particularly, to power semiconductor switching devices. Background Technology

[0004] A metal-oxide-semiconductor field-effect transistor (“MOSFET”) is a well-known type of semiconductor transistor that can be used as a switching device. A MOSFET is a three-terminal device comprising a source region and a drain region separated by a channel, and a gate electrode deployed adjacent to the channel region. A MOSFET can be turned on or off by applying a gate bias voltage to the gate electrode. When the MOSFET is on (i.e., it is in its “on state”), current flows through the channel region of the MOSFET between the source and drain regions. When the bias voltage is removed from the gate electrode (or reduced below a threshold level), current stops flowing through the channel region. For example, an n-type MOSFET has n-type source and drain regions and a p-type channel. Therefore, an n-type MOSFET has an “npn” design. An n-type MOSFET is turned on when a gate bias voltage is applied to the gate electrode sufficient to create a conductive n-type reverse layer in the p-type channel region that electrically connects the n-type source and drain regions, allowing majority carriers to conduct therebetween.

[0005] The gate electrode of a power MOSFET is typically separated from the channel region by a thin gate insulating pattern (such as a silicon oxide pattern). Because the MOSFET's gate electrode is insulated from the channel region by the gate insulating pattern, a minimal gate current is required to keep the MOSFET in its on-state or to switch it between its on and off states. Since the gate forms a capacitor with the channel region, the gate current remains small during switching. Therefore, only minimal charging and discharging current is needed during switching, allowing for a less complex gate drive circuitry system.

[0006] A bipolar junction transistor (“BJT”) is another well-known type of semiconductor transistor, which is also commonly used as a switching device. A BJT comprises two pn junctions formed close together in a semiconductor material. In operation, charge carriers enter a first region of the semiconductor material adjacent to one of the pn junctions (the emitter). Most charge carriers leave the device from a second region of the semiconductor material adjacent to the other pn junction (the collector). The collector and emitter are formed in regions of semiconductor material having the same conductivity type. A third, relatively thin region of semiconductor material, called the base, is located between the collector and emitter and has a conductivity type opposite to that of the collector and emitter. Thus, the two pn junctions of the BJT are formed at the junction of the collector and base, and at the junction of the base and emitter. By allowing a small current to flow through the base of the BJT, a proportionally larger current flows from the emitter to the collector.

[0007] A BJT is a current-controlled device in which a BJT is "turned on" by allowing current to flow through the base of the transistor (i.e., it is biased so that current flows between the emitter and collector). For example, in an npn BJT (i.e., a BJT with an n-type collector and emitter region and a p-type base region), the transistor is typically turned on by applying a positive voltage to the base to forward bias the base-emitter pn junction. When the device is biased in this way, the hole current flowing into the base of the transistor is injected into the emitter. Holes are called "majority carriers" because the base is a p-type region, and holes are the "normal" charge carriers in this region. In response to the hole current flowing into the emitter, electrons are injected from the emitter into the base and diffuse towards the collector at the base. These electrons are called "minority carriers" because electrons are not normal charge carriers in the p-type base region. The device is called a "bipolar" device because the emitter-collector current includes both electron and hole currents.

[0008] BJTs require relatively large base currents to keep the device in its on-state. Therefore, relatively complex external drive circuitry is required to supply the relatively large base current demanded by high-power BJTs. Furthermore, due to the bipolar nature of current conduction, the switching speed of a BJT can be significantly slower than that of a power MOSFET.

[0009] The third well-known type of semiconductor switching device is the Insulated Gate Bipolar Transistor (“IGBT”), which is a device combining the high-impedance gate of a power MOSFET and the low on-state conduction losses of a power BJT. For example, an IGBT can be implemented as a Darlington pair comprising a high-voltage n-channel MOSFET at the input and a BJT at the output. The base current of the BJT is supplied through the channel of the MOSFET, allowing for simplified external drive circuitry.

[0010] The demand for high-power semiconductor switching devices that can carry large currents in their "on" state and block large voltages (e.g., hundreds or even thousands of volts) in their reverse blocking state is increasing. To support high current densities and block such high voltages, power MOSFETs and IGBTs typically have a vertical structure where the source and drain are located on opposite sides of a thick semiconductor layer structure to block higher voltage levels. In very high-power applications, semiconductor switching devices are typically formed using wide-bandgap semiconductor material systems (here, the term "wide-bandgap semiconductor" includes any semiconductor with a bandgap of at least 1.4 eV), such as, for example, silicon carbide ("SiC"), which has several advantageous characteristics, including, for example, high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturated electron drift velocity. Compared to devices formed using other semiconductor materials (such as, for example, silicon), electronic devices formed using silicon carbide can have the ability to operate at higher temperatures, higher power densities, higher speeds, higher power levels, and / or higher radiation densities. Summary of the Invention

[0011] According to some embodiments of the present invention, a semiconductor device includes a semiconductor layer structure comprising an active region and an active region, the active region comprising a plurality of unit cells and the active region comprising a gate pad on the semiconductor layer structure and a gate bonding pad on the gate pad and electrically connected to the gate pad, an isolation layer between the gate pad and the gate bonding pad, and a barrier layer between the gate pad and the isolation layer.

[0012] In some embodiments, the barrier layer is a first barrier layer, and the semiconductor device further includes a second barrier layer on the gate pad and on the first barrier layer.

[0013] In some embodiments, at least a portion of the isolation layer is located between the first barrier layer and the second barrier layer.

[0014] In some embodiments, the barrier layer comprises multiple layers.

[0015] In some embodiments, the barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0016] In some embodiments, the barrier layer is a first barrier layer, and the semiconductor device further includes a gate finger on the active region and electrically connected to a gate bonding pad, and a second barrier layer on the gate finger.

[0017] In some embodiments, the second barrier layer is located on the top surface and sidewalls of the gate finger.

[0018] In some embodiments, the barrier layer is a first barrier layer, and the semiconductor device further includes a source contact located on the semiconductor layer structure, a second barrier layer located on the sidewalls and bottom surface of the source contact, and a third barrier layer located between the semiconductor layer structure and the second barrier layer.

[0019] According to some embodiments of the present invention, a semiconductor device includes a semiconductor substrate, a gate pad on the semiconductor substrate, a gate bonding pad located on the gate pad and electrically connected to the gate pad, a first barrier layer located between the bottom of the gate bonding pad and the gate pad in a first direction perpendicular to the top surface of the semiconductor substrate, and a second barrier layer located between the gate pad and the first barrier layer in the first direction.

[0020] In some embodiments, the width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate exceeds the width of the portion of the first barrier layer between the bottom of the second barrier layer and the gate bonding pad.

[0021] In some embodiments, the thickness of the second barrier layer is substantially uniform along the width of the second barrier layer in the second direction.

[0022] In some embodiments, the gate bonding pad is coupled to the gate pad via a contact hole having opposing sidewalls, a portion of the first barrier layer is on the opposing sidewalls of the contact hole, and the width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate is greater than the width of the contact hole in the second direction.

[0023] In some embodiments, the semiconductor device further includes an isolation layer, wherein a portion of the isolation layer is located between the second barrier layer and the gate bonding pad.

[0024] In some embodiments, the second barrier layer comprises multiple layers.

[0025] In some embodiments, the second barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0026] In some embodiments, the second barrier layer is located on the top surface and sidewall of the gate pad.

[0027] In some embodiments, the material of the second barrier layer is different from the material of the first barrier layer.

[0028] In some embodiments, the semiconductor device further includes a semiconductor layer structure comprising an active region and an active region, wherein a gate pad is on the active region, a gate finger is on the active region and electrically connected to the gate pad, and a third barrier layer is on the gate finger.

[0029] In some embodiments, a third barrier layer is located on the top surface and sidewalls of the gate finger.

[0030] According to some embodiments of the present invention, a semiconductor device includes a semiconductor substrate, a gate pad on the semiconductor substrate, an isolation layer on the gate pad, an isolation layer and a first barrier layer on the gate pad, and a second barrier layer located between the gate pad and the first barrier layer in a first direction, wherein the width of the second barrier layer in a second direction exceeds the width of the first barrier layer in the second direction.

[0031] In some embodiments, the semiconductor device further includes a gate bonding pad located on the gate pad and electrically connected to the gate pad via a contact hole in an isolation layer having opposing sidewalls, the first barrier layer including a first portion extending in a second direction between opposing sidewalls of the contact hole, and the width of the second barrier layer in the second direction exceeding the width of the first portion of the first barrier layer in the second direction.

[0032] In some embodiments, a portion of the isolation layer is between the second barrier layer and the gate bonding pad.

[0033] In some embodiments, the isolation layer is on the top surface of the second barrier layer and on the sidewall of the first barrier layer.

[0034] According to some embodiments of the present invention, a semiconductor device includes a semiconductor layer structure, a plurality of unit cell transistors electrically connected in parallel, each unit cell transistor including a gate finger extending in a first direction on the top surface of the semiconductor layer structure, the gate fingers being spaced apart from each other along a second direction, and an auxiliary gate electrode barrier layer on the upper surface of each gate finger.

[0035] In some embodiments, the gate refers to polysilicon.

[0036] In some embodiments, the auxiliary gate electrode barrier layer comprises titanium (Ti) and / or tantalum (Ta).

[0037] In some embodiments, an auxiliary gate electrode barrier layer is also present on the opposite sidewall of each gate finger in the gate fingers.

[0038] In some embodiments, the semiconductor layer structure includes an active region and an active region, and the active region includes a plurality of unit cell transistors. The active region includes: a gate pad on the semiconductor layer structure; a gate bonding pad on the gate pad and electrically connected to the gate pad; an isolation layer between the gate pad and the gate bonding pad; and an auxiliary gate pad barrier layer between the gate pad and the isolation layer.

[0039] In some embodiments, an auxiliary gate pad barrier layer is located on the top surface and sidewalls of the gate pad.

[0040] In some embodiments, the semiconductor device further includes a gate pad barrier layer located between the auxiliary gate pad barrier layer and the gate bonding pad.

[0041] In some embodiments, the auxiliary gate electrode barrier layer comprises multiple layers.

[0042] In some embodiments, the semiconductor device further includes a source contact on the semiconductor layer structure, a source blocking layer on the sidewalls and bottom surface of the source contact, and an auxiliary source blocking layer between the semiconductor layer structure and the source blocking layer.

[0043] In some embodiments, the semiconductor device further includes an isolation layer located on the gate finger, and an auxiliary gate electrode barrier layer located between the isolation layer and the gate finger. Attached Figure Description

[0044] Figure 1 This is a schematic plan view of a semiconductor wafer including multiple power switching devices according to an embodiment of the present invention.

[0045] Figure 2A Is included Figure 1 A schematic plan view of one of the power switching devices on a semiconductor wafer.

[0046] Figure 2B yes Figure 2A A schematic plan view of a power switching device in which the source and gate metallization have been removed.

[0047] Figure 3A It is along Figure 2B A schematic cross-sectional view taken along line A-A' illustrates the unit cell structure in the active region and the gate pads in the non-active region of a conventional device. Figure 3B yes Figure 3A A schematic cross-sectional view of part A. Figure 3C yes Figure 3A A schematic cross-sectional view of part B.

[0048] Figure 4A The illustrations depict semiconductor devices according to some embodiments described herein. Figure 4B yes Figure 4A A schematic cross-sectional view of part A. Figure 4C Additional semiconductor devices according to some embodiments described herein are illustrated.

[0049] Figure 5A and 5B Additional semiconductor devices according to some embodiments described herein are illustrated.

[0050] Figure 6A Additional semiconductor devices according to some embodiments described herein are illustrated. Figure 6B yes Figure 6A A schematic cross-sectional view of part B. Figures 6C to 6EAdditional semiconductor devices according to some embodiments described herein are illustrated.

[0051] Figure 7-12 A method for manufacturing a semiconductor device according to an embodiment described herein is illustrated. Detailed Implementation

[0052] Currently, power silicon carbide MOSFETs are used in applications requiring high voltage blocking (such as 5,000 volts or higher). For example, silicon carbide MOSFETs are commercially available with a rated current density of 10 A / cm². 2 Or higher, blocking voltages of at least 10kV. To form such a device, multiple “unit cells” are typically formed, each unit cell comprising a MOSFET transistor. In high-power applications, a large number of these unit cells (e.g., hundreds or thousands) are typically provided on a single semiconductor substrate, and a gate electrode pattern is formed on the top side of the semiconductor substrate, which serves as the gate electrode for all unit cells. The opposite (bottom) side of the semiconductor substrate serves as the common drain for all unit cells of the device. Multiple source contacts are formed on the source region in the semiconductor layer structure, exposed within the openings of the gate electrode pattern. These source contacts are also electrically connected to each other to serve as a common source. The resulting device has three terminals: a common source terminal, a common drain terminal, and a common gate electrode, which serve as terminals for hundreds or thousands of individual unit cell transistors. It will be appreciated that the above description is for n-type MOSFETs; for p-type MOSFETs, the positions of the drain and source are reversed.

[0053] The gate electrode pattern of a power MOSFET can be achieved by forming a patterned conductive layer comprising a plurality of elongated gate fingers extending through the active region of the device. The patterned conductive layer may comprise a semiconductor layer, such as, for example, a polysilicon layer and / or doped silicon (Si). The patterned conductive layer may also comprise gate pads in the non-active region of the device, and each gate finger may be connected to the gate pad either directly or via one or more gate buses and / or conductive vias.

[0054] This disclosure describes a method for improving diffusion barrier protection between a device layer and a metallization layer while altering the conductivity and adhesion between the layers. This would be particularly useful for improving the gate contact region in power transistors (e.g., MOSFETs or IGBTs).

[0055] The embodiments described herein may involve adding a material layer (such as TiN, other metal nitrides, and / or intermetallic compounds) on top of conductive layers, such as gate pads and / or gate electrodes (typically doped Si or silicide materials), source contacts, and / or other layers requiring additional contacts (such as current or temperature sensing devices within a power device). The material layer may possess properties such as diffusion barrier, enhanced conductivity, and / or adhesion to the contact areas (insulating and / or conductive layers) above it.

[0056] Metals, such as those used in metal layers, often contain a large number of impurities that can harmfully affect semiconductors or metal-insulator-semiconductor interfaces; therefore, improved barrier properties would be useful for semiconductor devices.

[0057] Various aspects of the invention will now be discussed in more detail with reference to the accompanying drawings, which illustrate exemplary embodiments of the invention.

[0058] Figure 1 This is a schematic plan view of a wafer 10 including multiple power switching devices according to an embodiment of the present invention. (See reference) Figure 1 The wafer 10 may be a thin planar structure comprising a semiconductor layer structure on which other material layers, such as insulating layers and / or metal layers, are formed. The semiconductor layer structure may include a semiconductor substrate and / or multiple other semiconductor layers. Multiple power switching devices 100 may be formed using the wafer 10. The switching devices 100 may be formed in rows and columns and may be spaced apart from each other, such that the wafer 10 may subsequently be monolithized (e.g., diced) to separate the individual switching devices 100 for packaging and testing. In some embodiments, the wafer 10 may include a silicon carbide substrate having one or more silicon carbide layers formed thereon (e.g., by epitaxial growth). Other semiconductor layers (e.g., polysilicon layers), insulating layers, and / or metal layers may be formed on the silicon carbide semiconductor layer structure to form the power switching device 100. In some embodiments, the silicon carbide substrate and the silicon carbide layers formed thereon may be 4H silicon carbide.

[0059] Figure 2A Is included Figure 1 A schematic plan view of one of the power switching devices 100 on a semiconductor wafer 10. Figure 2B yes Figure 2A A schematic plan view of a power switching device 100, wherein the source and gate metallization have been removed. In the following description, it is assumed that the power switching device 100 is an n-type power MOSFET 100.

[0060] like Figure 2AAs shown, the protective layer 110 covers most of the top surface of the power MOSFET 100. The protective layer 110 may be formed of, for example, polyamide. Various bonding pads may be exposed through openings 112 in the protective layer 110. The bonding pads may include a gate bonding pad 120 and one or more source bonding pads 122. Figure 2A The configuration, shape, and structure of the gate bonding pad 120 and source bonding pad 122 shown are merely examples, and the embodiments described herein are not limited thereto. Figure 2A The image shows two source bonding pads, 122-1 and 122-2. Although in... Figure 2A While not visible, drain contacts and / or bonding pads 124 may be provided on the bottom side of MOSFET 100. Bonding pads 120, 122, and 124 may be formed of metal (such as aluminum), and bonding lines may be easily attached via conventional techniques such as thermoforming or soldering. Source contacts are provided to contact the semiconductor layer structure of MOSFET 100, as will be discussed in more detail below. Source contacts may be the lower portion of a source metal pattern 123 extending across most of the upper surface of MOSFET 100 (e.g., all of the upper surface of MOSFET 100 except for the portion occupied by gate bonding pad 120). Source bonding pads 122-1 and 122-2 may include portions of the source metal pattern 123 exposed by openings 112 in the protective layer 110. Bonding lines 20 are in... Figure 2A As shown, it can be used to connect the gate bonding pad 120 and the source pads 122-1, 122-2 to an external voltage source (not shown), such as terminals of other circuit elements.

[0061] like Figure 2B As shown, the MOSFET 100 includes a semiconductor layer structure comprising an active region 102 and an active region 104. The active region 102 is the region of the device that includes an operable transistor (e.g., a unit cell transistor discussed herein), while the active region 104 is the region that does not include such an operable transistor. A unit cell transistor 200 of the MOSFET 100 is formed in the active region 102. The location of a unit cell 200 is determined by… Figure 2B Box 200 in the diagram is shown to provide context.

[0062] In some embodiments, the active region 102 may generally correspond to the region below the source metal pattern 123. The non-active region 104 includes a gate pad portion 106 and a termination portion 108. The gate pad portion 106 of the non-active region 104 may generally correspond to the portion of the semiconductor layer structure below the gate pad 132. The termination portion 108 of the non-active region 104 may extend around the periphery of the MOSFET 100 and may include one or more termination structures, such as guard rings and / or junction termination extensions that may reduce electric field congestion around the device edges. The termination structure (shown as guard ring 109) may disperse the electric field along the periphery of the MOSFET 100, thereby reducing electric field congestion. Edge termination structures can be used to increase the reverse blocking voltage, at which a phenomenon known as "avalanche breakdown" occurs, where the increased electric field causes runaway charge carriers to be generated within the semiconductor device, resulting in a sharp increase in current that can damage or even destroy the device.

[0063] like Figure 2B As further shown, a gate electrode pattern 130 may be provided, including a gate pad 132, a plurality of gate fingers 134, and one or more gate buses 136 electrically connecting the gate fingers 134 to the gate pad 132. The gate pad 132 of the gate electrode pattern 130 may be below the gate bonding pad 120 in the gate pad portion 106 of the non-active region 104, and the gate fingers 134 may extend (e.g., horizontally) across the active region 102. An insulating layer (not shown) may cover the gate fingers 134 and (one or more) gate buses 136. A source metal pattern 123 may be provided over the gate fingers 134 and the insulating layer, wherein the source contacts of the source metal layer contact corresponding source regions in the semiconductor layer structure in the openings between the gate fingers 134.

[0064] Figure 3A It is along Figure 2B A schematic cross-sectional view taken along line A-A' illustrates the unit cell structure in the active region and the gate pads in the non-active region of a conventional device. Figure 3B yes Figure 3A A schematic cross-sectional view of part A. Figure 3C yes Figure 3A A schematic cross-sectional view of part B.

[0065] refer to Figure 3A The MOSFET device 100 may include unit cells 200 that are part of the active region 102 of the MOSFET 100. The unit cell 200 may be one of a plurality of unit cells 200 electrically arranged in parallel.

[0066] The power MOSFET 100 and therefore the unit cell 200 may include an n-type wide-bandgap semiconductor substrate 210. The substrate 210 may include, for example, a single-crystal 4H silicon carbide semiconductor substrate. The substrate 210 may be heavily doped with n-type impurities (i.e., n... + (Silicon carbide substrate). Impurities may include, for example, nitrogen or phosphorus. The doping concentration of substrate 210 may be, for example, 1 x 10⁻⁶. 18 atoms / cm 3 and 1x10 21 atoms / cm 3 The thickness can be between 100 and 500 micrometers, but other doping concentrations can be used. The substrate 210 can be any suitable thickness (e.g., between 100 and 500 micrometers).

[0067] A lightly doped n-type silicon carbide drift region 220 can be provided on substrate 210. The n-type silicon carbide drift region 220 can be formed, for example, by epitaxial growth on the silicon carbide substrate 210. The n-type silicon carbide drift region 220 can have, for example, a 1x10⁻¹² kJ / m² area. 16 Up to 5x10 17 Dopant / cm 3 The doping concentration. The n-type silicon carbide drift region 220 can be a thick region with a vertical height of, for example, 3-100 micrometers above the substrate 210. In some embodiments, the upper portion of the n-type silicon carbide drift region 220 may include a more heavily doped n-type silicon carbide current spreading layer than the lower portion of the n-type silicon carbide drift region 220.

[0068] The upper part of the n-type silicon carbide drift region 220 can be p-type doped by ion implantation to form a p-well 240. The p-well 240 can have, for example, a density of 5 x 10⁻⁶. 16 / cm 3 and 5x10 19 / cm 3 The doping concentration between [variable values]. The upper portion 242 of each p-well 240 can be more heavily doped with a p-type dopant. The upper portion 242 of each p-well 240 can have, for example, a doping concentration of 2 x 10 [units]. 18 / cm 3 and 1x10 20 / cm 3 The doping concentration varies between different levels. The p-well 240 (including its more heavily doped upper portion 242) can be formed by ion implantation. As those skilled in the art know, ions such as n-type or p-type dopants can be implanted into a semiconductor layer or region by ionizing a desired ion species and accelerating the ions as an ion beam towards the surface of the semiconductor layer in the ion implantation target chamber with a predetermined kinetic energy. Based on the predetermined kinetic energy, the desired ion species can penetrate into the semiconductor layer to a certain depth.

[0069] In the active region 102, heavily doped (n +The n-type silicon carbide source region 250 can be formed in the upper part of the p-well 240, directly adjacent to and in contact with the heavily doped portion 242 of the p-well 240. The n-type source region 250 can also be formed by ion implantation. Heavily doped (n... + The n-type silicon carbide region 250 serves as the source region of the unit cell transistor 200. The drift region 220 and the substrate 210 together serve as the common drain region of the unit cell transistor 200.

[0070] The n-type silicon carbide substrate 210, the n-type silicon carbide drift region 220, the p-wells 240 and 242, and the n-type source region 250 formed therein can together constitute the semiconductor layer structure of the MOSFET device 100.

[0071] A gate insulating pattern 260 may be formed on the upper surface of the semiconductor layer structure, over the exposed portion of the drift region 220 between the p-well 240 and the n-type source region 250 and extending to the edges of the p-well 240 and the n-type source region 250. The gate insulating pattern 260 may include, for example, a silicon oxide layer, but other insulating materials may be used. Gate fingers 134 are formed on the gate insulating pattern 260. It will be appreciated that the gate fingers 134 may be a continuous gate electrode pattern 130 including a gate pad 132, a plurality of gate fingers 134, and one or more gate buses 136 (see [link to documentation]). Figure 2B In some embodiments, the gate electrode pattern 130 may include, for example, a semiconductor pattern (e.g., polysilicon) and / or a metal gate pattern.

[0072] Source contact 280 can be formed on the n-type source region 250 and the heavily doped portion 242 of the p-well. (See above reference.) Figure 2A-2B The source contact 280 may be part of a continuous source metal pattern 123 extending across the upper surface of the silicon carbide semiconductor layer structure. The remainder of the source metal pattern 123 (and the insulating layer that electrically isolates the gate finger 270 from the source metal pattern 123) is not present. Figure 3A The figures are shown in a simplified manner. The source contact 280 may comprise a thin stack of, for example, metals (such as nickel, titanium, tungsten, or aluminum), alloys, or these or similar materials. As described above, the drain contact 124 may be formed on the lower surface of the substrate 210. The drain contact 124 may comprise, for example, a material similar to that of the source contact 280, as this forms an ohmic contact with the silicon carbide substrate. When a voltage is applied to the gate finger 134, current can flow from the n-type source region 250 through the drift region 220 beneath the gate finger 134.

[0073] Although MOSFET 100 is shown as an n-type device with source contact 280 on its upper surface and drain contact 124 on its bottom surface, it will be appreciated that in a p-type device, these positions are reversed. Therefore, in the following description (including the claims), source contact and drain contact may generally refer to either source contact or drain contact.

[0074] like Figure 3A As shown, in the gate pad portion 106 of the non-active region, a p-well 244 extends beneath most or all of the gate pad portion 106 of the non-active region. The p-well 244 may extend a significant distance in each horizontal direction beneath the gate pad portion 106, such as a distance between 100 and 300 micrometers in each direction. A field insulating layer 264 is formed on the p-well 244 in the gate pad portion 106 of the non-active region 104. In some embodiments, the field insulating layer 264 may have a thickness of, for example, 600-800 nanometers in the vertical direction (i.e., in the direction perpendicular to the main surface of the substrate 210). A gate pad 132 is formed on the field insulating layer 264. (Refer to the above...) Figure 2B As discussed, the gate pad 132 and gate finger 134 may be part of a continuous gate electrode pattern 130.

[0075] In some embodiments, the additional source contact 284 may penetrate the field insulating layer 264 to contact the p-well 244. The additional source contact 284 can help manage the displacement current of the MOSFET device 100, as discussed in U.S. Patent Application No. 15 / 699,149, filed September 8, 2017, entitled “Power Switching Devices with DV / DT Capability and Methods of Making such Devices,” the entire contents of which are incorporated herein by reference. In some embodiments, the additional source contact 284 may be omitted.

[0076] An isolation layer 230 may be formed on the gate finger 134 and / or the gate pad 132. The isolation layer 230 may be used to isolate the gate electrode pattern 130 (including the gate finger 134 and the gate pad 132) from the source metal pattern 123 (including the source contact 280 and additional source contact 284).

[0077] A gate barrier layer 310 may be deployed between gate bonding pad 120 and gate pad 132. The gate barrier layer 310 may serve as a metallization barrier layer and / or an adhesion layer. Similarly, a source barrier layer 320 may be deployed between source contact 280 and source / drain region 250 and / or between additional source contact 284 and p-well 244. The gate barrier layer 310 and / or source barrier layer 320 may reduce and / or prevent metal diffusion from the respective contacts into the underlying material on which the barrier layer is placed. For example, the gate barrier layer 310 may reduce the diffusion of metal material from the metal of gate bonding pad 120 to the polysilicon of gate pad 132. Elements diffused into the polysilicon may further diffuse into the gate oxide and / or active regions, thereby impairing the performance of the MOSFET device 100.

[0078] refer to Figure 3B and 3C In conventional devices, gate contacts and / or source contacts are formed by etching a portion of the device (e.g., isolation layer 230) to form contact holes 375. Barrier layers (e.g., gate barrier layer 310 and / or source barrier layer 320) can be formed within the contact holes 375. Metal for the contacts can then be formed on the barrier layer. However, due to the stepped coverage associated with the formation of the barrier layer, the corners of the contact holes 375 will have poor coverage. For example, see reference... Figure 3B The region 385 of the gate barrier layer 310 will be thinner at the corner of the contact hole 375 between the gate bonding pad 120 and the gate pad 132. Similarly, see reference... Figure 3C Region 386 of the source barrier layer 320 is thin at the corner of the contact hole 375 between the source contact 280 and the source region 250. Because the corner regions 385, 386 of the source and gate contact holes 375 are thin, conventional devices may be susceptible to diffusion from the metal layers of the gate bonding pad 120 and / or the source contact 280.

[0079] Figure 4A A semiconductor device 400 according to some embodiments described herein is illustrated. Figure 4B yes Figure 4A A schematic cross-sectional view of part A. Figure 4C An additional semiconductor device 400' according to some embodiments described herein is illustrated. For brevity, details of the additional semiconductor device 400' will be omitted. Figures 4A-4C Zhongyu Figures 3A-3C The description of those elements that are the same as or similar to the elements in the text. Therefore, Figures 4A-4C The description will focus on the differences from those devices previously described.

[0080] refer to Figure 4A and 4BCompared to conventional devices, the MOSFET device 400 according to some embodiments described herein may include additional barrier layers. For example, the MOSFET device 400 may include an auxiliary gate pad barrier layer 410 and an auxiliary gate electrode barrier layer 420.

[0081] An auxiliary gate pad barrier layer 410 may be formed on the gate pad 132 and may be on the upper surface 132a of the gate pad 132, and in some embodiments cover the upper surface 132a of the gate pad 132. Figure 4B In the diagram, the auxiliary gate pad barrier layer 410 is shown with a separate shade to aid in identification relative to the gate barrier layer 310, but this separate shade is not intended to limit or restrict the configuration of the auxiliary gate pad barrier layer 410 or the gate barrier layer 310. An auxiliary gate pad barrier layer 410 may be provided in addition to the gate barrier layer 310. Therefore, the barrier layer will be present above (e.g., in the form of the gate barrier layer 310) and below (e.g., in the form of the auxiliary gate pad barrier layer 410) the isolation device and the isolation layer 230 of the gate bonding pad 120. In some embodiments, the gate barrier layer 310 may be on and / or in contact with the auxiliary gate pad barrier layer 410 in a portion of the MOSFET device 400 between the gate bonding pad 120 and the gate pad 132 (e.g., in the vertical direction). In some embodiments, the isolation layer 230 may be between the auxiliary gate pad barrier layer 410 and the gate barrier layer 310 and / or the gate bonding pad 120. In some embodiments, the isolation layer 230 may be on the top surface of a portion of the auxiliary gate pad barrier layer 410 and on the sidewall of the gate barrier layer 310.

[0082] The presence of the auxiliary gate pad barrier layer 410 can improve barrier layer coverage at the bottom corner region 385 between the gate bonding pad 120 and the gate pad 132. For example, the width of the auxiliary gate pad barrier layer 410 in a direction parallel to the top surface of the substrate 210 (e.g., in the horizontal direction) can exceed the width of the gate barrier layer 310 in the portion between the auxiliary gate pad barrier layer 410 and the bottom of the gate bonding pad 120 (e.g., the portion of the gate barrier layer 310 extending between the sidewalls of the contact holes connecting the gate bonding pad 120 to the gate pad 132). Therefore, even if the deposition of the gate barrier layer 310 at the bottom corner region 385 is not ideal, the underlying layer (here, the gate pad 132) can be protected from any elements in the contact metal.

[0083] An auxiliary gate electrode barrier layer 420 may also be provided on the gate finger 134 in the active region 102 of the MOSFET device 400. Similar to the auxiliary gate pad barrier layer 410, the auxiliary gate electrode barrier layer 420 may be used for the purpose of blocking the diffusion of elements that may diffuse at the gate electrode interface with the material on top of it, improving layer conductivity and / or enhancing the adhesion of the gate finger 134 to the dielectric layer on top of it.

[0084] When an auxiliary gate electrode barrier layer 420 is present, the barrier layer will exist below (e.g., in the form of the auxiliary gate electrode barrier layer 420) and above (e.g., in the form of the source barrier layer 320) the isolation layer 230 that isolates the gate finger 134 from the source metal pattern 123. In some embodiments, the auxiliary gate electrode barrier layer 420 may be located between the upper surface 134a of the gate finger 134 and the isolation layer 230.

[0085] The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be applied in various ways to produce continuous or adjacent layers with a thickness of 0.5 nm to 500 nm. In some embodiments, the thickness of the auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be substantially uniform. The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and other metal nitrides and / or intermetallic compounds, including, for example, cobalt (Co), ruthenium (Ru), etc. The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 can be a single layer (such as TiN, TaN, or similar materials with good thermodynamic stability and conductivity), or a multilayer stack of various elements or compound materials in various stacking orders. Thus, although Figure 4A and 4B The illustration shows a single layer for the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420, but the structure shown is intended to also represent a multilayer structure. In some embodiments, conductive oxides may be used where adhesion to the dielectric layer is important. As will be understood by those skilled in the art, the materials used will depend on the processing and application. The auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 may be applied as needed to improve diffusion blocking, conductivity, and / or adhesion properties.

[0086] In some embodiments, the material and / or configuration of the auxiliary gate pad barrier layer 410 may differ from the material and / or configuration of the auxiliary gate electrode barrier layer 420. In some embodiments, the material and / or configuration of the auxiliary gate pad barrier layer 410 may differ from the material and / or configuration of the gate barrier layer 310. In some embodiments, the material and / or configuration of the auxiliary gate electrode barrier layer 420 may differ from the material and / or configuration of the gate barrier layer 310.

[0087] In some embodiments, an auxiliary gate pad barrier layer 410 may be present, and an auxiliary gate electrode barrier layer 420 may be omitted. For example, Figure 4C The illustration shows a MOSFET device 400' in which the auxiliary gate electrode barrier layer 420 is absent.

[0088] Figure 5A and 5B Additional semiconductor devices according to some embodiments described herein are shown. For the sake of brevity, details regarding... Figure 5A and 5B The description of those elements that are the same as or similar to the elements in the previously described figures. Therefore, Figure 5A and 5B The description will focus on the differences from those devices previously described.

[0089] refer to Figure 5A In a MOSFET device 500 according to some embodiments, an auxiliary gate pad barrier layer 410' may extend on the top surface 132a and one or more sidewalls 132b of the gate pad 132. Thus, the auxiliary gate pad barrier layer 410' may extend continuously on the top surface and side surface of the gate pad 132.

[0090] Similarly, the auxiliary gate electrode barrier layer 420' may extend onto one or more sidewalls 134b of the gate finger 134. Thus, the auxiliary gate electrode barrier layer 420' may extend continuously on the top and side surfaces of the gate finger 134.

[0091] The use of auxiliary gate pad barrier layer 410' and / or auxiliary gate electrode barrier layer 420' can increase the diffusion barrier of gate pad 132 and / or gate finger 134. In addition, auxiliary gate pad barrier layer 410' and / or auxiliary gate electrode barrier layer 420' can improve adhesion to the corresponding gate pad 132 and / or gate finger 134.

[0092] As previously mentioned, in some embodiments, an auxiliary gate pad barrier layer 410' may be present and the auxiliary gate electrode barrier layer 420' may be omitted. For example, Figure 5BThe illustration shows a MOSFET device 500' in which the auxiliary gate electrode barrier layer 420' is absent.

[0093] Figure 6A An additional semiconductor device 600 is illustrated according to some embodiments described herein. Figure 6B yes Figure 6A A schematic cross-sectional view of part B. Figures 6C to 6E Additional semiconductor devices according to some embodiments described herein are illustrated. For brevity, details regarding... Figures 6A to 6E The description of those elements that are the same as or similar to those in the aforementioned figures. Therefore, Figures 6A to 6E The description will focus on the differences from those devices previously described.

[0094] refer to Figure 6A and 6B The MOSFET device 600 may include an auxiliary source barrier layer 620. The auxiliary source barrier layer 620 may be formed on a semiconductor structure and may be formed on a more heavily doped portion 242 of the n-type source region 250 and / or the p-well. In addition to the source barrier layer 320, the auxiliary source barrier layer 620 may also be provided. Figure 6B In the diagram, the auxiliary source barrier layer 620 is shown in a separate shade to aid in identification relative to the source barrier layer 320, but this separate shade is not intended to limit the configuration of the auxiliary source barrier layer 620 or the source barrier layer 320. In some embodiments, the source barrier layer 320 may be in contact with and on the auxiliary source barrier layer 620 in a portion of the MOSFET device 600 between the source contact 280 and a more heavily doped portion 242 of the semiconductor structure including the heavily doped n-type source region 250 and the p-well.

[0095] like Figure 6B As shown, in some embodiments, the auxiliary source barrier layer 620 may extend beyond the source barrier layer 320 located on the sidewall of the source contact 280. In some embodiments, a portion of the isolation layer 230 may be between a portion of the auxiliary source barrier layer 620 and the source barrier layer 320. The use of the auxiliary source barrier layer 620 may provide additional diffusion protection between the source contact 280 and the semiconductor structure including the heavily doped portion 242 of the n-type source region 250 and / or p-well. For example, the auxiliary source barrier layer 620 may be used to reinforce the region 686 at the corner of the source contact 280.

[0096] refer to Figure 6A The MOSFET device 600 may include... Figures 4A to 4CThe auxiliary gate pad barrier layer 410 and / or the auxiliary gate electrode barrier layer 420 shown are used in combination to utilize the auxiliary source barrier layer 620, but this disclosure is not limited thereto. In some embodiments, the auxiliary source barrier layer 620 may be used independently of one or more of the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420.

[0097] Figure 6C The diagram illustrates the auxiliary source barrier layer 620 and its relationship to the topic discussed in this paper. Figure 5A and 5B An embodiment in which the auxiliary gate pad barrier layer 410' and the auxiliary gate electrode barrier layer 420' are used in combination is discussed. Figures 6A to 6C An auxiliary source barrier layer 620 is illustrated for use with an auxiliary gate electrode barrier layer 420, but the embodiments described herein are not limited thereto. Figure 6D and 6E The illustration shows the use of the auxiliary source barrier layer 620 and the auxiliary gate pad barrier layers 410, 410', but the auxiliary gate electrode barrier layers 420, 420' are not present.

[0098] Therefore, it will be understood that, without departing from the scope of the embodiments described herein, the auxiliary gate pad barrier layer 410, the auxiliary gate pad barrier layer 410', the auxiliary gate electrode barrier layer 420, the auxiliary gate electrode barrier layer 420', and the auxiliary source barrier layer 620 can be used independently of each other and in various combinations.

[0099] Figure 7-12 A method for manufacturing a semiconductor device according to an embodiment described herein is illustrated.

[0100] refer to Figure 7 A substrate 210 is provided, and a drift region 220 is formed on the substrate 210 by epitaxial growth. In some embodiments, the substrate 210 is heavily doped (n... + n-type silicon carbide and the drift region 220 is lightly doped (n - Silicon carbide drift region 220. In some embodiments, an n-type silicon carbide current spreading layer may be formed, including the upper part of the drift layer 220.

[0101] P-well 240 can be formed in the active region 102 of the final device, and p-well 244 can be formed in the non-active region 106 of the final device. In the active region 102, the upper portion 242 of each p-well 240 can be more heavily doped with a p-type dopant, and the heavily doped (n...) + The n-type silicon carbide source region 250 can be formed in the upper part of the p-well 240, which is directly adjacent to and in contact with the heavily doped portion 242 of the p-well 240. Heavily doped (n... +The n-type silicon carbide region 250 serves as the source region 200 of the unit cell transistor. In some embodiments, ion implantation may be used to form p-wells 240, 244 and the n-type source region 250.

[0102] In the active region 102, a gate insulating layer may be formed on the upper surface of the semiconductor layer structure. The gate insulating layer may be patterned and etched to form a gate insulating pattern 260 over the exposed portion of the drift region 220 and extending to the edges of the p-well 240 and the n-type source region 250. In the non-active region 106, a field insulating layer 264 may be formed on the p-well 244.

[0103] Conductive materials such as polysilicon can be formed on the field insulating layer 264 and the gate insulating pattern 260. The conductive material can be patterned and etched to form the gate pads 132 and the gate fingers 134. The gate pads 132 and the gate fingers 134 can be electrically coupled to each other.

[0104] refer to Figure 8 An auxiliary barrier layer 810 may be formed on the gate finger 134 and the gate pad 132. In some embodiments, the auxiliary barrier layer 810 may extend on the respective sidewalls of the gate finger 134 and the gate pad 132. In some embodiments, the auxiliary barrier layer 810 may be formed on the more heavily doped portion 242 of the n-type source region 250 and the p-well.

[0105] The auxiliary barrier layer 810 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), and other metal nitrides and / or intermetallic compounds, including, for example, cobalt (Co) and ruthenium (Ru). The auxiliary barrier layer 810 may be a single layer (such as TiN, TaN, or similar materials with good thermodynamic stability and electrical conductivity), or a multilayer stack of various elements or compound materials in various stacking orders. Therefore, although... Figure 8 The illustration shows a single layer for the auxiliary barrier layer 810, but the structure shown is intended to also represent a structure that includes multiple layers.

[0106] Although shown to cover both active region 102 and non-active region 106, it will be understood that embodiments of this disclosure are not limited to this configuration. In some embodiments, the auxiliary barrier layer 810 may be formed only in the non-active region 106. In other words, in some embodiments, the auxiliary barrier layer 810 may be formed only on the gate pad 132.

[0107] The auxiliary barrier layer 810 can then be patterned and etched using standard techniques to form auxiliary barrier layers according to various embodiments described herein. For example, refer to Figure 9AThe auxiliary barrier layer 810 can be patterned and etched to remove all portions of the auxiliary barrier layer 810 except those above the gate pad 132 and the gate finger 134. In this way, the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420 can be formed, such as... Figure 4A As shown in the figures. In some embodiments, a portion of the field insulating layer 264 may also be removed as part of forming the auxiliary gate pad barrier layer 410, but the embodiments described herein are not limited thereto.

[0108] refer to Figure 9B The auxiliary barrier layer 810 can alternatively be patterned and etched to remove all portions of the auxiliary barrier layer 810 except those above the gate pad 132 and the gate finger 134. For example... Figure 9B As shown, etching can be performed to leave portions of the auxiliary barrier layer 810 on the sidewalls of the gate pad 132 and the gate finger 134. In this way, an auxiliary gate pad barrier layer 410' and an auxiliary gate electrode barrier layer 420' can be formed, such as... Figure 5A Those shown in the image.

[0109] In some embodiments, the auxiliary barrier layer 810 or another layer may be patterned and etched to leave portions of the auxiliary barrier layer 810 on the n-type source region 250, the more heavily doped portion 242 of the p-well, and / or the p-well 244. In this way, an auxiliary source barrier layer 620 may be formed, such as... Figure 6A Those shown in the image. Figure 9C The illustration shows an embodiment in which the auxiliary barrier layer 810 is patterned and etched to form an auxiliary source barrier layer 620 together with an auxiliary gate pad barrier layer 410 and an auxiliary gate electrode barrier layer 420. Figure 9D The illustration shows an embodiment in which the auxiliary barrier layer 810 is patterned and etched to form an auxiliary source barrier layer 620 together with an auxiliary gate pad barrier layer 410' and an auxiliary gate electrode barrier layer 420'.

[0110] In some embodiments, additional patterning steps may be performed on the field insulating layer 264 to form an auxiliary source blocking layer 620. For example, refer back to Figure 8In some embodiments, portions of the field insulating layer 264 and the auxiliary barrier layer 810 may be patterned and etched to expose the upper surface of the n-type source region 250, the more heavily doped portion 242 of the p-well, and / or the p-well 244. Additional barrier layer material may then be deposited in the exposed regions to form the auxiliary source barrier layer 620. In some embodiments, the barrier layer material used to form the auxiliary source barrier layer 620 may be the same as the material used to form the auxiliary gate pad barrier layer 410 and the auxiliary gate electrode barrier layer 420, but the embodiments described herein are not limited thereto. Additional mechanisms for forming the auxiliary gate pad barrier layer 410, the auxiliary gate electrode barrier layer 420, and the auxiliary source barrier layer 620 will be recognized by those skilled in the art, and the embodiments described herein are not limited to those shown in the figures.

[0111] After the auxiliary barrier layer is formed, additional processing can be performed to produce one or more of the MOSFET devices described herein. Figure 10-12 The main focus is on forming a consensus on Figure 4A The process described herein is based on the MOSFET device 400. However, it will be understood that the process described herein can be modified with necessary changes to implement additional embodiments of the device described herein, without limitation.

[0112] refer to Figure 10 The isolation layer 230 may be formed on the gate finger 134, gate pad 132, field insulating layer 264, auxiliary gate pad barrier layer 410, and auxiliary gate electrode barrier layer 420. The isolation layer 230 may be an IMD (intermetallic dielectric) layer or an ILD (interlayer dielectric) layer. In some embodiments, the isolation layer 230 may include the same or similar material as the field insulating layer 264, but the embodiments described herein are not limited thereto.

[0113] refer to Figure 11 The isolation layer 230 is patterned and etched to form contact holes 1010 for source contacts and contact holes 1020 for gate bonding pads. Contact holes 1020 may expose portions of the auxiliary gate pad barrier layer 410. In some embodiments, the auxiliary gate pad barrier layer 410 may extend beyond the sidewalls of the contact holes 1020. Contact holes 1010 may expose portions of the semiconductor structure, such as the more heavily doped portions 242 of the n-type source region 250 and / or the p-well 240. In embodiments where the auxiliary source barrier layer 620 is present (see, for example...), Figure 9C and 9D Contact hole 1010 can expose auxiliary source barrier layer 620.

[0114] refer to Figure 12A barrier layer 1210 can be formed on the isolation layer 230 and within the contact holes 1010 and 1020. The barrier layer 1210 can be on the sidewalls and bottom of the contact holes 1010 and 1020. The barrier layer 1210 can also be formed on a portion of the auxiliary gate pad barrier layer 410 exposed by the contact hole 1020. In embodiments where an auxiliary source barrier layer 620 is present (see, for example...), Figure 9C and 9D The barrier layer 1210 can be formed on the auxiliary source barrier layer 620 exposed by the contact hole 1010.

[0115] Go back to reference Figure 4A A metal contact layer can be formed on the active region 102 and the non-active region 104. The metal contact layer can be patterned and etched to form the gate bonding pad 120 and the source metal pattern 123. Etching of the metal contact layer can also separate the barrier layer 1210 into the gate barrier layer 310 and the source barrier layer 320.

[0116] The power switching device according to the embodiments disclosed herein can provide significantly improved performance. By reducing the diffusion of material into the active region of the device and / or increasing the adhesion between the metal layer and other conductive parts of the device, the overall structure of the device can be improved and defects can be reduced and / or eliminated.

[0117] It will be appreciated that the specific layer structures, doping concentrations, materials, conductivity types, etc., shown in the figures and / or described herein are provided merely as examples to illustrate the structures of particular exemplary embodiments. Therefore, the specific details discussed below are not limited to the present invention.

[0118] In this document, embodiments of the invention are described with respect to cross-sectional views showing one or two unit cells of a power switching device. It will be appreciated that practical implementations will typically include a greater number of unit cells. However, it will also be appreciated that the invention is not limited to such devices, and the appended claims also cover MOSFETs and other power switching devices comprising, for example, a single unit cell. Furthermore, while this disclosure focuses on silicon carbide devices, it will be appreciated that embodiments of the invention are also applicable to devices formed using other wide-bandgap semiconductors, such as, for example, gallium nitride, zinc selenide, or any other II-VI or III-V wide-bandgap compound semiconductors.

[0119] While the preceding figures illustrate the structure of an n-channel MOSFET unit cell, it will be appreciated that, according to further embodiments of the invention, the polarity of each semiconductor layer in each device can be reversed to provide a corresponding p-channel MOSFET.

[0120] The invention has been described above with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. It will be understood that when an element or layer is referred to as “on another element or layer,” “connected to another element or layer,” or “coupled to another element or layer,” it may be directly on, connected to, or coupled to another element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as “directly on another element or layer,” “directly connected to another element or layer,” or “directly coupled to another element or layer,” there are no intermediate elements or layers. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. The same reference numerals always refer to the same element.

[0121] It will be understood that while the terms "first" and "second" are used herein to describe various regions, layers, and / or elements, these regions, layers, and / or elements should not be limited by these terms. These terms are used only to distinguish one region, layer, or element from another. Therefore, the first region, layer, or element discussed below may be referred to as the second region, layer, or element, and similarly, the second region, layer, or element may be referred to as the first region, layer, or element without departing from the scope of the invention.

[0122] Relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another, as illustrated in the figures. It will be understood that relative terms are intended to cover different orientations of the device other than those depicted in the figures. For example, if the device in the figures is flipped, then the element described as being “down” to another element will be oriented “up” to the other element. Thus, the exemplary term “down” can include both “down” and “up” orientations depending on the specific orientation of the figure. Similarly, if one of the devices in the figures is flipped, then the element described as being “below” or “under” another element will be oriented “above” the other element. Thus, the exemplary term “below” or “under” can include both “up” and “down” orientations.

[0123] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that, when used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” designate the presence of the stated features, elements, and / or components, but do not preclude the presence or addition of one or more other features, elements, components, and / or groups thereof.

[0124] Embodiments of the invention are described herein with reference to cross-sectional views, which are schematic diagrams. Accordingly, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be construed as limited to the specific shapes of the regions shown herein, but should include, for example, shape deviations caused by manufacturing processes. For instance, an injection region illustrated as rectangular will typically have rounded or curved features at its edges and / or an injection concentration gradient, rather than a binary change from an injection region to a non-injection region. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0125] It will be understood that the embodiments disclosed herein can be combined. Therefore, features depicted and / or described with respect to the first embodiment can also be included in the second embodiment, and vice versa.

[0126] While the embodiments described above have been referenced to specific accompanying drawings, it should be understood that some embodiments of the invention may include additional and / or intermediate layers, structures, or elements, and / or certain layers, structures, or elements may be removed. Although several exemplary embodiments of the invention have been described, those skilled in the art will readily recognize that many modifications can be made to the exemplary embodiments without materially departing from the novel teachings and advantages of the invention. Therefore, all such modifications are intended to be included within the scope of the invention as defined in the claims. Consequently, it should be understood that the foregoing is illustrative of the invention and should not be construed as limiting it to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims. The invention is defined by the following claims, including equivalents of the claims.

Claims

1. A semiconductor device, comprising: A semiconductor layer structure includes an active region and an active region, wherein the active region includes a plurality of unit cells and the active region includes a gate pad on the semiconductor layer structure and a gate bonding pad on the gate pad and electrically connected to the gate pad. An isolation layer is located between the gate pad and the gate bonding pad; The first barrier layer is located between the gate pad and the isolation layer; as well as The second barrier layer is located on the first barrier layer between the gate bonding pad and the first barrier layer. At least a portion of the isolation layer is located between the first barrier layer and the second barrier layer.

2. The semiconductor device of claim 1, wherein the first barrier layer comprises multiple layers.

3. The semiconductor device of claim 1 or claim 2, wherein the first barrier layer comprises titanium (Ti) and / or tantalum (Ta).

4. The semiconductor device of claim 1 or claim 2, wherein the first barrier layer is located on the top surface and sidewall of the gate pad.

5. The semiconductor device of claim 1, further comprising: The gate finger is located on the active region and electrically connected to the gate bonding pad; as well as The third barrier layer is located on the gate finger.

6. The semiconductor device of claim 5, wherein the third barrier layer is located on the top surface and sidewall of the gate finger.

7. The semiconductor device of claim 1, further comprising: The source contact is located on the semiconductor layer structure; The third barrier layer is located on the sidewalls and bottom surface of the source contact; as well as The fourth barrier layer is located between the semiconductor layer structure and the third barrier layer.

8. A semiconductor device, comprising: Semiconductor substrate; Gate pads are located on the semiconductor substrate; Gate bonding pad, located on the gate pad and electrically connected to the gate pad; A first barrier layer is located between the bottom of the gate bonding pad and the gate pad in a first direction perpendicular to the top surface of the semiconductor substrate; and The second barrier layer is located between the gate pad and the first barrier layer in the first direction. The gate bonding pad is coupled to the gate pad via a contact hole having opposing sidewalls, and A portion of the first barrier layer extends on the opposite sidewall of the contact hole.

9. The semiconductor device of claim 8, wherein the width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate exceeds the width of the portion of the first barrier layer between the bottom of the second barrier layer and the gate bonding pad.

10. The semiconductor device of claim 9, wherein the thickness of the second barrier layer is substantially uniform along the width of the second barrier layer in the second direction.

11. The semiconductor device according to any one of claims 8-10, The width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate is greater than the width of the contact hole in the second direction.

12. The semiconductor device of any one of claims 8-10, further comprising an isolation layer, wherein a portion of the isolation layer is located between the second barrier layer and the gate bonding pad.

13. The semiconductor device according to any one of claims 8-10, wherein the second barrier layer comprises multiple layers.

14. The semiconductor device according to any one of claims 8-10, wherein the second barrier layer comprises titanium (Ti) and / or tantalum (Ta).

15. The semiconductor device according to any one of claims 8-10, wherein the second barrier layer is located on the top surface and sidewall of the gate pad.

16. The semiconductor device according to any one of claims 8-10, wherein the material of the second barrier layer is different from the material of the first barrier layer.

17. The semiconductor device according to any one of claims 8-10, further comprising: A semiconductor layer structure, comprising active and non-active regions, wherein the gate pad is located on the non-active region; The gate finger is located on the active region and is electrically connected to the gate pad; as well as The third barrier layer is located on the gate finger.

18. The semiconductor device of claim 17, wherein the third barrier layer is located on the top surface and sidewall of the gate finger.

19. A semiconductor device, comprising: Semiconductor substrate; Gate pads are located on the semiconductor substrate; An isolation layer is located on the gate pad; The first barrier layer is located on the isolation layer and the gate pad; as well as A second barrier layer is located between the gate pad and the first barrier layer in a first direction perpendicular to the top surface of the semiconductor substrate, and the width of the second barrier layer in a second direction parallel to the top surface of the semiconductor substrate exceeds the width of the first barrier layer in the second direction. At least a portion of the isolation layer is located between the first barrier layer and the second barrier layer in a first direction.

20. The semiconductor device of claim 19, further comprising a gate bonding pad located on the gate pad and electrically connected to the gate pad via a contact hole having opposing sidewalls in an isolation layer. The first barrier layer includes a first portion extending in a second direction between opposite sidewalls of the contact hole, and The width of the second barrier layer in the second direction exceeds the width of the first portion of the first barrier layer in the second direction.

21. The semiconductor device of claim 20, wherein a portion of the isolation layer is between the second barrier layer and the gate bonding pad.

22. The semiconductor device according to any one of claims 19-21, wherein the isolation layer is on the top surface of the second barrier layer and on the sidewall of the first barrier layer.

23. A semiconductor device, comprising: Semiconductor layer structure; A plurality of unit cell transistors are connected in parallel, each unit cell transistor including a gate finger extending in a first direction on the top surface of a semiconductor layer structure, the gate fingers being spaced apart from each other along a second direction, wherein the first direction and the second direction are parallel to the top surface of the semiconductor layer structure and perpendicular to each other; as well as An auxiliary gate electrode blocking layer is located on the upper surface and opposite sidewalls of each of the gate fingers.

24. The semiconductor device of claim 23, wherein the gate finger comprises polysilicon.

25. The semiconductor device of claim 23 or claim 24, wherein the auxiliary gate electrode barrier layer comprises titanium (Ti) and / or tantalum (Ta).

26. The semiconductor device of claim 23 or claim 24, wherein the semiconductor layer structure includes an active region and an active region. The active region includes the plurality of unit cell transistors, and The non-active region includes: Gate pads on a semiconductor layer structure; Gate bonding pads on the gate pads and electrically connected to the gate pads; The isolation layer between the gate pad and the gate bonding pad; as well as Auxiliary gate pad barrier layer between the gate pad and the isolation layer.

27. The semiconductor device of claim 26, wherein the auxiliary gate pad barrier layer is located on the top surface and sidewall of the gate pad.

28. The semiconductor device of claim 26, further comprising a gate pad barrier layer located between the auxiliary gate pad barrier layer and the gate bonding pad.

29. The semiconductor device of claim 23 or claim 24, wherein the auxiliary gate electrode barrier layer comprises multiple layers.

30. The semiconductor device of claim 23 or claim 24, further comprising: The source contact is located on the semiconductor layer structure; The source barrier layer is located on the sidewalls and bottom surface of the source contacts; as well as The auxiliary source barrier layer is located between the semiconductor layer structure and the source barrier layer.

31. The semiconductor device of claim 23, further comprising an isolation layer located on the gate finger. The auxiliary gate electrode barrier layer is located between the isolation layer and the gate finger.

Images