A page table creation method, a processor verification method, an apparatus, and an electronic device

Abstract

Embodiments of the present application disclose a page table creation method, a processor verification method, a device and an electronic device, and relate to the technical field of processor verification, and are invented to improve the efficiency of processor verification. The method comprises the following steps: determining a virtual address range to be converted according to a maximum access memory address required by a preset test code; applying for an address space required by each level of page table according to the virtual address range; initializing each level of page table to fill a base address of a next level of page table into a page table entry of a previous level of page table, and filling high bits of a virtual address into a page table entry of a last level of page table; wherein the high bits of the virtual address are bit positions of the virtual address except for page-in offset bit positions. The present application is suitable for verifying a processor.

Description

Technical Field

[0001] This application relates to the field of processor verification technology, and in particular to a page table creation method, a processor verification method, an apparatus, an electronic device, and a readable storage medium. Background Technology

[0002] Paging plays a crucial role in processors. Before enabling paging, the system needs to initialize the corresponding page tables, typically by dynamically allocating a memory space to store them. These page tables enable the translation of virtual addresses into physical addresses. During processor verification, numerous page faults are generated, interrupting the verification process and triggering page fault service routines that require allocating the necessary page tables. These routines significantly reduce the processor's verification efficiency. Summary of the Invention

[0003] In view of this, embodiments of this application provide a page table creation method, a processor verification method, an apparatus, an electronic device, and a readable storage medium to improve processor verification efficiency.

[0004] In a first aspect, embodiments of this application provide a page table creation method, comprising: determining the virtual address range to be converted based on the maximum memory address required by a preset test code; allocating the required address space for each level of page table based on the virtual address range; initializing each level of page table to fill the base address of the next level page table into the page table entry of the previous level page table, and filling the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits.

[0005] According to a specific implementation of an embodiment of this application, the initialized page tables at each level are used to verify the processor; before allocating the required address space for each level of page tables, the method further includes: selecting a paging mode and a page size; and determining the page table translation level based on the kernel operating mode, paging mode, and page size of the processor to be verified, as well as a pre-established mapping relationship between the operating mode, paging mode, page size, and page table translation level.

[0006] According to a specific implementation of an embodiment of this application, selecting the paging mode includes: selecting the paging mode according to the kernel running mode.

[0007] According to a specific implementation of an embodiment of this application, selecting the page size includes selecting a page size of 4K, 2M, or 1G.

[0008] According to a specific implementation of an embodiment of this application, the kernel running mode includes: classic running mode or long running mode.

[0009] Secondly, embodiments of this application provide a processor verification method applied to a processor verification system. The verification method includes: determining the maximum memory address accessed by the verification system to determine the virtual address range to be converted; allocating the required address space for each level of page tables according to the virtual address range; initializing each level of page tables to fill the base address of the next level page table into the page table entry of the previous level page table, and filling the high-order bits of the virtual address into the page table entry of the last level page table; wherein the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bit; updating the base address of the first level page table in the CR3 control register and enabling the paging mechanism; and, according to the base address of the first level page table in the CR3 control register and the initialized page tables at each level, the test code obtains data at the target physical address and / or writes data to the target physical address to verify the processor based on the data.

[0010] According to a specific implementation of this application, before allocating the required address space for each level of page table, the method further includes: determining the paging mode and page size to be enabled by the verification system; and determining the page table conversion level based on the kernel running mode, paging mode, and page size entered by the verification system upon startup, as well as the pre-established mapping relationship between the running mode, paging mode, page size, and page table conversion level.

[0011] Thirdly, embodiments of this application provide a page table creation apparatus, comprising: a first determining module, configured to determine the range of virtual addresses to be converted based on the maximum memory address required by a preset test code; a first applying module, configured to apply for the required address space for each level of page table based on the virtual address range; and a first initialization module, configured to initialize each level of page table, such that the base address of the next level page table is filled into the page table entry of the previous level page table, and the high-order bits of the virtual address are filled into the page table entry of the last level page table; wherein the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits.

[0012] According to a specific implementation of an embodiment of this application, the apparatus further includes: a selection module, configured to select a paging mode and a page size before the first application module allocates the required address space for each level of page table; and a second determination module, configured to determine the page table conversion level based on the processor's kernel operating mode, paging mode, and page size, as well as a pre-established mapping relationship between the operating mode, paging mode, page size, and page table conversion level.

[0013] According to a specific implementation of an embodiment of this application, the selection module is specifically used to: select a paging mode according to the kernel running mode.

[0014] According to a specific implementation of an embodiment of this application, the selection module is specifically used to: select a page size of 4K, 2M, or 1G.

[0015] According to a specific implementation of an embodiment of this application, the kernel running mode includes: classic running mode or long running mode.

[0016] Fourthly, embodiments of this application provide a processor verification device applied to a processor verification system. The verification device includes: a third determining module, used to determine the maximum memory address accessed by the verification system to determine the virtual address range to be converted; a second applying module, used to apply for the required address space for each level of page tables according to the virtual address range; a second initialization module, used to initialize each level of page tables, filling the base address of the next level page table into the page table entry of the previous level page table, and filling the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bit; an updating module, used to update the base address of the first level page table to the CR3 control register and enable the paging mechanism; and a verification module, used to obtain data at the target physical address by test code according to the base address of the first level page table in the CR3 control register and the initialized page tables of each level, and / or write data to the target physical address, so as to verify the processor according to the data.

[0017] According to a specific implementation of an embodiment of this application, the apparatus further includes: a fourth determining module, configured to determine the paging mode and page size to be enabled by the verification system before the second application module requests the address space required for each level of page table; and a fifth determining module, configured to determine the page table conversion level based on the kernel running mode, paging mode, and page size entered by the verification system upon startup, as well as the pre-established mapping relationship between the running mode, paging mode, page size, and page table conversion level.

[0018] Fifthly, embodiments of this application provide an electronic device, the electronic device comprising: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed within the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the page table creation method or the processor verification method described in any of the foregoing implementations.

[0019] Sixthly, embodiments of this application provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement the page table creation method or the processor verification method described in any of the foregoing implementations.

[0020] The page table creation method, processor verification method, apparatus, electronic device, and readable storage medium of this embodiment determine the virtual address range to be converted based on the maximum memory address required by the preset test code, allocate the necessary address space for each level of page table according to the virtual address range, initialize each level of page table, fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table, wherein the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic flowchart illustrating a page table creation method provided in an embodiment of this application;

[0023] Figure 2 A flowchart illustrating a page table creation method provided in a specific embodiment of this application;

[0024] Figure 3 A schematic diagram illustrating the conversion of a virtual address to a physical address according to a specific embodiment of this application;

[0025] Figure 4 A flowchart for executing code for the processor;

[0026] Figure 5 A schematic flowchart of a processor verification method provided in an embodiment of this application;

[0027] Figure 6 A flowchart illustrating a processor verification method provided in a specific embodiment of this application;

[0028] Figure 7 A schematic diagram of the structure of a page table creation apparatus provided in an embodiment of this application;

[0029] Figure 8This is a schematic diagram of the structure of a processor verification device provided in an embodiment of this application;

[0030] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0031] The embodiments of this application will now be described in detail with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0032] To enable those skilled in the art to better understand the technical concept, implementation scheme and beneficial effects of the embodiments of this application, detailed descriptions are provided below through specific embodiments.

[0033] One embodiment of this application provides a page table creation method that facilitates improved processor verification efficiency.

[0034] Figure 1 A flowchart illustrating a page table creation method provided in an embodiment of this application is shown below. Figure 1 As shown, the page table creation method in this embodiment may include:

[0035] S101. Determine the range of virtual addresses to be converted based on the maximum memory address required by the preset test code.

[0036] If the maximum address accessed by the kernel is 0xFFFFFFFF, the range of virtual addresses to be translated can be determined to be 0x0-0xFFFFFFFF, and page tables can be generated for all pages within this range.

[0037] Based on the maximum memory address required by the preset test code, determine the range of virtual addresses to be converted, and then use this range to initialize page tables at all levels.

[0038] S102. Based on the virtual address range, allocate the required address space for each level of page table.

[0039] Based on the virtual address range, the operating system can be requested the memory address space required for each level of page tables. Since each level of page tables resides in physical memory, sufficient memory space needs to be reserved for each level of page tables from the operating system.

[0040] S103. Initialize page tables at all levels to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table.

[0041] During the process of allocating the necessary address space for each level of page table, the base address of each level of page table can be determined. Thus, during the initialization of each level of page table, the base address of the next level page table can be filled into the page table entry of the previous level page table. For example, the base address of the second level page table can be filled into the page table entry of the first level page table.

[0042] In this embodiment, the high-order bits of the virtual address are the bits in the virtual address excluding the offset bits within the page.

[0043] Since the page table entry of the last-level page table stores the base address of the physical address, the physical address corresponding to the virtual address can be obtained by combining the base address with the offset bits in the virtual address. In this embodiment, the last-level page table entry stores the bits in the virtual address excluding the offset bits. Thus, the physical address can be determined based on the bits in the virtual address excluding the offset bits and the offset bits in the page table, that is, the obtained physical address is equal to the virtual address.

[0044] In this embodiment, the virtual address range to be converted is determined based on the maximum memory address required by the preset test code. According to the virtual address range, the necessary address space is allocated for each level of page tables, and each level of page tables is initialized. The base address of the next-level page table is filled into the page table entry of the previous-level page table, and the high-order bits of the virtual address are filled into the page table entry of the last-level page table. The high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits. Since the page table entry of the last-level page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained by combining this base address with the page offset bits in the virtual address, and in this embodiment, the last-level page table entry stores the bits in the virtual address excluding the page offset bits, thus... The physical address can be determined based on the bits in the virtual address excluding the page offset bit and the page offset bit. That is, the obtained physical address is equal to the virtual address, and the range of the virtual address is determined based on the maximum memory address required by the preset test code. In this way, when using the initialized page table to verify the processor, page faults will not occur, improving the processor verification efficiency. This avoids the problem of reduced processor running efficiency caused by a large number of page faults during the test code execution, which would interrupt the execution and enter the page fault handling service routine. In addition, during the development and compilation of processor verification code using the page table of this embodiment, only the physical address or the virtual address can be used. This reduces the development and compilation complexity of the processor verification code and improves the development and compilation efficiency of the processor verification code.

[0045] In some examples, after initializing page tables at each level, the base address of the first-level page table can be updated in the control register CR3 to enable paging mode; the attributes of page table entries at each level, such as read / write attributes, can also be configured.

[0046] Another embodiment of this application is basically the same as the above embodiments, except that in this embodiment, the initialized page tables at each level are used to verify the processor; before allocating the required address space for each level of page tables, the method further includes:

[0047] S104. Select the pagination mode and page size.

[0048] The paging mode is kernel paging mode, where kernel refers to the processor's kernel. Paging modes can include Page Address Extension (PAE) and Non-PAE. In some cases, the paging mode is selected based on the kernel's operating mode. The kernel's operating mode can include 32-bit classic operating mode or 64-bit long operating mode. In classic operating mode, the paging mode can be Non-PAE; in long operating mode, the paging mode can be PAE.

[0049] Page sizes include 4K, 2M, or 1G, and page size affects the number of page table levels required for page table transformation.

[0050] S105. Determine the page table translation level based on the kernel operating mode, paging mode, and page size of the processor to be verified, as well as the pre-established mapping relationship between the operating mode, paging mode, page size, and page table translation level.

[0051] In some cases, the kernel running mode may include either classic running mode or long running mode.

[0052] In this embodiment, the kernel operating mode, paging mode, and page size affect the number of page table levels.

[0053] The pre-established mapping relationship between the operating mode, paging mode, page size, and page table transition level allows the page table transition level to be determined based on the given kernel operating mode, paging mode, and page size.

[0054] The following detailed description of the solution in this application is based on a specific embodiment.

[0055] See Figure 2 The page table creation method in this embodiment may include:

[0056] S11. Select the kernel paging mode and page table size.

[0057] Choose between the kernel paging mode, either Non PAE or PAE, with page table sizes of 4K, 2M, or 1G.

[0058] Non-PAE mode uses 32-bit page table entries, while PAE mode uses 64-bit page table entries; the page table size determines the number of page table entry levels required for page table translation.

[0059] S12. Determine the number of levels in the page table based on the kernel operating mode, paging mode, and page table size.

[0060] For example, if the kernel is running in 32-bit Legacy mode and PAE paging and a 4K page table size are selected, then 3 levels of page tables (PDPE, PDE, PTE) are required.

[0061] S13. Determine the maximum memory address accessed by the kernel to determine the range of virtual addresses that need to be translated.

[0062] For example, if the maximum address accessed by the kernel is 0xFFFFFFFF, then a corresponding page table needs to be generated for all pages in the virtual address range of 0x0-0xFFFFFFFF.

[0063] S14. Allocate the memory address space required for each level of page table.

[0064] Since page tables at all levels reside in physical memory, sufficient memory space needs to be reserved for each level of page table.

[0065] S15. Initialize page tables at all levels.

[0066] Here, you need to fill in the base address of the second-level page table for the first-level page table entry, the base address of the third-level page table for the second-level page table entry, and the high-order bits of the virtual address of the current page for the third-level page table entry. Finally, you need to fill in the attribute configuration for each level of page table.

[0067] S16. Update the CR3 register and enable the paging mechanism.

[0068] By updating the base address of the first-level page table to the CR3 register, the kernel can enable the paging mechanism.

[0069] Referring to point 3, the kernel chooses to use a 4KB paging mode with PAE (Page Address Estimation). For a 32-bit virtual address, only the high 20 bits need to be translated according to the page table, while the low 12 bits, used as the page offset, are not translated. This maps virtual address 0x12345678 to physical address 0x12345678.

[0070] In this embodiment, the page table is initialized before the processor system starts the paging mechanism. This allows all pages contained in the largest virtual address accessed by the system to be replaced with their equal physical addresses. This ensures that verification cases are compiled and run at physical addresses, and also enables the processor's paging mechanism. Furthermore, no page faults will occur during system operation, improving processor execution efficiency.

[0071] See Figure 4 After the processor starts the paging mechanism, all accessed memory addresses are virtual addresses. These are converted into physical addresses by the page table of the memory management unit, and instructions or data are fetched from the memory module to enter the processor verification program.

[0072] One embodiment of this application provides a processor verification method that can improve processor verification efficiency.

[0073] See Figure 5 The processor verification method provided in one embodiment of this application is applied to a processor verification system. The verification method in this embodiment may include:

[0074] S201. Determine the maximum memory address that the verification system can access, so as to determine the range of virtual addresses to be converted.

[0075] If the maximum address accessed by the kernel is 0xFFFFFFFF, the range of virtual addresses to be translated can be determined to be 0x0-0xFFFFFFFF, and page tables can be generated for all pages within this range.

[0076] Based on the maximum memory address required by the preset test code, the range of virtual addresses to be converted is determined, and then this range is used to initialize page tables at all levels. In this way, the preset test code will not generate page faults during execution, improving execution efficiency and avoiding the problem of reduced processor efficiency caused by a large number of page faults during the execution of the test code, which would interrupt the execution of the test code and enter the page fault handling service routine.

[0077] S202. Based on the virtual address range, request the necessary address space for each level of page table.

[0078] Based on the virtual address range, the operating system can be requested the memory address space required for each level of page tables. Since each level of page tables resides in physical memory, sufficient memory space needs to be reserved for each level of page tables from the operating system.

[0079] S203. Initialize page tables at all levels to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table.

[0080] During the process of allocating the necessary address space for each level of page table, the base address of each level of page table can be determined. Thus, during the initialization of each level of page table, the base address of the next level page table can be filled into the page table entry of the previous level page table. For example, the base address of the second level page table can be filled into the page table entry of the first level page table.

[0081] In this embodiment, the high-order bits of the virtual address are the bits in the virtual address excluding the offset bits within the page.

[0082] Since the page table entry of the last-level page table stores the base address of the physical address, the physical address corresponding to the virtual address can be obtained by combining the base address with the offset bits in the virtual address. In this embodiment, the last-level page table entry stores the bits in the virtual address excluding the offset bits. Thus, the physical address can be determined based on the bits in the virtual address excluding the offset bits and the offset bits in the page table, that is, the obtained physical address is equal to the virtual address.

[0083] S204. Update the base address of the first-level page table to the CR3 control register and enable the paging mechanism.

[0084] The first-level page table is the first-level page table used for initializing page tables.

[0085] S205. Based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level, the test code obtains data at the target physical address and / or writes data to the target physical address to verify the processor based on the data.

[0086] The value in the CR3 control register is the base address of the first-level page table.

[0087] During the execution of test code, data can be read from or written to memory through the initialized page tables. In this embodiment, when the test code is running, data can be written to or read from memory based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level. The processor can be verified based on the written and / or read data.

[0088] In this embodiment, the maximum memory address accessed by the verification system is determined to identify the virtual address range to be converted. Based on the virtual address range, the required address space is allocated for each level of page tables, and each level of page tables is initialized. The base address of the next level page table is filled into the page table entry of the previous level page table, and the high-order bits of the virtual address are filled into the page table entry of the last level page table. The high-order bits of the virtual address are the bits in the virtual address excluding the page offset bit. Since the page table entry of the last level page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained by combining this base address with the page offset bit in the virtual address, and since the last level page table entry in this embodiment stores the bits in the virtual address excluding the page offset bit, the physical address can be determined based on the bits in the virtual address excluding the page offset bit and the page offset bit. That is, the obtained physical address is equal to the virtual address. The virtual address range is determined based on the maximum memory address required by the preset test code. Thus, when the test code obtains data at the target physical address and / or writes data to the target physical address based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level, page faults will not occur during the verification of the processor. This improves processor verification efficiency and avoids the problem of reduced processor efficiency caused by numerous page faults interrupting the test code execution and entering the page fault handling service routine. Furthermore, during the development and compilation of processor verification code using the page table of this embodiment, only physical or virtual addresses can be used. This reduces the complexity of developing and compiling processor verification code, improves its efficiency, and further enhances processor verification efficiency.

[0089] Another embodiment of this application is basically the same as the above embodiments, except that, before allocating the required address space for each level of page table, the method of this embodiment may further include:

[0090] S206. Determine the pagination mode and page size to be enabled by the verification system.

[0091] The paging mode is kernel paging mode, where kernel refers to the processor's kernel. Paging modes can include NonPAE or PAE. In some examples, NonPAE mode uses 32-bit page table entries, while PAE mode uses 64-bit page table entries.

[0092] Page sizes include 4K, 2M, or 1G, and page size affects the number of page table levels required for page table transformation.

[0093] S207. Based on the kernel operating mode, paging mode, and page size entered by the verification system during startup, as well as the pre-established mapping relationship between the operating mode, paging mode, page size, and page table translation level, determine the page table translation level.

[0094] In some cases, the kernel operating mode may include Legacy mode or Long mode.

[0095] In this embodiment, the kernel operating mode, paging mode, and page size affect the number of page table levels.

[0096] The pre-established mapping relationship between the operating mode, paging mode, page size, and page table transition level allows the page table transition level to be determined based on the given kernel operating mode, paging mode, and page size.

[0097] See Figure 6 The following is an example of a page table initialization method implemented in a verification system. The specific execution flow is as follows:

[0098] S21. Select the system kernel paging mode and page size.

[0099] During startup initialization, the x86 processor verification system selects the paging mode and page size to be enabled by the system kernel and configures the corresponding registers.

[0100] S22. Determine the number of levels for page table transformation.

[0101] The number of page table translation levels is determined based on the operating mode, paging mode, and page size entered by the x86 processor verification system during startup.

[0102] S23. Request the physical address space required for each level of page table.

[0103] Allocate the physical address space required for each level of page table and ensure that this physical address space is not occupied.

[0104] S24. Determine the maximum memory address accessed in the verification system and determine the range of virtual addresses to be converted.

[0105] S25. Initialize page tables at all levels.

[0106] The page table entries are initialized according to specific rules. The base address of the lower-level page table is filled in the upper-level page table, and the high-order bits of the virtual address are filled in the last-level page table to ensure that the virtual address is equal to the physical address. The page table attributes are then configured at each level, and finally the page table is generated.

[0107] S26. Update the CR3 control register and enable paging.

[0108] Update the page table base address, i.e., the CR3 control register. Enable paging mechanism.

[0109] S27, Regression Validation Case.

[0110] Regression processor verification test cases.

[0111] Even when the number of regression test cases is large and the randomness is high, using the page table in this example can still ensure that no page faults occur during the entire regression test, effectively improving the verification efficiency.

[0112] Processor verification requires regression testing of a large number of verification cases. When the processor paging mechanism is activated, the memory locations where the data and instructions in the verification cases are stored are somewhat random. Therefore, in the existing technology, the processor may generate a large number of page faults when executing a large number of verification cases. Furthermore, the page fault handler needs to allocate the required page table. However, the page fault service routine is not the content of the processor case verification and is invalid verification code. Moreover, frequent entry into the page fault service routine will reduce the processor verification efficiency.

[0113] In this embodiment, the page table is initialized in the processor verification system, and all pages contained in the maximum virtual address accessed by the system are replaced with their equal physical addresses. This ensures that the verification case is compiled and run at the physical address, and at the same time, no page faults will occur during system operation, thereby improving the processor verification efficiency.

[0114] One embodiment of this application provides a page table creation apparatus that facilitates improved processor verification efficiency.

[0115] Figure 7 This is a schematic diagram of the structure of a page table creation apparatus provided in an embodiment of this application, as shown below. Figure 7 As shown, the page table creation apparatus of this embodiment may include: a first determining module 11, used to determine the virtual address range to be converted according to the maximum memory address required by the preset test code; a first requesting module 12, used to request the required address space for each level of page table according to the virtual address range; and a first initialization module 13, used to initialize each level of page table, so as to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits.

[0116] The apparatus of this embodiment can be used to perform Figure 1 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0117] The apparatus in this embodiment determines the virtual address range to be converted based on the maximum memory address required by the preset test code. Based on the virtual address range, it allocates the necessary address space for each level of page tables, initializes each level of page tables, fills the base address of the next-level page table into the page table entry of the previous-level page table, and fills the high-order bits of the virtual address into the page table entry of the last-level page table. The high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits. Since the page table entry of the last-level page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained by combining this base address with the page offset bits in the virtual address, and since the last-level page table entry in this embodiment stores the bits in the virtual address excluding the page offset bits, the physical address can be obtained. The physical address can be determined based on the bits in the virtual address excluding the page offset bit and the page offset bit. That is, the obtained physical address is equal to the virtual address, and the range of the virtual address is determined based on the maximum memory address required by the preset test code. In this way, when using the initialized page table to verify the processor, page faults will not occur, improving the processor verification efficiency. This avoids the problem of a large number of page faults being generated during the test code execution and interrupting the process into the page fault handling service routine, which would reduce the processor's running efficiency. In addition, during the development and compilation of processor verification code using the page table of this embodiment, only the physical address or the virtual address can be used. This reduces the complexity of developing and compiling processor verification code and improves the efficiency of developing and compiling processor verification code.

[0118] As an optional implementation, the apparatus further includes: a selection module, configured to select a paging mode and a page size before the first request module requests the address space required for each level of page table; and a second determination module, configured to determine the page table translation level based on the processor's kernel operating mode, paging mode, and page size, as well as a pre-established mapping relationship between the operating mode, paging mode, page size, and page table translation level.

[0119] As an optional implementation, the selection module is specifically used to: select a paging mode according to the kernel operating mode. 。

[0120] As an optional implementation, the selection module is specifically used to select a page size of 4K, 2M, or 1G.

[0121] As an optional implementation, the kernel running mode includes: classic running mode or long running mode.

[0122] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0123] One embodiment of this application provides a processor verification device that can improve processor verification efficiency.

[0124] Figure 8 This is a schematic diagram of the structure of a processor verification device provided in an embodiment of this application, as shown below. Figure 8 As shown, the processor verification device of this embodiment is applied to a processor verification system. The verification device may include: a third determining module 21, used to determine the maximum memory address accessed by the verification system to determine the virtual address range to be converted; a second requesting module 22, used to request the required address space for each level of page tables according to the virtual address range; a second initialization module 23, used to initialize each level of page tables, so as to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bit; an updating module 24, used to update the base address of the first level page table into the CR3 control register and enable the paging mechanism; and a verification module 25, used to obtain data at the target physical address by test code according to the base address of the first level page table in the CR3 control register and the initialized page tables of each level, and / or write data to the target physical address, so as to verify the processor according to the data.

[0125] The apparatus of this embodiment can be used to perform Figure 5 The technical solutions of the method embodiments shown are similar in principle and in effect, and will not be described again here.

[0126] In this embodiment, the maximum memory address accessed by the verification system is determined to identify the virtual address range to be converted. Based on the virtual address range, the required address space is allocated for each level of page tables, and each level of page tables is initialized. The base address of the next level page table is filled into the page table entry of the previous level page table, and the high-order bits of the virtual address are filled into the page table entry of the last level page table. The high-order bits of the virtual address are the bits in the virtual address excluding the page offset bit. Since the page table entry of the last level page table stores the base address of the physical address, and the physical address corresponding to the virtual address can be obtained by combining this base address with the page offset bit in the virtual address, and since the last level page table entry in this embodiment stores the bits in the virtual address excluding the page offset bit, the physical address can be determined based on the bits in the virtual address excluding the page offset bit and the page offset bit. That is, the obtained physical address is equal to the virtual address. The virtual address range is determined based on the maximum memory address required by the preset test code. Thus, when the test code obtains data at the target physical address and / or writes data to the target physical address based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level, page faults will not occur during the verification of the processor. This improves processor verification efficiency and avoids the problem of reduced processor efficiency caused by numerous page faults interrupting the test code execution and entering the page fault handling service routine. Furthermore, during the development and compilation of processor verification code using the page table of this embodiment, only physical or virtual addresses can be used. This reduces the complexity of developing and compiling processor verification code, improves its efficiency, and further enhances processor verification efficiency.

[0127] As an optional implementation, the apparatus further includes: a fourth determining module, configured to determine the paging mode and page size to be enabled by the verification system before the second request module requests the address space required for each level of page table; and a fifth determining module, configured to determine the page table conversion level based on the kernel running mode, paging mode, and page size entered by the verification system at startup, as well as the pre-established mapping relationship between the running mode, paging mode, page size, and page table conversion level.

[0128] The apparatus described in the above embodiments can be used to execute the technical solutions of the above method embodiments. The implementation principle and technical effects are similar, and will not be repeated here.

[0129] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application, as shown below. Figure 9As shown, the device may include: a housing 61, a processor 62, a memory 63, a circuit board 64, and a power supply circuit 65. The circuit board 64 is disposed inside the space enclosed by the housing 61, and the processor 62 and the memory 63 are disposed on the circuit board 64. The power supply circuit 65 is used to supply power to the various circuits or devices of the above-mentioned electronic device. The memory 63 is used to store executable program code. The processor 62 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 63, and is used to execute any of the page table creation methods or processor verification methods provided in the foregoing embodiments. Therefore, it can also achieve the corresponding beneficial technical effects, which have been described in detail above and will not be repeated here.

[0130] The aforementioned electronic devices exist in various forms, including but not limited to:

[0131] (1) Mobile communication devices: These devices are characterized by their mobile communication capabilities and are primarily designed to provide voice and data communication. These terminals include smartphones (such as iPhones), multimedia phones, feature phones, and low-end phones.

[0132] (2) Ultra-mobile personal computer devices: These devices fall under the category of personal computers, possessing computing and processing capabilities, and generally also have mobile internet access features. These terminals include PDAs, MIDs, and UMPCs, such as the iPad.

[0133] (3) Portable entertainment devices: These devices can display and play multimedia content. This category includes: audio and video players (such as iPods), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

[0134] (4) Server: A device that provides computing services. The components of a server include a processor, hard disk, memory, system bus, etc. Servers are similar to general computer architectures, but because they need to provide highly reliable services, they have higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.

[0135] (5) Other electronic devices with data interaction functions.

[0136] Accordingly, embodiments of this application also provide a computer-readable storage medium storing one or more programs, which can be executed by one or more processors to implement any of the page table creation methods or processor verification methods provided in the foregoing embodiments, thus achieving the corresponding technical effects. This has been described in detail above and will not be repeated here.

[0137] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0138] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0139] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0140] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this application, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0141] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0142] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for creating page tables, characterized in that, include: Determine the range of virtual addresses to be converted based on the maximum memory address required by the preset test code; Based on the virtual address range, allocate the required address space for each level of page table; Initialize page tables at each level so that the base address of the next-level page table is filled into the page table entry of the previous-level page table. The high-order bits of the virtual address are filled into the page table entry of the last-level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the offset bits within the page; The initialized page tables at each level are used to verify the processor; before allocating the necessary address space for each page table, the method further includes: Choose the pagination mode and page size; The page table translation level is determined based on the kernel operating mode, paging mode, and page size of the processor to be verified, as well as the pre-established mapping relationship between operating mode, paging mode, page size, and page table translation level.

2. The method according to claim 1, characterized in that, The selection of pagination mode includes: Select the paging mode based on the kernel operating mode.

3. The method according to claim 1, characterized in that, The kernel operating modes include: classic operating mode or long operating mode.

4. A processor verification method, characterized in that, The verification method, applied to a processor verification system, includes: Determine the maximum memory address that the verification system can access, in order to determine the range of virtual addresses to be converted; Based on the virtual address range, allocate the required address space for each level of page table; Initialize page tables at each level so that the base address of the next-level page table is filled into the page table entry of the previous-level page table. The high-order bits of the virtual address are filled into the page table entry of the last-level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the offset bits within the page; Update the base address of the first-level page table to the CR3 control register and enable the paging mechanism; Based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level, the test code obtains data at the target physical address and / or writes data to the target physical address to verify the processor based on the data. The method further includes, before allocating the necessary address space for each level of page table: Determine the pagination mode and page size to be enabled by the verification system; Based on the kernel operating mode, paging mode, and page size entered by the verification system upon startup, as well as the pre-established mapping relationship between the operating mode, paging mode, page size, and page table transition levels, the page table transition level is determined.

5. A page table creation apparatus, characterized in that, include: The first determining module is used to determine the range of virtual addresses to be converted based on the maximum memory address required by the preset test code. The first application module is used to apply for the required address space for each level of page table according to the virtual address range; The first initialization module is used to initialize page tables at all levels, so as to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the offset bits within the page; The initialized page tables at each level are used to verify the processor, and the device further includes: The selection module is used to select the paging mode and page size before the first application module allocates the address space required for each level of page table; The second determining module is used to determine the page table translation level based on the kernel operating mode, paging mode, and page size of the processor to be verified, as well as the pre-established mapping relationship between the operating mode, paging mode, page size, and page table translation level.

6. A processor verification device, characterized in that, The verification device, used in a processor verification system, includes: The third determining module is used to determine the maximum memory address accessed by the verification system, so as to determine the range of virtual addresses to be converted; The second application module is used to apply for the required address space for each level of page table according to the virtual address range; The second initialization module is used to initialize page tables at all levels, so as to fill the base address of the next level page table into the page table entry of the previous level page table, and fill the high-order bits of the virtual address into the page table entry of the last level page table; wherein, the high-order bits of the virtual address are the bits in the virtual address excluding the page offset bits; The update module is used to update the base address of the first-level page table into the CR3 control register and enable the paging mechanism; The verification module is used to obtain data at the target physical address and / or write data to the target physical address based on the base address of the first-level page table in the CR3 control register and the initialized page tables at each level, so as to verify the processor based on the data. The device further includes: The fourth determining module is used to determine the paging mode and page size to be enabled by the verification system before the second application module applies for the address space required for each level of page table; The fifth determining module is used to determine the page table conversion level based on the kernel running mode, paging mode, and page size entered by the verification system at startup, as well as the pre-established mapping relationship between the running mode, paging mode, page size, and page table conversion level.

7. An electronic device, characterized in that, The electronic device includes: a housing, a processor, a memory, a circuit board, and a power supply circuit, wherein the circuit board is disposed inside the space enclosed by the housing, and the processor and the memory are disposed on the circuit board; the power supply circuit is used to supply power to various circuits or devices of the electronic device; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, for executing the page table creation method according to any one of claims 1-3 or the processor verification method according to claim 4.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores one or more programs, which can be executed by one or more processors to implement the page table creation method according to any one of claims 1-3 or the processor verification method according to claim 4.

Images