A Method for Optimizing the Size Parameters of Circuit Diagram at the Plate Layer Level Based on Transfer Learning

Abstract

The present invention discloses a method for optimizing the size parameters of a circuit diagram at the layout layer level based on transfer learning, comprising the following steps: obtaining a schematic diagram, simulation data at the layout layer level, and sampling data; constructing neural networks at the schematic layer level and the layout layer level, the input of the neural network including a set of size parameters of devices in the circuit schematic diagram; the output of the neural network at the schematic layer level including simulation data; using the NSGA-II optimization algorithm to optimize the set of size parameters of devices in the circuit layout, and judging the simulation results through a custom evaluation function: if the circuit design specifications are not met, continue to iterate until the number of loop iterations is exhausted or a set of size parameters that meet the requirements is obtained, and an optimized set of size parameters is obtained. The present invention can greatly reduce the data samples required for establishing a layout model and accelerate the layout modeling process.

Description

Technical Field

[0001] The present invention is applied to the field of radio frequency integrated circuit design, and in particular is a layout level circuit diagram size parameter optimization method based on transfer learning. Background Art

[0002] As a practical means of RF integrated circuit design verification, electromagnetic simulation technology is widely used in layout design and layout optimization. Electromagnetic simulation simulates the performance of RF circuits after processing to a certain extent, freeing RF circuit design engineers from the traditional design, processing and testing process, and replacing traditional processing and manufacturing experiments with simulation experiments. In recent years, the rapid improvement of hardware performance and the gradual improvement of EDA software have given RF circuit engineers more time to focus on design work. Electromagnetic simulation has the following advantages: 1. Key parameters such as geometric structure, material properties, and placement are very easy to adjust. 2. Certain parts of the circuit can be analyzed separately. 3. The electromagnetic characteristics of any structure and any system can be obtained according to user needs. 4. Compared with testing, electromagnetic simulation can provide more comprehensive and complete electromagnetic information. Electromagnetic simulation has been widely and successfully applied to many aspects of electromagnetic performance prediction and design. On the premise of understanding the problem to be analyzed, reasonably setting the simulation model and solving parameters, simulation can completely replace testing. The high cost-effectiveness and flexibility of simulation can greatly improve design efficiency and reduce design costs.

[0003] However, electromagnetic simulation also has many problems. If you want to obtain a higher-precision simulation, an electromagnetic simulation often takes several days or even weeks, which undoubtedly increases the time cost of circuit design. Secondly, in layout design, most of our changes to the device require manual intervention to verify the rationality of the parameters, which also invisibly increases the workload of circuit design engineers.

[0004] How to introduce AI into EDA tools has always been a hot research direction. Artificial Neural Networks (ANNs), also known as Neural Networks (NNs) or Connection Models, are a mathematical model that imitates the behavioral characteristics of animal neural networks and performs distributed parallel information processing. This network relies on the complexity of the system and adjusts the interconnected relationships between a large number of internal nodes to achieve the purpose of processing information.

[0005] Attached Figure 1 The figure shows a double hidden layer feedforward fully connected neural network, or multi-layer perceptron (MLP). Figure 2It is a schematic diagram of the perceptron network structure of a simple multi-input neuron. Each hidden layer of it is a fully connected layer, and each of its units is called a neuron. Taking linear regression as an example, given an instance x = (x1, x2, …, x n ), the linear model attempts to learn a function that predicts through the linear combination of n attributes, that is, as shown in Formula 1, and its matrix form is shown in Formula 2:

[0006]

[0007] f(x) = f(W T X + b) (2)

[0008] In the above two formulas, f is the activation function, w n is the weight size corresponding to each input parameter, x n is the input parameter, b is the bias parameter, W T is the weight parameter matrix, and X is the input parameter matrix.

[0009] The training of the neural network is supervised learning, that is, the input X has a corresponding true value Y, and the loss Loss between the output Y of the neural network and the true value Y is what the network backpropagates. The training process of the entire network is a process of continuously reducing the loss Loss. For this reason, Formula 3 is listed:

[0010]

[0011] In the above formula, Loss is the loss, y i is the true value, w is the weight parameter, b is the bias parameter, and x i is the input parameter.

[0012] Generally, the gradient descent method is used to find the best combination of w and b to minimize Loss. When solving, every time w and b are updated, the partial derivatives of each parameter are calculated once, and then the parameters are updated again according to Loss. The update formulas are Formulas 4 and 5.

[0013]

[0014]

[0015] In the above formula, the superscript i represents the i-th weight, the subscript n represents the n-th step, and α is the learning rate. Through continuous iterative learning, Loss is gradually reduced until the optimal solution is obtained. Thus, the training of the fully connected neural network is completed.

[0016] The purpose of transfer learning is to apply the knowledge or patterns learned in a certain field or task to different but related fields or problems. The main idea of transfer learning is to transfer labeled data or knowledge structures from related fields to complete or improve the learning effect of the target field or task. Summary of the Invention

[0017] The present invention aims to accelerate the optimized design of the layout link of radio frequency integrated circuits, integrating layout generation, automatic layout library building, establishing a layout model through transfer learning, and layout optimization.

[0018] The present invention provides a method for optimizing the size parameters of the circuit diagram at the layout level based on transfer learning, including the following steps:

[0019] Step A: Obtain the simulation data at the principle layer level, the sampling data at the principle layer level, the simulation data at the layout layer level, and the sampling data at the layout layer level as training data; the simulation data includes any one of scattering parameters, simulation frequency bands, and noise.

[0020] Step B: Construct a neural network at the principle layer level, and use the simulation data at the principle layer level and the sampling data at the principle layer level to train the neural network at the principle layer level to obtain a schematic diagram network. The input of the neural network at the principle layer level includes the size parameter group of the devices in the circuit schematic diagram; the output of the neural network at the principle layer level includes simulation data.

[0021] Construct a neural network at the layout layer level; use the transfer learning method, and use the simulation data at the layout layer level and the sampling data at the layout layer level as the training set to train the neural network at the layout layer level to obtain a layout network. The input of the neural network at the layout layer level includes the size parameter group of the devices in the circuit layout, and the output includes simulation data.

[0022] Step C: Use the NSGAⅡ optimization algorithm to optimize the size parameter group of the devices in the circuit layout:

[0023] Input the size parameter range of the devices in the circuit layout into the NSGAⅡ optimization algorithm, use the NSGAⅡ optimization algorithm to select a suitable parameter group within the range, input the suitable parameter group into the layout network, and obtain simulation data as the simulation result.

[0024] According to the requirements for the following design indicators, the design indicators include return loss, insertion loss, and insertion loss flatness, customize an evaluation function, and judge the simulation result: if it does not meet the design indicators of the circuit, continue to iterate until the number of loop times is exhausted or a size parameter group that meets the requirements is obtained, and obtain the optimized size parameter group.

[0025] Preferably, step A specifically includes the following steps:

[0026] A1: Through a script, within the dimensional parameter range of the devices in the circuit schematic diagram, extract several groups of dimensional parameters and generate a netlist; use the group of dimensional parameters as the sampling data at the schematic diagram layer level, send the generated netlist into a simulator for schematic diagram simulation to obtain simulation data; the simulation data is scattering parameters; obtain the training data at the schematic diagram layer level based on the sampling data at the schematic diagram layer level and the scattering parameters;

[0027] A2: Through a script, within the dimensional parameter range of the devices in the circuit layout, extract several groups of dimensional parameters and generate a simulation file, use the group of dimensional parameters as the sampling data at the layout layer level, send the simulation file into an electromagnetic simulator for simulation, extract the scattering parameters in the simulation data and convert them into an SNP file; then use the SNP file for co-simulation to obtain co-simulation data, the co-simulation data includes scattering parameters, and obtain the training data at the layout layer level based on the scattering parameters and the sampling data at the layout layer level.

[0028] Preferably, the circuit in step A1 is a low-noise amplifier circuit.

[0029] Preferably, the neural network at the schematic diagram layer level is a multi-layer perceptron; the bottom layer of the multi-layer perceptron is the input layer, the middle is the hidden layer, and the last is the output layer.

[0030] Preferably, the number of nodes in the hidden layer is greater than the number of nodes in the input layer and the output layer; the number of hidden layers is 3 layers and the number of nodes is 400.

[0031] Preferably, in step B, the transfer learning method includes: using the schematic diagram network as a pre-trained network for transfer.

[0032] Preferably, in step C, the execution of the NSGA-II algorithm includes the following steps:

[0033] The first step: Generate an initial population, at this time the evolutionary generation Gen = 1; the initial population contains N groups of device dimensional parameters, and this group of dimensional parameters is sampled by the NSGA-II algorithm within the dimensional parameter range of the devices in the circuit layout, and N is the size of the sub-population; normalize the N groups of dimensional parameters in the initial population and input them into the layout network to obtain predicted simulation data; input the predicted simulation data into a custom evaluation function to obtain an evaluation score group of the initial population;

[0034] Step 2: Determine whether the first-generation sub-population has been generated. If it has, set the generation number Gen = 2; otherwise, perform non-dominated sorting, selection, Gaussian crossover, and mutation on the initial population to generate the first-generation sub-population and set the generation number Gen = 2. The first-generation sub-population contains N device size parameter groups, which are obtained by the NSGA-II algorithm within the size parameter range of the devices in the circuit layout. Normalize the N size parameter groups in the first-generation sub-population and input them into the layout network to obtain the predicted simulation data for Step 2. Input the predicted simulation data for Step 2 into the custom evaluation function to obtain the evaluation score group for the first-generation sub-population.

[0035] Step 3: Merge the parent population and the offspring population into a new population. The parent population is the population that generated the current generation of sub-population, and the parent population will be used multiple times in the loop. The new population obtains the optimal solutions in the initial population and the first-generation sub-population through the elite selection strategy, and retains the size parameter groups and evaluation score groups of the Pareto solutions.

[0036] Step 4: Determine whether a new parent population has been generated. If not, calculate the objective functions of the individuals in the new population, perform fast non-dominated sorting, calculate the crowding degree, and generate a new parent population through the elite strategy operation. If so, proceed to Step 5.

[0037] Step 5: Perform selection, crossover, and mutation operations on the generated parent population to generate an offspring population.

[0038] Step 6: Determine whether Gen is equal to the maximum number of generations. If not, set the generation number Gen = Gen + 1 and return to Step 3. Otherwise, the algorithm ends. Output the size parameter groups and evaluation score groups of all Pareto solutions.

[0039] A method for establishing a layout simulation model using transfer learning proposed by the present invention can greatly reduce the data samples required for establishing the layout model and accelerate the layout modeling process. The present invention also proposes a series of automated processes, including design layout establishment, layout DRC detection, layout sampling simulation, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structure diagram of a feedforward fully-connected neural network with two hidden layers.

[0041] Figure 2 is a schematic diagram of the structure of a simple multi-input neuron perceptron network.

[0042] Figure 3 is the overall flowchart of the technical solution.

[0043] Figure 4 is the preset network structure diagram.

[0044] Figure 5 It is a process diagram of neural network training at the principle layer level.

[0045] Figure 6 It is a comparison diagram of the neural network training process at the layout layer level.

[0046] Figure 7 It is a comparison diagram of the neural network test structure.

[0047] Figure 8 It is a flow chart of the NSGAⅡ algorithm.

[0048] Figure 9 It is a diagram of the NSGAⅡ optimization result. Specific implementation manners

[0049] To make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will elaborate on the various embodiments of the present disclosure with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the various embodiments of the present disclosure, many technical details are provided for the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation to the specific implementation manners of the present disclosure. The various embodiments can be combined and cross-referenced with each other on the premise of not being contradictory.

[0050] To implement the above functions, the present invention adopts the following technical solutions:

[0051] Preparation stage: Prepare training files, including simulation data and sampling data at the principle layer level, and simulation data and sampling data at the layout layer level. A schematic diagram is a diagram connected by lines using general graphic symbols of electronic devices. It mainly describes the working principle of electronic and electrical products and the connection relationship of components. It is a diagram used to guide the working principle analysis, production debugging and maintenance of electrical products. After simulating the schematic diagram, simulation data can be obtained. The simulation data can include information such as the scattering parameters of the circuit, the simulation frequency band, and noise according to the simulation settings. A layout is the result of the physical design in the bottom layer of integrated circuit design. Through layout and wiring techniques, the physical design converts the results of logic synthesis into a physical layout file. This file contains information about the shape, area and position of each hardware unit on the chip. After simulating the layout, simulation data can be obtained. The simulation data can include information such as the scattering parameters of the circuit, the simulation frequency band, and noise according to the simulation settings. Sampling data is a parameter group composed of device parameters in the circuit and is saved as sampling data. Extract relevant data and convert it into usable training data;

[0052] Training stage: Use the simulation data and sampling data at the principle layer to train the neural network at the principle layer. This neural network can replace the simulator. After inputting the size parameter group of the devices in the circuit (taking the microstrip line as an example, the size parameters are the length and width of the microstrip line), it outputs relevant simulation data, including but not limited to scattering parameters, simulation frequency bands, noise and other information. Use transfer learning to use the simulation data and sampling data at the layout layer as the training set to train the neural network at the layout layer. This neural network can replace the electromagnetic simulator. After inputting the size parameter group of the devices in the circuit (taking the microstrip line as an example, the size parameters are the length and width of the microstrip line), it outputs relevant simulation data, including but not limited to scattering parameters, simulation frequency bands, noise and other information.;

[0053] In the optimization stage, use the NSGA-II optimization algorithm to optimize the size parameter group of the devices in the layout layer circuit. Input the size parameter range of the devices in the circuit into the optimization algorithm. The algorithm will select appropriate parameter groups within the range, call the neural network at the layout layer to output the predicted simulation results according to the input parameter groups and frequency bands. The simulation data includes but not limited to scattering parameters, simulation frequency bands, noise and other information. According to the design specifications of the circuit, define the evaluation function to judge the simulation results. If it does not meet the design specifications of the circuit, continue to iterate until the number of loops is exhausted or the size parameter group that meets the requirements is obtained, and the optimization ends. The general flow chart of the technical solution is as attached Figure 3 as shown.

[0054] Preferably, the preparation stage includes two parts:

[0055] A1: Randomly extract the size parameter group in the size parameter range of the devices in the circuit through the script and automatically generate a netlist. The netlist usually conveys information about the circuit connection, such as the instances of modules, wire networks, and related attributes. Save the size parameter group as sampling data, send the obtained netlist into the simulator for schematic simulation, extract and preprocess the scattering parameters in the simulation data. Then convert the preprocessed sampling data and the preprocessed simulation data into the training set at the principle layer.

[0056] A2: Randomly extract the size parameter group in the size parameter range of the devices in the circuit through the script and automatically generate a simulation file. Save the size parameter group as sampling data, send the simulation file into the electromagnetic simulator for simulation, extract the scattering parameters in the simulation data and convert them into an SNP file. The SNP file is usually used to represent S parameters, which are parameters used to represent active devices or passive connections of n-port networks. Then use the SNP file for co-simulation to obtain the co-simulation results, extract and preprocess the scattering parameters in the simulation data. Then convert the preprocessed sampling data and the preprocessed simulation data into the training set at the layout layer.

[0057] Preferably, the training stage includes the following parts:

[0058] B1: Use the sampled data at the principle layer level and the simulation frequency band points as the input parameters of the training set, and the scattering parameters of the simulation data as the output parameters of the training set. Use this training set to train the neural network at the principle layer level.

[0059] B2: Use the sampled data at the layout layer level and the simulation frequency band points as the input parameters of the training set, and the scattering parameters of the simulation data as the output parameters of the training set. Use the parameters of each layer in the neural network at the principle layer level as the initialization parameters of the new neural network, and perform fine-tuning training on the new neural network. The training set used is the training set at the layout layer level, and the neural network at the layout layer level is trained. Test the trained neural network, compare the predicted data obtained by inputting a set of test data into the neural network after normalization with the actual simulation data, and check whether the comparison result is close to determine whether the neural network is accurate; if it is not accurate enough, it is necessary to expand the training set at the layout layer level and continue training until the requirements are met.

[0060] Preferably, the optimization stage includes two parts:

[0061] C1: Call the neural network at the layout layer level, input the parameter set obtained by the optimization algorithm and the simulation frequency band into the neural network, and the neural network will return the scattering parameter set corresponding to the frequency band. Use a custom evaluation function to evaluate the scattering parameter set. In this process, the neural network replaces the role of the electromagnetic simulator.

[0062] C2: Use the NSGAⅡ optimization algorithm to continuously iterate and loop to obtain the optimal size parameter set, and finally generate the required layout file.

[0063] The technical solution disclosed by the present invention relates to a method for establishing a layout layer level simulation model and a method for optimizing the design of an integrated circuit layout layer level, and its process is as Figure 3 shown, including:

[0064] Step A101, obtain the topological structure diagram of the circuit to be optimized.

[0065] The circuit to be optimized is a low-noise amplifier circuit; the design parameters of the low-noise amplifier include return loss, insertion loss, and insertion loss flatness.

[0066] Step A102: Based on the topological structure diagram and design specifications of the circuit to be optimized, determine the size parameters of the devices in the circuit to be optimized and their corresponding value ranges, and perform parameter sampling within the value ranges. Save the sampled device size parameter groups as sampling data at the schematic layer level, generate the corresponding netlist using a script, input it into the simulator for simulation, extract and preprocess the scattering parameters in the simulation data. Then, preprocess the sampling data and the preprocessed simulation data and convert them into a training set at the schematic layer level.

[0067] Step A201: Use a script to randomly generate a set of size parameters that comply with the design rules based on the PCB design rules (DRC). After removing the active part of the circuit, generate a simulation file for electromagnetic simulation. During this process, save the size parameter group as sampling data. Convert the output data into SNP format and import it into the schematic diagram in the form of a passive part for co-simulation to obtain the simulation results. Extract and preprocess the scattering parameters in the simulation data. Then, preprocess the sampling data and the preprocessed simulation data and convert them into a training set at the layout layer level. In this training set, the sampling data and the circuit operating frequency band are input parameters, and the scattering parameters in the simulation data are output parameters. The data processing uses the normalization method, and the formula 6 for parameter normalization is as follows:

[0068]

[0069] In the above formula, x* is the parameter after normalization processing, x is the original parameter, min is the minimum value of the parameter, and max is the maximum value of the parameter. In this technical solution, the input parameters are normalized using the linear function normalization method to convert the original data to the range of [0, 1]. In this way, the equal-proportion scaling of the original data is achieved. Parameter normalization has the following advantages: 1. Improve the convergence speed of the model. 2. Improve the accuracy of the model. Normalization is necessary as it can make the contributions of each feature to the result the same.

[0070] Since electromagnetic simulation takes a long time, in order to reduce the time cost of simulation, small-sample training will be adopted. Use a pre-trained model for transfer fine-tuning. Pre-trained models usually have good semantic expressions in terms of features. At this time, only fine-tuning the model on a small data set can achieve good results. This is also the commonly used training method for most small data sets at present.

[0071] Step B101: Construct a neural network and input the schematic training set into the neural network for training.

[0072] The neural network model is a multi-layer perceptron (MPL). The bottom layer of the multi-layer perceptron is the input layer, the middle is the hidden layer, and the last is the output layer. The number of nodes in the hidden layer is greater than the number of nodes in the input layer and the output layer.

[0073] The preset network structure can be as Figure 4 shown. The input layer has n nodes, the hidden layer has 3 layers with 400 nodes, and the output layer has m nodes. In this technical solution, the number of hidden layers and nodes is not limited, and those skilled in the art can select and set according to actual needs in practical applications.

[0074] After initializing the network, the schematic diagram data is divided into a training set and a test set, and the training data is randomly shuffled.

[0075] The processed schematic diagram training set is input into the neural network for training, and the training process diagram is as shown in the appendix Figure 5 shown. In the figure, the x-axis represents the number of training generations, the left y-axis represents the training accuracy, the right y-axis represents the training Loss, the solid line represents the training accuracy, and the dashed line represents the training Loss.

[0076] Exemplarily, the traditional MPL training process is divided into the following three parts:

[0077] 1. Initialize the network weights and the thresholds of the neurons

[0078] For the network in the first training, generally, random initialization is adopted. For the pre-trained network, generally, the pre-trained parameters are imported to initialize the parameters.

[0079] 2. Forward propagation

[0080] Calculate the inputs and outputs of the hidden layer neurons and the output layer neurons layer by layer according to the formula. The calculation formula is as shown in Formula 7:

[0081]

[0082] In the above formula, i is the subscript of the neurons in the previous layer, or the nodes in the input layer. j is the subscript of the neurons in the current layer, or the neurons in the hidden layer. W ij represents the weights from each neuron in the previous layer to the current neuron, that is, the weights of neuron j, b is the bias of the current neuron, and h j represents the sum of the weighted values of all the inputs of the current node and the bias.

[0083] The output a of the neuron is calculated through the activation function, and the calculation formula is as shown in Formula 8:

[0084]

[0085] aj Represents the output value of the hidden layer neurons, g is the activation function, and the output of the neurons in this layer is equal to the input of the neurons in the lower layer.

[0086] 3. Loss-based back propagation

[0087] The goal of back propagation is to adjust the weights of the network so that the output and the target have the smallest error, and the idea of ​​least squares. Its loss function is defined as the mean square error of the output vector, and the calculation formula is shown in Formula 9:

[0088]

[0089] In the above formula, k is the subscript of the next layer of neurons, or the output layer neurons, y is the output value, and t is the true value.

[0090] After the error is obtained, gradient descent is used to find the optimal solution, that is, to find the partial derivative of the loss function Loss with respect to the weight w. The calculation formula is shown in Formula 10:

[0091]

[0092] In the above formula, w jk is the weight from each neuron in the previous layer to the current neuron, that is, the weight of neuron k, h k Represents the sum of all input weights and biases of the current node.

[0093] Use the gradient descent method to update the weights. The update formula is as follows:

[0094]

[0095] According to this method, the weights of the upper layers are updated in sequence until the combination with the minimum loss is obtained, and the training is completed.

[0096] Step B201, construct a neural network and input the layout training set into the neural network for training.

[0097] Use the network trained with the schematic diagram as the pre-trained network for migration, and fine-tune the parameters of each layer. Fine-tune is translated into Chinese as "fine-tuning". In deep learning, it is necessary to continuously train and update the parameters (weights) of the model in the deep network to fit the model that can achieve the expected results.

[0098] For example, the weight parameters of the network obtained by training the schematic training set are transferred as pre-trained values ​​to the neural network for layout training. After the data set is divided into a training set and a test set, it is put into the neural network for small sample training to obtain a neural network model at the layout level. The training process comparison diagram is shown in the attached figure. Figure 6As shown in the figure. Among them, the x-axis represents the number of training generations, the left y-axis represents the training accuracy, the right y-axis represents the training Loss. The solid line represents the training accuracy, and the dashed line represents the training Loss. It can be seen from the figure that during the short training process, the training accuracy directly starts to increase from 90%. After the training is completed, the neural network is tested. A set of test data is normalized and then input into the neural network. The predicted data obtained is compared with the actual simulation data to check whether the comparison results are close, so as to judge whether the neural network is accurate. If it is not accurate enough, the extended version of the layer-level training set needs to be expanded and continue training until the requirements are met. The comparison chart of the test results is as attached Figure 7 As shown. The dashed line shown in the figure is the prediction result, and the solid line is the actual simulation result. It can be seen from the figure that the network basically meets the requirements.

[0099] Step C101, call the layer-level neural network to obtain the simulated simulation data and assign scores.

[0100] Input the value range of the size parameters of the circuit devices into the NSGAⅡ optimization algorithm. The optimization algorithm generates a sub-population that meets the requirements according to the input value range. The parameter groups in the population are inspected and reasonable parameter groups are obtained after DRC modification. The reasonable parameter groups are normalized and then input into the layer-level neural network to obtain simulation data. After extracting the simulation data, the corresponding scores are obtained according to the custom evaluation function. The evaluation function is set according to the actual design indicators, and each circuit is different and evaluated according to personal needs, and the evaluation scores are returned. Taking the S11 parameter index as less than -10dB as an example, we will traverse the S11 parameter values within the simulation frequency band, take the maximum value of S11 within the simulation frequency band, and compare it with -10. If the maximum value is less than -10dB, the S11 parameter meets the index requirements and gets a full score; if it is greater than -10dB, the score is given according to the gap with -10. The greater the gap, the lower the score.

[0101] Step C201, use the NSGAⅡ algorithm for iterative optimization to find one or more groups of parameter group solutions that meet the optimization indicators.

[0102] The flow chart of the NSGAⅡ algorithm execution is as attached Figure 8 As shown.

[0103] The first step: Generate the initial population. At this time, the evolutionary generation Gen = 1. The initial population contains N device size parameter groups, and this size parameter group is sampled by the algorithm within the value range. N is the size of the sub-population. The N size parameter groups in the initial population are normalized and then input into the layer-level neural network to obtain the predicted simulation data. The simulation data is input into the custom evaluation function to obtain the evaluation score group of the initial population.

[0104] Step 2: Determine whether the first-generation sub-population has been generated. If it has, set the generation number Gen = 2. Otherwise, perform non-dominated sorting, selection, Gaussian crossover, and mutation on the initial population to generate the first-generation sub-population and set the generation number Gen = 2. The first-generation sub-population contains N groups of device size parameters, which are obtained by the algorithm within the value range. Normalize the N groups of size parameters in the first-generation sub-population and input them into the layout layer neural network to obtain predicted simulation data. Input the simulation data into a custom evaluation function to obtain the evaluation score group of the first-generation sub-population.

[0105] Step 3: Merge the parent population and the offspring population into a new population. The parent population is the population that generated the current generation of sub-population, and the parent population will be used multiple times in the loop; the new population obtains the optimal solutions in the initial population and the first-generation sub-population through the elite selection strategy in the algorithm, and retains the size parameter groups and evaluation score groups of the Pareto solutions.

[0106] Step 4: Determine whether a new parent population has been generated. If not, calculate the objective function of the individuals in the new population, and perform operations such as fast non-dominated sorting, crowding degree calculation, and elite strategy to generate a new parent population; otherwise, go to Step 5.

[0107] Step 5: Perform selection, crossover, and mutation operations on the generated parent population to generate an offspring population.

[0108] Step 6: Determine whether Gen is equal to the maximum number of generations. If not, set the generation number Gen = Gen + 1 and return to Step 3; otherwise, the algorithm ends. Output the size parameter groups and evaluation score groups of all Pareto solutions.

[0109] When the algorithm ends, it will return multiple size parameter groups and the corresponding evaluation score groups. Some parameter optimization results are shown in the appendix Figure 9 as shown. It can be seen from the figure that the optimization goal in the figure is the insertion loss flatness, and the full score of the goal is 10 points. After iterative optimization, the optimization index can basically be achieved. Input the optimal parameter group into the script to generate a new netlist, and generate the corresponding layout file according to the netlist. The process of this technical solution ends.

[0110] Those of ordinary skill in the art can understand that the above embodiments are specific implementation manners to implement the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. A method for optimizing the size parameters of a circuit diagram at the plate layer level based on transfer learning, characterized in that, It includes the following steps: Step A: Obtain the simulation data at the principle layer level, the sampling data at the principle layer level, the simulation data at the layout layer level, and the sampling data at the layout layer level as training data; the simulation data includes any one of scattering parameters, simulation frequency bands, and noise; Step B: Construct a neural network at the principle layer level, and use the simulation data and sampling data at the principle layer level to train the neural network at the principle layer level to obtain a schematic diagram network. The input of the neural network at the principle layer level includes the size parameter group of the devices in the circuit schematic diagram; the output of the neural network at the principle layer level includes simulation data; Construct a neural network at the layout layer level; Use the transfer learning method, and use the simulation data and sampling data at the layout layer level as the training set to train the neural network at the layout layer level to obtain a layout network. The input of the neural network at the layout layer level includes the size parameter group of the devices in the circuit layout, and the output includes simulation data; Step C: Use the NSGAⅡ optimization algorithm to optimize the size parameter group of the devices in the circuit layout: Input the size parameter range of the devices in the circuit layout into the NSGAⅡ optimization algorithm, use the NSGAⅡ optimization algorithm to select a suitable parameter group within the range, input the suitable parameter group into the layout network, and obtain simulation data as the simulation result; According to the requirements for the following design indicators, the design indicators include return loss, insertion loss, and insertion loss flatness, customize an evaluation function, and judge the simulation result: if it does not meet the design indicators of the circuit, continue to iterate until the number of loops is exhausted or a size parameter group that meets the requirements is obtained, and obtain the optimized size parameter group.

2. The method for optimizing the size parameters of the circuit diagram at the layer level based on transfer learning according to claim 1, wherein The specific steps of Step A include the following steps: A1: Through a script, within the size parameter range of the devices in the circuit schematic diagram, extract several size parameter groups and generate a netlist; use the size parameter groups as the sampling data at the principle layer level, send the generated netlist into a simulator for schematic diagram simulation to obtain simulation data; the simulation data is scattering parameters; obtain the training data at the principle layer level based on the sampling data at the principle layer level and the scattering parameters; A2: Through a script, within the size parameter range of the devices in the circuit layout, extract several size parameter groups and generate a simulation file, use the size parameter groups as the sampling data at the layout layer level, send the simulation file into an electromagnetic simulator for simulation, extract the scattering parameters in the simulation data and convert them into SNP files; then use the SNP files for co-simulation to obtain co-simulation data, and the co-simulation data includes scattering parameters, and obtain the training data at the layout layer level based on the scattering parameters and the sampling data at the layout layer level.

3. The method for optimizing the size parameters of the circuit diagram at the layout layer based on transfer learning according to claim 2, wherein, The circuit in Step A1 is a low-noise amplifier circuit.

4. The method for optimizing the size parameters of a circuit diagram at the layout layer level based on transfer learning according to claim 3, wherein The neural network at the principle layer level is a multi-layer perceptron; the bottom layer of the multi-layer perceptron is the input layer, the middle is the hidden layer, and the last is the output layer.

5. The method for optimizing the size parameters of the circuit diagram at the layout layer based on transfer learning according to claim 4, characterized in that, The number of nodes in the hidden layer is greater than the number of nodes in the input layer and the output layer; the number of hidden layers is 3 layers, and the number of nodes is 400.

6. The method for optimizing the size parameters of the circuit diagram at the layer level based on transfer learning according to claim 5, wherein In the said step B, the transfer learning method includes: using a schematic network as a pre-trained network for transfer.

7. The method for optimizing the size parameters of the circuit diagram at the layout layer based on transfer learning according to claim 6, wherein: In the said step C, the execution of the NSGA-II algorithm includes the following steps: The first step: Generate an initial population, at this time the generation number Gen = 1; the initial population contains N groups of device size parameters, and this size parameter group is sampled by the NSGA-II algorithm within the size parameter range of the devices in the circuit layout, where N is the size of the sub-population; normalize the N size parameter groups in the initial population and input them into the layout network to obtain predicted simulation data; input the predicted simulation data into a custom evaluation function to obtain an evaluation score group of the initial population. The second step: Determine whether the first-generation sub-population has been generated. If it has been generated, then set the generation number Gen = 2. Otherwise, perform non-dominated sorting and selection, Gaussian crossover, and mutation on the initial population to generate the first-generation sub-population and set the generation number Gen = 2; the first-generation sub-population contains N groups of device size parameters, and this size parameter group is obtained by the NSGA-II algorithm within the size parameter range of the devices in the circuit layout; normalize the N size parameter groups in the first-generation sub-population and input them into the layout network to obtain the predicted simulation data of the second step; input the predicted simulation data of the second step into a custom evaluation function to obtain an evaluation score group of the first-generation sub-population. The third step: Combine the parent population and the offspring population into a new population. The parent population is the population that generates the offspring population of this generation, and the parent population will be used multiple times in the loop; the new population obtains the optimal solutions in the initial population and the first-generation sub-population through the elite selection strategy, and retains the size parameter groups and evaluation score groups of the Pareto solutions. The fourth step: Determine whether a new parent population has been generated. If not, calculate the objective function of the individuals in the new population, perform fast non-dominated sorting, calculate the crowding degree, and generate a new parent population through the elite strategy operation; if so, go to the fifth step. The fifth step: Perform selection, crossover, and mutation operations on the generated parent population to generate an offspring population. The sixth step: Determine whether Gen is equal to the maximum generation number. If not, then the generation number Gen = Gen + 1 and return to the third step; otherwise, the algorithm runs to completion; output the size parameter groups and evaluation score groups of all Pareto solutions.

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