Integrated circuit including non-volatile memory

Abstract

The present application relates to an integrated circuit comprising a non-volatile memory. The integrated circuit comprises: a non-volatile memory having a plurality of memory cells, wherein each memory cell is configured to store information and to provide a read current whose intensity depends on the value stored therein when the memory cell is selected for reading; and a sense amplifier comprising: a first amplifier configured to amplify the read current of each memory cell selected for reading; an oscillation generator configured to generate, based on the amplified signal, a signal having oscillations according to a frequency depending on the intensity of the current of the amplified signal; a counter configured to count, over at least one given time period, the oscillations of the signal generated by the oscillation generator; and a digital processing circuit configured to determine, based on the value counted during the at least one given time period, the value represented by the amplified signal using a look-up table between the value counted by the counter and the value represented by the amplified signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to French application No. 2110247, filed on September 29, 2021, which is incorporated herein by reference. Technical Field

[0003] The various implementations and embodiments relate to integrated circuits, and more specifically to integrated circuits including non-volatile memory. Background Technology

[0004] Non-volatile memory is used to store information. Specifically, conventional non-volatile memory comprises multiple memory cells. These memory cells form the basic blocks of memory. Specifically, a memory cell is an electronic circuit configured to typically store a piece of binary information called a bit, that is, a piece of information that can be encoded at two levels, allowing it to have a value of "0" or "1". The memory cells of a memory are arranged in columns and rows.

[0005] More specifically, a memory cell may include a memory transistor with a floating gate configured to store a charge corresponding to a binary message. Summary of the Invention

[0006] To read a single piece of information recorded in a memory cell, each column of the memory cell is equipped with a sensing amplifier. This amplifier is used to detect and amplify a low-power signal representing a bit stored in that column of memory cells. These signals are amplified to a level that allows them to be used by circuitry external to the memory.

[0007] Some non-volatile memories are capable of storing information across more than two levels. Therefore, these memories comprise multi-level cells. In other words, such a memory cell is configured to store a single piece of information that can take more than two values ​​(not just "0" or "1"). Specifically, each memory cell is adapted to store more than one bit of information by discriminating the amount of charge that can be stored on the floating gate of the storage transistor. For example, a memory cell can allow the storage of four levels of information, thus corresponding to two bits. The use of multi-level memory cells allows for a reduction in the size of the memory and its manufacturing cost. However, known solutions do not guarantee sufficiently reliable retrieval of the information stored in the memory.

[0008] Furthermore, memory cells with multiple levels are typically sensitive to temperature variations and changes in the memory implementation. These sensitivities to temperature variations and changes in memory implementation can lead to errors when reading information stored in the memory, further reducing the reliability of such memory cells.

[0009] Furthermore, data stored in memory is typically processed by a processor. Therefore, the processor is configured to perform computations by processing this data. However, this involves relatively long data processing times. To reduce data processing time, some non-volatile memories are suitable for performing computations directly on the data they store (this method is also known as "in-memory computing"). Performing computations directly in memory allows avoiding the time loss associated with transferring data between memory and the processor. This type of non-volatile memory is particularly advantageous for certain applications, such as the execution of artificial neural networks. However, such memories are typically complex to manufacture.

[0010] Various embodiments provide a convenient non-volatile memory that allows information that can take more than two values ​​to be stored in the same memory cell.

[0011] According to one embodiment, an integrated circuit including non-volatile memory is proposed, the integrated circuit comprising:

[0012] Multiple memory cells, each configured to store one piece of information that can take more than two values, and each memory cell configured to circulate a read current when the memory cell is selected for reading, the read current having an intensity depending on the value stored in the memory cell.

[0013] The sensing amplifier includes:

[0014] An amplifier is configured to amplify the read current of each memory cell selected for reading.

[0015] The components include:

[0016] An oscillator is configured to generate an oscillating signal based on an amplified signal, the frequency of which depends on the strength of the current in the amplified signal.

[0017] A counter is configured to count the oscillations of a signal generated by an oscillator within at least a given time period.

[0018] The digital processing circuit is configured to determine the value represented by the amplified signal based on the value counted during at least one given time period, using a lookup table between values ​​that can be counted by a counter and values ​​that can be represented by an amplified signal.

[0019] Therefore, each memory cell is a multi-level unit that allows for increased memory density.

[0020] The determining component of the sensing amplifier allows for the determination of the value stored in the memory cell in a simple and reliable manner.

[0021] In one embodiment, the sensing amplifier is configured to sum the values ​​of information stored in several memory cells by selecting to read these various memory cells and by summing the read currents delivered by these selected memory cells before delivering the summed current to the amplifier of the sensing amplifier.

[0022] Therefore, the amplified summing current is sent to the oscillator. Thus, the number of oscillations counted by the counter is proportional to the sum of the information values ​​of the memory cells selected for reading.

[0023] Therefore, memory is suitable for performing addition operations directly within its internal memory units on information values ​​stored in several memory cells in a simple and fast manner. Specifically, addition operations can thus be performed directly in memory, rather than by the processor. This allows for the use of time to send the values ​​to be added from memory to the processor without incurring a loss.

[0024] In another embodiment, the sensing amplifier is configured to apply weights to the value of a piece of information stored in the memory cell by selecting the cell for reading during several given time periods.

[0025] The weight applied to the value of a piece of information stored in a memory cell corresponds to the number of time periods during which the memory cell is selected for reading.

[0026] Therefore, memory is suitable for performing weighting of the value of a piece of information stored in a memory cell directly within itself in a simple and fast manner. Specifically, weighting can therefore be performed directly in memory, rather than by the processor. This allows for the use of the time required to send the value to be weighted from memory to the processor without incurring a penalty.

[0027] In another embodiment, the sensing amplifier further includes a temperature compensation component, which includes a temperature sensor configured to measure the temperature of the memory, and the temperature compensation component is configured to adjust the control of the memory cell to adjust the read current generated by the memory cell according to the temperature measured by the temperature sensor.

[0028] Components designed to compensate for temperature allow for reduction or even elimination of errors in determining the value corresponding to the amplified signal, which may be caused by temperature variations in the memory.

[0029] In yet another embodiment, the sensing amplifier further includes a calibration component configured to:

[0030] Define the basic current at the input of the sense amplifier when no memory cell is selected, to define the expected minimum value that can be counted by the counter, and

[0031] Adjust the amplifier gain to obtain the desired maximum value that can be counted by the counter.

[0032] Therefore, the calibration component allows for automatic calibration of the sensing amplifier to reduce or even eliminate errors in determining the value corresponding to the amplified signal, which may be caused by variations in the implementation of the memory.

[0033] In various embodiments, the counter is eight-bit. Attached Figure Description

[0034] Other advantages and features of the invention will become apparent upon review of the detailed description of the embodiments and implementations (shown in a non-limiting manner) and the accompanying drawings, in which:

[0035] Figure 1 An integrated circuit according to an embodiment is illustrated;

[0036] Figure 2 A memory cell BC according to an embodiment is shown;

[0037] Figure 3 The illustration shows the distribution of the read current according to an embodiment;

[0038] Figure 4 The illustration shows a sense amplifier SA according to an embodiment; and

[0039] Figure 5 A timing diagram according to an embodiment is illustrated. Detailed Implementation

[0040] Figure 1 An integrated circuit CI according to an embodiment is illustrated.

[0041] The integrated circuit CI includes a memory MEM, which comprises several memory cells BC. Each memory cell BC is a multi-level cell. Therefore, each memory cell is configured to store one piece of information across more than two levels. Consequently, one piece of information stored in a memory cell can take more than two values.

[0042] Each memory cell BC includes an output configured to deliver an electrical signal of strength representing the value stored in the memory cell BC.

[0043] like Figure 2As illustrated, the memory cell BC may include a storage transistor TM and a selection transistor TS. The storage transistor TM is configured to store one piece of information on more than two stages.

[0044] Specifically, the storage transistor TM includes a source S1 connected to the drain D2 of the select transistor TS. The storage transistor TM also includes a drain D1, which forms the output of the memory cell BC. This output is connected to the bit line BL.

[0045] The storage transistor TM also includes a gate G1 and a floating gate FG1. The gate G1 is configured to receive a signal CG, which allows control of the gate G1 of the storage transistor to perform the writing of a piece of information in the storage transistor TM or the reading of a piece of information stored in the storage transistor TM.

[0046] Specifically, the floating gate FG1 is configured to store charge based on the current applied to the gate G1. The amount of charge stored corresponds to a piece of information stored by the storage transistor TM. The storage transistor TM is configured to store various amounts of charge. When a piece of information stored in the storage transistor is read, a read current is generated. This read current depends on the amount of charge stored by the floating gate FG1.

[0047] For example, Figure 3 The diagram illustrates the distribution of read currents corresponding to a message that can take four values. Therefore, the first-stage read current N0 with a standard deviation σ0 corresponds to the value "0", the second-stage read current N1 with a standard deviation σ1 corresponds to the value "1", the third-stage read current N2 with a standard deviation σ2 corresponds to the value "2", and the fourth-stage read current N3 with a standard deviation σ3 corresponds to the value "3". The value of a message stored by the storage transistor TM can therefore be represented using two bits.

[0048] The select transistor TS includes a source S2 connected to the source line SL, which is connected to the cold point, specifically ground GND. The select transistor TS also includes a gate G2 configured to receive a signal WL. The signal WL allows selection of the memory cell BC to read or write a piece of information from the storage transistor TM.

[0049] The memory cells BC of a memory can be divided into various groups. For example, a group of four memory cells BC1, BC2, BC3, and BC4 is... Figure 1 As shown in the image.

[0050] For each group of memory cells BC, the memory MEM also includes a sense amplifier SA. The sense amplifier SA is adapted to read information stored in the memory cells of the same group. The sense amplifier SA is also adapted to perform calculations on the information stored in the memory cells of the same group.

[0051] Specifically, the sensing amplifier SA is connected to the output of each memory cell BC so as to receive a current representing a piece of information stored in the memory cell BC.

[0052] The sensing amplifier SA includes a weighting component WM, which allows weights to be applied to the information stored in the memory.

[0053] The sensing amplifier SA also includes an adder AM, which allows weighted or unweighted information to be added together.

[0054] The sensing amplifier SA also includes a detection component DM, which is configured to determine a weighted or unweighted value of the information stored in the memory cell BC, or to determine a value calculated by the addition component AM based on the value of the information stored in the memory cell BC. The value determined by the detection component DM is therefore indicated in the digital signal Sout.

[0055] Specifically, the detection components DM include an oscillator RO (“ring oscillator”), a counter CPT, and a digital processing circuit DB. These detection components DM are described in detail below.

[0056] The memory also provides a reference current CR. These reference currents are used by the temperature compensation component TCM, and the calibration component CAM described below.

[0057] Figure 4 An embodiment of the sense amplifier SA is illustrated. The sense amplifier SA has an input connected to a bit line BL, which is configured to receive read current from memory cells in the same group connected to the bit line BL.

[0058] The signal on bit line BL therefore has a strength equal to the sum of the read currents from the selected memory cell BC. Thus, since the strength of the read current from the memory cell depends on the value of a piece of information stored in that memory cell, the strength of the signal on bit line BL depends on the sum of the values ​​stored in the selected memory cell BC.

[0059] Specifically, the sense amplifier SA includes an operational amplifier AOP configured to polarize the bit line BL to obtain a read current circulating in the memory cell BC readable by the sense amplifier SA. The operational amplifier AOP is configured to receive signals for the bit line BL and BG, and to deliver a signal VBIAS, which allows the bit line to be polarized via a capacitor element CAP. The signal VBIAS is generated based on the signal BG used to polarize the bit line BL.

[0060] The sensing amplifier SA also includes an amplifier CM, which allows amplification of the signal on the bit line BL. The amplifier CM may be a current mirror. The amplifier CM has an input connected to the bit line BL to receive the signal circulating on the bit line BL. The amplifier CM also has an input configured to receive a signal VBIAS generated by the operational amplifier AOP to activate the sensing amplifier SA.

[0061] The amplifier CM also has an output configured to deliver an amplified signal SGA based on a signal circulating on the bit line BL. The amplifier CM allows the signal on the bit line BL to be amplified so that the latter has an amplitude sufficient for operation of the oscillator RO.

[0062] Specifically, the oscillator RO includes an input configured to receive an amplified signal SGA delivered by the amplifier CM. The oscillator RO also has an output configured to deliver an output signal SGO, which exhibits regular continuous oscillations, specifically a burst of pulses. The oscillation frequency in the output signal depends on the strength of the amplified signal received at the oscillator's input. Specifically, the greater the strength of the amplified signal SGA, the higher the oscillation frequency in the output signal SGO. Therefore, the oscillation frequency directly depends on the current delivered by the memory cell BC selected for reading.

[0063] The counter CPT includes an input configured to receive a signal SGO delivered at the output of the oscillator RO. The counter CPT is configured to count the number of oscillations CNT in the signal SGO over at least one given time period. Therefore, the higher the oscillation frequency in the signal SGO, the larger the count value CNT of the counter during that time period. Consequently, the relationship between the count value CNT and the current on the bit line BL is a linear transfer function.

[0064] Preferably, the counter CPT is 8-bit.

[0065] The digital processing circuit DB is configured to determine the value corresponding to the signal on the bit line BL based on the value CNT counted by the counter CPT.

[0066] Specifically, the digital processing circuit DB can use a lookup table that matches the value CNT, which can be counted by a counter, with the sum of the values ​​stored in the memory cell BC that indicate the selected read.

[0067] Therefore, a memory can simply determine the value of the information stored in a memory cell.

[0068] Furthermore, the sensing amplifier SA is configured to apply weights to the values ​​of information stored in the memory cell BC. This weighting is performed by modifying the selection of the memory cell BC over time. Specifically, the weight applied to the values ​​stored in the memory cell BC corresponds to the number of time periods during which the memory cell BC is selected. Therefore, by controlling the selection time of the memory cell BC, the weight applied to the value of a piece of information stored in the memory cell BC is simply defined.

[0069] Furthermore, the digital processing circuit DB is configured to perform a subtraction operation between the values ​​of the information stored in the memory unit BC based on the reading of the value of the minuend forming the subtraction operation and the reading of the value of the subtrahend forming the subtraction operation. Specifically, before performing the subtraction operation using the digital processing circuit DB, the value of the minuend forming the subtraction operation is added during the first read, and the value of the subtrahend forming the subtraction operation is added during the second read.

[0070] Therefore, the memory MEM is configured to perform calculations internally in a simple and fast manner. Thus, it is not necessary to send the information values ​​stored in the memory cells to the processor to perform these calculations.

[0071] The sensing amplifier SA also includes a temperature compensation component (TCM) configured to compensate for errors that may be caused by temperature variations in the memory MEM. The TCM may include a temperature sensor suitable for sensing the temperature of the memory. The TCM may also include a reference value stored in the memory cell BC and allow the delivery of a reference current CR. When the sensor detects a temperature change, the digital processing circuit DB is therefore configured to adjust the voltage of the signal delivered to the floating gate of the storage transistor based on a comparison between the value read from the memory cell BC based on the stored reference value and the recorded reference value.

[0072] The sensing amplifier SA also includes a calibration component CAM, which is configured to automatically calibrate the sensing amplifier SA. Calibration allows compensation for variations in the implementation of the memory. Specifically, the calibration component CAM allows calibration of the linear transfer function between the value counted by the counter and the current on the bit line. The calibration component CAM is therefore configured to adjust the ratio between the value counted by the counter and the current on the bit line. The calibration component CAM can be activated by digital processing circuitry. Specifically, the calibration component CAM includes a first circuit CAM1, which is configured to define a base current on the bit line when no memory cell BC is selected, in order to define a desired minimum value that can be counted by the counter. The calibration component also includes a second circuit CAM2, which is configured to adjust the amplifier gain to obtain a desired maximum value that can be counted by the counter when the current on the bit line is high (i.e., when all memory cells BC1, BC2, BC3, and BC4 are selected). The calibration performed by the calibration component CAM can be performed using a reference current CR.

[0073] Figure 5 An embodiment of an integrated circuit is illustrated, which allows the calculation of the value Sout corresponding to the following formula:

[0074] Sout = W1*B1 + W2*B2 + W3*B3 + W4*B4, where B1, B2, B3 and B4 are the values ​​stored in memory units BC1, BC2, BC3 and BC4 respectively, and W1, W2, W3 and W4 are the weights to be applied to values ​​B1, B2, B3 and B4 respectively.

[0075] Here, values ​​B1, B2, B3, and B4 are equal to 3. Values ​​W1 are equal to 1, W2 is equal to 2, W3 is equal to 3, and W4 is equal to 4.

[0076] Signals WL1, WL2, WL3, and WL4 represent the signals used to select memory cells BC1, BC2, BC3, and BC4 for reading, respectively.

[0077] Curve I_TOT represents the current intensity received at the input of oscillator RO. Curve ROF represents the frequency of oscillator RO. Curve CNT represents the value counted by counter CPT.

[0078] Since the maximum weight is equal to 4, the value Sout is calculated over four time intervals, T1 to T4. Each time interval is 40 nanoseconds.

[0079] During the first time period T1, memory cells BC1, BC2, BC3, and BC4 are all selected. The current intensity on the bit lines is therefore approximately 40 microamperes. Consequently, the frequency of the signal at the output of the oscillator is 750 MHz. Therefore, at the end of the first time period, the counter value is equal to 96. This value corresponds to the value S1 = B1 + B2 + B3 + B4.

[0080] Then, during the second time period T2, only memory cells BC2, BC3, and BC4 are selected. Therefore, memory cell BC1 is not selected. The current intensity on the bit line is therefore approximately 30 microamps. Consequently, the frequency of the signal at the output of the oscillator is 570 MHz. Therefore, at the end of the second time period, the counter value is equal to 144. This value corresponds to the value S2 = S1 + B2 + B3 + B4 = B1 + 2*B2 + 2*B3 + 2*B4.

[0081] Then, during the third time period T3, only memory cells BC3 and BC4 are selected. Therefore, memory cells BC1 and BC2 are not selected. The current intensity on the bit lines is therefore approximately 20 microamps. Consequently, the frequency of the signal at the output of the oscillator is 380 MHz. Therefore, at the end of the second time period, the counter value is equal to 168. This value corresponds to the value S3 = S2 + B3 + B4 = B1 + 2*B2 + 3*B3 + 3*B4.

[0082] Finally, during the fourth time period T4, only memory cell BC4 is selected. Therefore, memory cells BC1, BC2, and BC3 are not selected. The current intensity on the bit line is therefore approximately 10 microamps. Consequently, the frequency of the signal at the output of the oscillator is 190 MHz. Therefore, at the end of the second time period, the counter value is equal to 180. This value corresponds to the value Sout = S3 + B4 = B1 + 2*B2 + 3*B3 + 4*B4 = 30.

[0083] Although the invention has been described with reference to illustrative embodiments, this description is not intended to be limiting. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those skilled in the art during the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. An integrated circuit, comprising: Non-volatile memory, including: Multiple memory units, Each memory cell is configured to store information, and Each memory cell is configured to provide a read current, the strength of which depends on the value stored in the memory cell when the memory cell is selected for reading; and The sensing amplifier includes: A first amplifier is configured to amplify the read current of each memory cell selected for reading to generate an amplified signal; An oscillator is configured to generate a signal with oscillations according to a frequency based on the amplified signal, the frequency depending on the strength of the current in the amplified signal; A counter is configured to count the oscillations of the signal generated by the oscillation generator within at least a given time period; and A digital processing circuit is configured to determine the value represented by the amplified signal based on the value counted during the at least one given time period, using a lookup table between the value that can be counted by the counter and the value that can be represented by the amplified signal.

2. The integrated circuit of claim 1, wherein the sensing amplifier is configured to provide a value of information stored in a plurality of memory cells by reading the selected memory cells and by summing the read currents provided by the selected memory cells before delivering the summed current to the first amplifier.

3. The integrated circuit of claim 1, wherein the sensing amplifier is configured to apply weights to the values ​​of information stored in the memory cell by selecting to read the memory cell.

4. The integrated circuit of claim 1, wherein the sensing amplifier further comprises a temperature sensor configured to measure the temperature of the memory, the temperature sensor being configured to adjust control of the memory cell to adjust the read current generated by the memory cell based on the temperature measured by the temperature sensor.

5. The integrated circuit of claim 4, wherein the digital processing circuit includes the temperature sensor.

6. The integrated circuit of claim 4, wherein the digital processing circuit is configured to adjust a voltage signal to the floating gate of the memory cell, and wherein the voltage signal is adjusted based on a reference value when the sensor detects a temperature change.

7. The integrated circuit of claim 1, wherein the sensing amplifier further comprises a calibrator configured to: Define a basic current at the input of the sense amplifier when no memory cell is selected, to define the expected minimum value that can be counted by the counter; and The gain of the amplifier is adjusted to obtain the desired maximum value that can be counted by the counter.

8. The integrated circuit of claim 1, wherein the counter is eight-bit.

9. An integrated circuit, comprising: Non-volatile memory, including: Multiple memory units, Each memory cell is configured to store information, and Each memory cell is configured to provide a read current, the strength of which depends on the value stored in the memory cell when the memory cell is selected for reading; and The sensing amplifier includes: The input is configured to receive the read current; A first amplifier is configured to amplify the read current to generate an amplified signal; An oscillator is configured to generate an oscillator signal that oscillates continuously according to a frequency that depends on the strength of the current in the amplified signal. A counter is configured to count the number of regular continuous oscillations of the oscillation generator signal within at least a given time period, and to provide a count value; and A digital processing circuit is configured to determine a value represented by the count value counted during the at least one given time period using a lookup table of values ​​that can be counted by the counter and values ​​that can be represented by the count value.

10. The integrated circuit of claim 9, wherein the sensing amplifier further comprises an operational amplifier configured to: The read current is received at the first input of the operational amplifier; A signal is received at the second input of the operational amplifier; and At the output of the operational amplifier, a bias signal is provided to the first amplifier.

11. The integrated circuit of claim 10, wherein the first input of the operational amplifier is directly connected to the input of the sensing amplifier, and the output of the operational amplifier is directly connected to the first amplifier, wherein the first amplifier is directly connected to the input of the sensing amplifier, and wherein a capacitor element is directly connected to the output of the operational amplifier, directly connected to the first amplifier, and directly connected to the input of the sensing amplifier.

12. The integrated circuit of claim 10, further comprising a bit line between the inputs of the first amplifier and the sense amplifier, wherein the operational amplifier is configured to provide the bias signal, the bias signal allowing the bit line to be polarized via a capacitive element.

13. The integrated circuit of claim 9, wherein the sensing amplifier is configured to provide a value of information stored in a plurality of memory cells by reading the selected memory cells and by summing the read currents provided by the selected memory cells before delivering the summed read currents to the first amplifier.

14. The integrated circuit of claim 9, wherein the sensing amplifier is configured to apply weights to the values ​​of information stored in the memory cell by selecting to read the memory cell.

15. The integrated circuit of claim 9, wherein the sensing amplifier further comprises a temperature sensor configured to measure the temperature of the memory, the temperature sensor being configured to adjust control of the memory cell to adjust the read current generated by the memory cell based on the temperature measured by the temperature sensor.

16. The integrated circuit of claim 15, wherein the digital processing circuit includes the temperature sensor.

17. The integrated circuit of claim 15, wherein the digital processing circuit is configured to adjust a voltage signal to the floating gate of the memory cell, and wherein the voltage signal is adjusted based on a reference value when the sensor detects a temperature change.

18. The integrated circuit of claim 9, wherein the sensing amplifier further comprises a calibrator configured to: Define a basic current at the input of the sense amplifier when no memory cell is selected, to define the expected minimum value that can be counted by the counter; and The gain of the amplifier is adjusted to obtain the desired maximum value that can be counted by the counter.

19. The integrated circuit of claim 9, wherein the counter is eight-bit.

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