Multilayer ceramic capacitor

Abstract

The present application provides a kind of high voltage reliability of layered ceramic capacitor with.This layered ceramic capacitor (1) of the present application has: layered body (2), with: inner layer (11), inside electrode layer (15) and internal dielectric layer (14) are alternately stacked in multiple layers, and both ends in the stacking direction (T) are internal electrode layer (15);And external dielectric layer (20), cover the inner layer (11);And two external electrodes (3), respectively arranged in the layered body (2) as the end surface (C) of the face of the two sides in the length direction (L) crossing the stacking direction (T), the internal dielectric layer (14) and the external dielectric layer (20) include particles, the average particle size of the particles included in the internal dielectric layer (14) and the average particle size of the particles included in the external dielectric layer (20) are less than or equal to 100 nm.

Description

TECHNICAL FIELD

[0001] The present application relates to a multilayer ceramic capacitor. BACKGROUND

[0002] A multilayer ceramic capacitor produced by alternately stacking a plurality of dielectric layers and a plurality of internal electrode layers and then firing is known. In recent years, downsizing and large capacitance of such a multilayer ceramic capacitor are progressing. Also, in order to achieve downsizing and large capacitance, the internal electrode layers and the internal dielectric layers are thinned (for example, refer to Patent Literature 1).

[0003] PRIOR ART DOCUMENTS

[0004] PATENT LITERATURE

[0005] Patent Literature 1: Japanese Patent Application Publication No. 2021-082779

[0006] However, if the internal dielectric layers are thinned, the contact area between the internal dielectric layers and the dielectric layers in contact with the internal dielectric layers decreases, and thus peeling becomes easy, and there is a possibility that the insulation breakdown voltage decreases and the voltage resistance reliability decreases. SUMMARY

[0007] PROBLEMS TO BE SOLVED BY THE INVENTION

[0008] An object of the present application is to provide a multilayer ceramic capacitor having high voltage resistance reliability.

[0009] TECHNICAL SOLUTION TO THE PROBLEM

[0010] In order to solve the above problem, the present application provides a multilayer ceramic capacitor including: a laminate including: an inner layer portion in which a plurality of internal electrode layers and a plurality of internal dielectric layers are alternately stacked, and both ends in a stacking direction are internal electrode layers; and an external dielectric layer covering the inner layer portion; and two external electrodes disposed at end surfaces of the laminate as faces on both sides in a length direction crossing the stacking direction, the internal dielectric layers and the external dielectric layer containing particles, and a difference between an average particle diameter of the particles contained in the internal dielectric layers and an average particle diameter of the particles contained in the external dielectric layer being 100 nm or less.

[0011] EFFECT OF THE INVENTION

[0012] According to the present application, a multilayer ceramic capacitor having high voltage resistance reliability can be provided. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a schematic perspective view of a multilayer ceramic capacitor 1 of an embodiment.

[0014] Figure 2 isFigure 1 Cross-sectional view of the multilayer ceramic capacitor 1 along line II-II.

[0015] Figure 3 Figure 1 Cross-sectional view of the multilayer ceramic capacitor 1 along line III-III.

[0016] Figure 4 Example of an enlarged image of a cross section of the exposed inner layer portion 11.

[0017] Figure 5 Figure 3 Enlarged view of the P portion surrounded by a circle of the multilayer ceramic capacitor 1.

[0018] Figure 6 Flowchart illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0019] Figure 7 Diagram illustrating the manufacturing method of the multilayer ceramic capacitor 1.

[0020] Figure 8 Table showing the values of the insulation breakdown voltage of the multilayer ceramic capacitor 1 containing particles g of different particle diameters.

[0021] BRIEF DESCRIPTION OF DRAWINGS

[0022] g: particle;

[0023] 1: multilayer ceramic capacitor;

[0024] 2: laminate;

[0025] 3: external electrode;

[0026] 10: laminate chip;

[0027] 11: inner layer portion;

[0028] 14: internal dielectric layer;

[0029] 14g: particle;

[0030] 15: internal electrode layer;

[0031] 20: external dielectric layer;

[0032] 21: side margin portion;

[0033] 21a: outer side layer;

[0034] 21b: inner side layer;

[0035] 21g: particle;

[0036] 22: outer layer portion;

[0037] ​​22g: granules;

[0038] 30: base electrode layer;

[0039] 31: plating layer. DETAILED DESCRIPTION

[0040] (Laminated ceramic capacitor 1)

[0041] Hereinafter, a laminated ceramic capacitor 1 related to an embodiment of the present application will be described. Figure 1 is a schematic perspective view of the laminated ceramic capacitor 1 of the embodiment. Figure 2 is a cross-sectional view of the laminated ceramic capacitor 1 of Figure 1 along line II-II. Figure 3 is a cross-sectional view of the laminated ceramic capacitor 1 of Figure 1 along line III-III.

[0042] The laminated ceramic capacitor 1 is roughly rectangular parallelepiped-shaped, and has a laminated body 2 and a pair of external electrodes 3 provided at both ends of the laminated body 2. The laminated body 2 includes an inner layer portion 11 in which internal dielectric layers 14 and internal electrode layers 15 are laminated, and an external dielectric layer 20 covering the inner layer portion 11.

[0043] (Dimensions of the laminated ceramic capacitor 1)

[0044] With respect to the dimensions of the laminated ceramic capacitor 1, for example, the width direction W is 0.1 mm or more and 0.5 mm or less, the thickness direction is 0.1 mm or more and 0.5 mm or less, and the length direction L is 0.05 mm or more and 1.0 mm or less.

[0045] In the following description, as a term indicating the orientation of the laminated ceramic capacitor 1, in the laminated ceramic capacitor 1, the direction in which the pair of external electrodes 3 is provided is set as the length direction L. The direction in which the internal dielectric layers 14 and the internal electrode layers 15 are laminated is set as the laminating direction T. The direction intersecting either one of the length direction L and the laminating direction T is set as the width direction W. In addition, in the embodiment, the width direction W is orthogonal to either one of the length direction L and the laminating direction T. In the laminated ceramic capacitor 1 of the embodiment, the length direction L is longer than the width direction W and the laminating direction T, but is not limited thereto, and the length direction L size can also be not longer than the width direction W and the laminating direction T.

[0046] Further, in the following description, among the six outer surfaces of the laminate 2, a pair of outer surfaces opposite each other in the stacking direction T are set as the first main surface Al and the second main surface A2, a pair of outer surfaces opposite each other in the width direction W are set as the first side surface Bl and the second side surface B2, and a pair of outer surfaces opposite each other in the length direction L are set as the first end surface Cl and the second end surface C2. In addition, in cases where it is not necessary to particularly distinguish the first main surface Al and the second main surface A2 for the description, they are uniformly described as the main surface A, in cases where it is not necessary to particularly distinguish the first side surface Bl and the second side surface B2 for the description, they are uniformly described as the side surface B, and in cases where it is not necessary to particularly distinguish the first end surface Cl and the second end surface C2 for the description, they are uniformly described as the end surface C.

[0047] (Laminate 2)

[0048] The laminate 2 has the laminate chip 10 and the side margin portions 21 disposed on both sides in the width direction W of the laminate chip 10. The laminate chip 10 has the inner layer portion 11 in which the internal dielectric layers 14 and the internal electrode layers 15 are stacked, and the two outer layer portions 22 disposed on both sides in the stacking direction T of the inner layer portion 11. In the embodiment, the outer layer portions 22 and the side margin portions 21 together are the external dielectric layer 20 that covers the inner layer portion 11.

[0049] The laminate 2 is substantially rectangular parallelepiped-shaped, but preferably has rounded corners at the corner portions Rl and the ridge line portions R2. The corner portion Rl is a portion where the main surface A, the side surface B, and the end surface C intersect. The ridge line portion R2 is a portion where two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C intersect.

[0050] (Inner layer portion 11)

[0051] The inner layer portion 11 is a portion in which the internal dielectric layers 14 and the internal electrode layers 15 are alternately stacked along the stacking direction T, and in the embodiment, both ends in the stacking direction T of the inner layer portion 11 are the internal electrode layers 15. That is, the inner layer portion 11 is a portion between the internal electrode layers 15, and the internal dielectric layers 14 and the internal electrode layers 15 are alternately stacked therebetween.

[0052] (Internal electrode layer 15)

[0053] The internal electrode layer 15 has a plurality of first internal electrode layers 15A and a plurality of second internal electrode layers 15B. The first internal electrode layers 15A and the second internal electrode layers 15B are alternately disposed. In addition, in cases where it is not necessary to particularly distinguish the first internal electrode layers 15A and the second internal electrode layers 15B for the description, they are uniformly described as the internal electrode layer 15.

[0054] The inner electrode layer 15 may contain Ni (nickel) as the main component, and may further contain dielectric particles with the same composition as the ceramic contained in the inner dielectric layer 14. Sulfur (S) segregates to the interface with the inner dielectric layer 14. Furthermore, Sn (tin) may be disposed at the interface between the inner electrode layer 15 and the inner dielectric layer 14. In this case, Sn may be layered or dispersed. Additionally, Sn may be dissolved in the dielectric particles on the inner electrode layer 15 side or on the dielectric layer side.

[0055] The first internal electrode layer 15A has a first opposing portion 15Aa opposite to the second internal electrode layer 15B, and a first lead-out portion 15Ab extending from the first opposing portion 15Aa toward the first end face C1. The end of the first lead-out portion 15Ab is exposed at the first end face C1 and is electrically connected to the first external electrode 3A described later. The second internal electrode layer 15B has a second opposing portion 15Ba opposite to the first internal electrode layer 15A, and a second lead-out portion 15Bb extending from the second opposing portion 15Ba to the second end face C2. The end of the second lead-out portion 15Bb is electrically connected to the second external electrode 3B described later. The internal electrode layer 15, sandwiching the internal dielectric layer 14, stores charge between the first opposing portion 15Aa of the first internal electrode layer 15A and the second opposing portion 15Ba of the second internal electrode layer 15B, thus functioning as a capacitor.

[0056] like Figure 3 As shown, in the cross-section WT along the width direction W and the stacking direction T passing through the center of the laminate 2, the offset d of the ends of the two adjacent first internal electrode layers 15A and second internal electrode layers 15B in the width direction W along the stacking direction T is preferably 5 μm or less, more preferably 0.5 μm or less. That is, the ends of the adjacent first internal electrode layers 15A and second internal electrode layers 15B in the width direction W along the stacking direction T are at approximately the same position in the width direction W, and the positions of the ends are aligned in the stacking direction T.

[0057] The number of internal electrode layers 15 is preferably 10 or more and less than 1000.

[0058] The thickness of the internal electrode layer 15 is preferably 0.3 μm or more and 0.4 μm or less, more preferably 0.3 μm or more and 0.35 μm or less.

[0059] The thickness of the internal electrode layer 15 is measured, for example, as follows. First, the inner layer 11 is exposed by grinding a cross-section LT passing through the center of the multilayer ceramic capacitor 1. If necessary, the cross-section exposing the observation position is etched to remove the conductive layer that has been stretched due to grinding.

[0060] Figure 4 is an example of an enlarged view of a cross section of the exposed inner layer portion 11. In the illustrated enlarged view, for example, a plurality of straight lines La, Lb, Lc, Ld, Le extending in the stacking direction T are drawn at intervals of a pitch S. The pitch S is preferably 5 to 10 times the thickness of the internal electrode layer 15 to be measured, and for example, in the case of measuring an internal electrode layer 15 having a thickness of about 1 μm, the pitch S is set to 5 μm.

[0061] Next, the thickness da, db, dc, dd, de of each internal electrode layer 15 is measured on each of the five straight lines La, Lb, Lc, Ld, Le. However, in the case where the internal electrode layer 15 is missing on the straight lines La, Lb, Lc, Ld, Le, and the internal dielectric layer 14 sandwiching the internal electrode layer 15 is connected to each other, or in the case where the enlarged view of the measurement position is unclear, a new straight line is drawn, and the thickness of the internal electrode layer 15 is measured.

[0062] In addition, in the case where the number of layers of the internal electrode layer 15 is less than five, the thickness of all the internal electrode layers 15 is measured by the above-described method, and the average value thereof is taken as the average thickness of the plurality of internal electrode layers 15. The thickness of the internal dielectric layer 14 can also be measured in the same manner as the internal electrode layer 15.

[0063] (internal dielectric layer 14)

[0064] The internal dielectric layer 14 is, for example, a dielectric ceramic containing Ba and Ti components, and contains Si. In addition, a material in which a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, or the like is added in an amount smaller than the main components can also be used. In the embodiment, the molar ratio of Si to Ti in the internal dielectric layer 14 is 0.8 mol% or more and 1.4 mol% or less, but is not limited thereto. In addition, the Si content can be calculated by TEM analysis.

[0065] In addition, the internal dielectric layer 14 contains a plurality of particles (granular substances) 14g. Figure 5 is an enlarged view of the P portion surrounded by a circle of Figure 3 The particles 14g are a perovskite compound containing Ba and Ti, or the like barium titanate-based ceramic, and contain Si and other sub-components. The sub-components are at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y. The particle 14g contained in the internal dielectric layer 14 has a particle diameter of 140 nm or more and 270 nm or less.

[0066] (measurement method of particle diameter)

[0067] The particle diameter of the particles 14g of the inner dielectric layer 14 is the particle diameter of the central portion in the width direction W and the central portion in the length direction L. Further, the particle diameter of the particles 22g of the outer layer portion 22 described later is the particle diameter of the central portion in the width direction W and the central portion in the length direction L, and the particle diameter of the particles 21g of the side margin portion 21 is the particle diameter of the central portion in the width direction W and the central portion in the stacking direction T. In the case where the side margin portion 21 is multilayered, the width direction W is divided into a plurality of regions by 20 nm from the side of the side surface B, the area of each of the particles 21g is measured in each region, and the equivalent circle diameter is converted, and the average particle diameter in each region is taken as the particle diameter of the region. In the case of a region of less than 20 nm, the average particle diameter in the region is taken as the particle diameter of the region. The particle diameter of the particles 21g of the entire side margin portion 21 is the particle diameter obtained by further averaging the average particle diameters of the regions. Hereinafter, in the case where it is not necessary to distinguish the particles 14g of the inner dielectric layer 14, the particles 22g of the outer layer portion 22, and the particles 21g of the side margin portion 21, they are described as the particles g.

[0068] The measurement of each particle diameter can be performed using a transmission electron microscope (TEM). For example, in the range of a field of view of 10 μm x 10 μm, the area of the particles g in the field of view is measured, the equivalent circle diameter is calculated for each of the particles g, and the average value of the equivalent circle diameters is taken as the particle diameter.

[0069] (Number of sheets of the inner dielectric layer 14)

[0070] The number of sheets of the inner dielectric layer 14 and the outer layer portion 22 taken together is preferably 100 sheets or more and 2000 sheets or less.

[0071] (Thickness of the inner dielectric layer 14)

[0072] The inner dielectric layer 14 is preferably 0.4 μm or more and 0.5 μm or less, and more preferably 0.4 μm or more and 0.45 μm or less. Further, as described above, the thickness of the inner dielectric layer 14 can be obtained in the same manner as the inner electrode layer 15 by measuring the thickness Da, Db, Dc, Dd, De of each of the inner dielectric layers 14 on each of the five straight lines La, Lb, Lc, Ld, Le and taking the average.

[0073] (Outer dielectric layer 20)

[0074] The outer dielectric layer 20 that covers the inner layer portion 11 has an outer layer portion 22 and a side margin portion 21. The outer dielectric layer 20 is made of the same material as the inner dielectric layer 14 and contains a plurality of particles 22g and particles 21g, respectively. Among them, the molar ratio of Si to Ti in the outer dielectric layer 20 is less than that of the inner dielectric layer 14, and is 0.8 mol% or less, and preferably 0.5 mol% or less. In addition, the outer dielectric layer 20 contains Ni.

[0075] The particles g contained in the inner dielectric layer 14 and the outer dielectric layer 20 have a particle diameter of 140 nm or more and 270 nm or less. The average particle diameter of the particles 14g contained in the inner dielectric layer 14 and the average particle diameters of the particles 22g and the particles 21g contained in the outer dielectric layer 20 are substantially equal, and the difference in particle diameter is 100 nm or less. In addition, the difference between the average particle diameter of the particles 14g contained in the inner dielectric layer 14 and the average particle diameters of the particles 22g and the particles 21g contained in the outer dielectric layer 20 is within 36% if expressed in %.

[0076] (Outer layer portion 22)

[0077] The outer layer portion 22 is located on the both main surface A side of the laminate 2, and is a dielectric layer located between the main surface A and the inner electrode layer 15 closest to the main surface A.

[0078] (Side margin portion 21)

[0079] The side margin portion 21 is disposed on the both side surface B side of the laminate chip 10, that is, on the both side surface B side of the outer layer portion 22 and the inner layer portion 11, and covers the side surface B side of the outer layer portion 22 and the inner layer portion 11. A certain width range of the side surface B side of the laminate chip 10 is the side margin portion 21.

[0080] The side margin portion 21 of the embodiment is a two-layer structure of an outer side layer 21a located on the outer side and an inner side layer 21b located on the inner electrode layer 15 side. However, it is not limited thereto, and the side margin portion 21 can be one layer, and in addition, can be two or more layers. In addition, in the case where the side margin portion 21 is a plurality of layers, it can be confirmed to be a plurality of layers by dark field of an optical microscope, and in addition, it can be discriminated to be a plurality of layers by an additive or the like that is segregated to the layers. The inner side layer 21b of the embodiment is a thickness of, for example, 1 / 10 of the outer side layer 21a, and is considerably thin compared to the outer side layer 21a.

[0081] As for the side margin portion 21, when the entirety is averaged as the external dielectric layer 20 as described above, the molar ratio of Si to Ti is less than that of the internal dielectric layer 14, and is 0.8 mol% or less, preferably 0.5 mol% or less. As for the Si content of the entirety of the side margin portion 21, the Si contents of the outer layer 21a and the inner layer 21b can be calculated separately and then added together.

[0082] In the case where the side margin portion 21 is two layers, the molar ratio of Si to Ti of the inner layer 21b is less than that of the outer layer 21a. In the case where there are multiple layers, if the outermost side margin portion is taken as the outer layer 21a and the innermost side margin portion is taken as the inner layer 21b, the molar ratio of Si to Ti of the inner layer 21b is also less than that of the outer layer 21a. Specifically, the molar ratio of Si to Ti of the inner layer 21b is 0.01 to 0.1 mol%, and is preferably almost zero. The molar ratio of Si to Ti in the outer layer 21a is 0.8 mol% or less, and is preferably 0.5 mol% or less.

[0083] Further, in the side margin portion 21, the particle diameter of the particles of the dielectric that constitute the side margin portion 21 decreases from the inner layer toward the outer layer.

[0084] (External electrode 3)

[0085] The external electrode 3 has a first external electrode 3A provided on the first end surface C1 of the laminate 2, and a second external electrode 3B provided on the second end surface C2 of the laminate 2. In cases where it is not necessary to distinguish between the first external electrode 3A and the second external electrode 3B, they are described as the external electrode 3. The external electrode 3 covers not only the end surface C, but also a portion of the main surface A and the end surface C side of the side surface B.

[0086] As described above, the end portion of the first lead-out portion 15Ab of the first internal electrode layer 15A is exposed on the first end surface C1 and is electrically connected to the first external electrode 3A. Further, the end portion of the second lead-out portion 15Bb of the second internal electrode layer 15B is exposed on the second end surface C2 and is electrically connected to the second external electrode 3B. Thus, the first external electrode 3A and the second external electrode 3B are electrically connected in parallel to a plurality of capacitor elements.

[0087] In the embodiment, the external electrode 3 includes a base electrode layer 30 and a plating layer 31 disposed on the base electrode layer 30.

[0088] (Base electrode layer 30)

[0089] The base electrode layer 30 includes at least one layer selected from a fired layer 30a, a conductive resin layer 30b, a thin film layer 30c, and the like. In an embodiment, the three layers of the fired layer 30a, the conductive resin layer 30b, and the thin film layer 30c are included.

[0090] (Fired layer 30a)

[0091] As the metal of the fired layer 30a, at least one selected from Cu, Ni, Ag, Pd, an Ag-Pd alloy, Au, and the like is included, for example. The fired layer 30a can be one layer or multiple layers. The fired layer 30a is formed by applying a conductive paste including glass and a metal to the laminate 2 and performing firing. In an embodiment, the fired layer 30a is fired at the same time as the internal electrode layer 15, but is not limited thereto and can be fired after the internal electrode layer 15 is fired.

[0092] (Conductive resin layer 30b)

[0093] In an embodiment, the conductive resin layer 30b includes conductive particles and a thermosetting resin. As a specific example of the thermosetting resin, various known thermosetting resins such as an epoxy resin, a phenol resin, a polyurethane resin, a silicone resin, a polyimide resin, and the like can be used, for example. As a metal component, Ag or a metal powder on which Ag coating is performed on the surface of a base metal powder can be used, for example. In the case where the conductive resin layer 30b is formed, the fired layer 30a can not be formed and can be directly formed on the laminate 2. The conductive resin layer 30b can be one layer or multiple layers.

[0094] The conductive resin layer 30b includes a thermosetting resin, and thus is soft, for example, compared to the fired layer 30a composed of a plated film, a fired product of a conductive paste. Therefore, even in the case where a physical impact is applied to the multilayer ceramic capacitor 1 or an impact due to thermal cycles is applied, the conductive resin layer 30b functions as a buffer layer, prevents cracks from being generated in the multilayer ceramic capacitor 1, and easily absorbs piezoelectric vibration, having an effect of suppressing "singing".

[0095] (Thin film layer 30c)

[0096] The thin film layer 30c is a layer of 1 μm or less in which metal particles are deposited by a thin film formation method such as a sputtering method or an evaporation method.

[0097] (Plated layer 31)

[0098] The plating layer 31 preferably contains, for example, plating of a metal or an alloy containing the metal selected from the group including Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, and Ag-Pd alloy. The plating layer 31 is preferably formed of a plurality of layers, and in an embodiment, the plating layer 31 contains a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. In an embodiment, the first plating layer 31a is a Ni plating, and the second plating layer 31b is a Sn plating. The Ni plating layer 31 can prevent the base electrode layer 30 from being corroded by solder when the ceramic electronic component is mounted. The Sn plating layer 31 can improve wettability of solder when the ceramic electronic component is mounted, and can facilitate the mounting.

[0099] Further, the external electrode 3 can also be provided with the plating layer 31 directly on the laminate 2 without containing the base electrode layer 30. In this case, the internal electrode layer 15 and the plating layer 31 are directly connected. Further, in this case, a catalyst can also be provided on the laminate 2 as a pretreatment.

[0100] In this case, the plating layer 31 preferably contains a first plating layer 31a and a second plating layer 31b provided on the first plating layer 31a. The first plating layer 31a and the second plating layer 31b preferably contain, for example, plating of a metal or an alloy containing the metal selected from the group including Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, and Zn.

[0101] Further, for example, in a case where Ni is used as the internal electrode layer 15, Cu having good adhesion to Ni is preferably used as the first plating layer 31a. Further, Sn or Au having good solder wettability is preferably used as the second plating layer 31b, and Ni having solder resist performance is preferably used as the first plating layer 31a. The second plating layer 31b is formed as needed, and the external electrode 3 can also be composed of the first plating layer 31a. The second plating layer 31b can be provided as the outermost layer of the plating layer 31, and other plating layers can also be provided on the second plating layer 31b. The plating layer 31 preferably does not contain glass. The proportion of metal per unit volume of the plating layer 31 is preferably 99% by volume or more.

[0102] (Method for manufacturing the laminate ceramic capacitor 1)

[0103] Figure 6 is a flowchart illustrating a method for manufacturing the laminate ceramic capacitor 1. Figure 7 is a diagram illustrating a method for manufacturing the laminate ceramic capacitor 1.

[0104] (Manufacturing process of the raw sheet S1)

[0105] First, a ceramic slurry for an internal dielectric layer is prepared, comprising ceramic powder, binder, solvent, and Si, wherein the ceramic powder contains Ba and Ti. The molar ratio of Si to Ti in the ceramic slurry for the internal dielectric layer is 0.8 mol% or more and 1.4 mol% or less. The ceramic slurry for the internal dielectric layer is formed into a sheet using a molding coater, gravure coater, or microgravure coater on a carrier film, thereby producing a ceramic green sheet 101 for an internal dielectric layer.

[0106] Next, a conductive paste containing Ni is printed onto the inner dielectric layer using a ceramic green sheet 101 via screen printing, inkjet printing, gravure printing, or the like, to create a strip-shaped pattern, thereby forming a conductive pattern 102. Thus, a raw material sheet 103 is fabricated on the surface of the ceramic green sheet 101, which becomes the inner dielectric layer 14, onto which the conductive pattern 102, which becomes the inner electrode layer 15, is printed.

[0107] In addition, similar to the ceramic slurry for the inner dielectric layer, an outer layer ceramic slurry comprising ceramic powder, binder, solvent, and Si is prepared, wherein the ceramic powder comprises Ba and Ti. This outer layer ceramic slurry is formed into a sheet using a die-casting machine, gravure coating machine, or microgravure coating machine on a carrier film, thereby producing an outer layer ceramic green sheet 112. The molar ratio of Si to Ti in the outer layer ceramic slurry is less than that in the inner dielectric layer ceramic slurry, being 0.8 mol% or less, preferably 0.5 mol% or less.

[0108] (Lamination process S2)

[0109] Next, multiple raw material sheets 103 are stacked. For example... Figure 7 As shown, multiple raw material sheets 103 are stacked such that the conductive strip patterns 102 face the same direction, and the conductive strip patterns 102 are staggered by half a spacing in the width direction W between adjacent raw material sheets 103. Furthermore, outer ceramic green sheets 112 are stacked on both sides of the stacked raw material sheets 103 to form the outer layer portion 22.

[0110] Next, the outer layer is hot-pressed together with a ceramic green sheet 112 and a plurality of stacked raw material sheets 103 to create a master block 110.

[0111] (S3: Mother block cutting process)

[0112] Next, the mother block 110 is aligned with the dimensions of the laminated piece 10. Figure 7 Cutting line X and cutting lines (not shown) intersecting cutting line X are cut. This produces multiple laminated pieces 10.

[0113] (Side margin portion ceramic green sheet adhesion step S4)

[0114] The inner side layer ceramic slurry and the outer side layer ceramic slurry are prepared, the inner side layer ceramic slurry contains ceramic powder, a binder, a solvent, and a trace amount of Si, the ceramic powder contains Ba and Ti components, and the outer side layer ceramic slurry contains ceramic powder, a binder, a solvent, and more Si than the inner side layer ceramic slurry, the ceramic powder contains Ba and Ti components.

[0115] Specifically, the inner side layer ceramic slurry contains Si at a molar ratio of 0.01 to 0.1 mol% with respect to Ti, and the outer side layer ceramic slurry contains Si at a molar ratio of 0.8 mol% or less, more preferably 0.5 mol% or less, with respect to Ti.

[0116] The outer side layer ceramic slurry is applied to the surface of the support film and dried, and the inner side layer ceramic slurry is applied thereto and dried, thereby producing a ceramic green sheet having a two-layer structure.

[0117] Then, the ceramic green sheet is peeled from the support film, the inner side layer ceramic green sheet of the ceramic green sheet and the side surface of the laminated small piece 10 are opposed to each other, and pressing and punching are performed, thereby adhering the side margin portion ceramic green sheet to the side surface of the laminated small piece 10.

[0118] (Burn-on layer material application step S5)

[0119] The material of the burn-on layer 30a in the base electrode layer 30 is attached to both end surfaces C of the laminated small piece 10 after the side margin portion ceramic green sheet is adhered thereto.

[0120] (Firing step S6)

[0121] Then, the laminated small piece 10 to which the material of the burn-on layer 30a is attached is subjected to a debinding treatment in a nitrogen atmosphere under given conditions, and then fired and sintered in a nitrogen-hydrogen-water vapor mixed atmosphere at a given temperature, thereby becoming the laminated body 2 in which the burn-on layer 30a and the conductive resin layer 30b are formed.

[0122] In this firing step, the particles g of the dielectric are formed in the outer dielectric layer 20 in which the outer layer portion 22 and the side margin portion 21 are combined, and the inner dielectric layer 14. The particle size of the particles g can be adjusted by the Si content. If the Si content is large, the particle size of the particles g becomes small, and if the Si content is small, the particle size of the particles g becomes large. For example, if the laminated body 2 is fired, the particle size of the particles g of the laminated body 2 has a tendency to become smaller toward the outer surface of the laminated body 2. By adjusting the Si content of the laminated body 2, the excessive change in the particle size of the particles g of the laminated body 2 can be suppressed.

[0123] In the embodiment, the inner dielectric layer 14 and the outer dielectric layer 20 contain Si and Ti. The molar ratio of Si to Ti of the inner dielectric layer 14 is more than the molar ratio of Si to Ti of the outer dielectric layer 20. Specifically, the molar ratio of Si to Ti in the inner dielectric layer 14 is 0.8 mol% or more and 1.4 mol% or less. The molar ratio of Si to Ti of the outer dielectric layer 20 is 0.8 mol% or less.

[0124] Therefore, it can also be considered that the particle diameter of the particles 21g and the particles 22b of the outer dielectric layer 20, which has a smaller Si content than the inner dielectric layer 14, is larger than that of the particles 14g of the inner dielectric layer 14. However, if fired, even if the Si content is the same, the particles 21g and the particles 22b of the outer dielectric layer 20 located on the outer side have a tendency to become smaller than the case where located on the inner side. Further, the outer dielectric layer 20 contains Ni, and the growth of the particles of the outer dielectric layer 20 can also be suppressed by the Ni.

[0125] Therefore, according to the embodiment, after sintering, the particle diameter of the inner dielectric layer 14 and the particle diameter of the outer dielectric layer 20 become substantially equal, that is, the difference in the particle diameter becomes 100 nm or less.

[0126] In addition, the inner side layer 21b is considerably thinner than the outer side layer 21a, and therefore the Si content of the inner side layer 21b has a small contribution ratio to the determination of the particle diameter of the particles 21g. Therefore, the Si content in the outer side layer 21a is dominant in the formation of the particle diameter before sintering.

[0127] (Electrically conductive resin layer step S7)

[0128] Next, a material containing electrically conductive particles and a thermosetting resin is attached to the adhesion layer 30a.

[0129] (Thin film layer forming step S8)

[0130] Further, a thin film layer 30c as a layer of 1 μm or less in which metal particles are deposited is formed on the material of the electrically conductive resin layer 30b in the laminate 2 by a thin film forming method such as a sputtering method or an evaporation method.

[0131] (Plating layer forming step S9)

[0132] In the embodiment, as the plating layer 31, a first plating layer 31a as a Ni plating layer is formed, and a second plating layer 31b as a Sn plating layer is formed on the first plating layer 31a. Through the above steps, the laminate ceramic capacitor 1 can be manufactured.

[0133] (EFFECTS)

[0134] The laminated ceramic capacitor 1 of the embodiment has the following effects. On the side surface B side of the inner layer portion 11, there is an interface where the side margin portion 21 of the inner dielectric layer 14 and the outer dielectric layer 20 are in contact. On the end surface C side of the inner electrode layer 15 disposed on the two main surfaces A side of the inner layer portion 11, where the lead-out portion 15b does not extend, there is an interface where the outer layer portion 22 of the inner dielectric layer 14 and the outer dielectric layer 20 are in contact. At such an interface where the inner dielectric layer 14 and the outer dielectric layer 20 are in contact, if the particle size difference of the particles g contained in the dielectric layer is large, the difference in compressive stress becomes large, the interface easily peels, and the insulation breakdown voltage can become low.

[0135] However, in the embodiment, the average particle size of the particles 14g contained in the inner dielectric layer 14 and the average particle sizes of the particles 21g and the particles 22g contained in the outer dielectric layer 20 are substantially equal, and the difference in particle size is 100 nm or less.

[0136] Therefore, the difference in compressive stress at the interface of the inner dielectric layer 14 and the outer dielectric layer 20 is not easily generated, the decrease in insulation breakdown voltage can be prevented, the voltage resistance reliability can be improved, and the static capacitance can be improved.

[0137] Further, with respect to the both end portions in the width direction W, because the electric field also enters into the side margin portion 21, if the particle size in the side margin portion 21 is large, it becomes a weak point. If the particle size difference is small, it can be improved.

[0138] (Experimental Example)

[0139] By adjusting the Si content contained in each of the inner electrode layer 15 and the outer dielectric layer 20, a laminated ceramic capacitor 1 in which the particle size of the particles g contained in each of the inner electrode layer 15 and the outer dielectric layer 20 is different was manufactured. Then, a voltage was applied at a voltage increase rate of 50 V / sec between the external electrodes 3 of each of the laminated ceramic capacitors 1, and the voltage at the time of insulation breakdown was measured. Figure 8 is a table showing the values of the insulation breakdown voltage thereof.

[0140] As shown in the table, the particle size difference of each of Examples 1 to 8 is 100 nm or less. At this time, the insulation breakdown voltage (BVD) is 40 V or more.

[0141] In contrast, in the comparative example, the particle size difference is 137 nm. At this time, the insulation breakdown voltage (BVD) becomes a value as low as 27 V.

[0142] According to the above, the multilayer ceramic capacitor 1 of the embodiment to which the present application relates, in which the internal electrode layer 15 and the external dielectric layer 20 each contain particles g having a particle size difference of 100 nm or less, can improve the insulation breakdown voltage compared to a comparative example in which the particle g has a particle size difference of more than 100 nm, and can provide a multilayer ceramic capacitor 1 having high voltage resistance reliability.

[0143] The above describes the embodiment of the present application, but is not limited to the embodiment, and various modifications can be made within the scope of the gist thereof.

Claims

1. A multilayer ceramic capacitor comprising: a multilayer body including an inner layer portion in which a plurality of internal electrode layers and internal dielectric layers are stacked and both ends in a stacking direction are internal electrode layers, two outer layer portions disposed on both sides of the inner layer portion in the stacking direction, and a side margin portion disposed on both sides of the inner layer portion and the two outer layer portions in a width direction intersecting the stacking direction; and two external electrodes disposed on end surfaces of the multilayer body as surfaces on both sides in a length direction intersecting the stacking direction, wherein a position in the stacking direction of an end portion of the internal electrode layer in the width direction is shifted by 0.5 μm or less, the internal dielectric layer, the two outer layer portions, and the side margin portion contain particles, a difference between an average particle diameter of the particles contained in the internal dielectric layer and an average particle diameter of the particles contained in the two outer layer portions is 100 nm or less, a difference between the average particle diameter of the particles contained in the internal dielectric layer and an average particle diameter of the particles contained in the side margin portion is 100 nm or less, a difference between an average particle diameter of the particles contained in the two outer layer portions and an average particle diameter of the particles contained in the side margin portion is 100 nm or less, the internal dielectric layer and the side margin portion contain Si and Ti, and a molar ratio of Si to Ti in the internal dielectric layer is higher than a molar ratio of Si to Ti in the side margin portion.

2. The multilayer ceramic capacitor according to claim 1, wherein an average particle diameter of the particles contained in the internal dielectric layer and an average particle diameter of the particles contained in the side margin portion are 140 nm or more and 270 nm or less.

3. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein a molar ratio of Si to Ti in the internal dielectric layer is 0.8 mol% or more and 1.4 mol% or less.

4. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein a molar ratio of Si to Ti in the side margin portion is 0.8 mol% or less.

5. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the outer layer portion contains Si and Ti, and a molar ratio of Si to Ti in the outer layer portion is 0.5 mol% or less.

6. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein a molar ratio of Si to Ti in the side margin portion is 0.5 mol% or less.

7. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein the side margin portion is provided with a plurality of layers in the width direction, and a molar ratio of Si to Ti in an outermost side margin portion is more than a molar ratio of Si to Ti in an innermost side margin portion.

8. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein a thickness of the internal dielectric layer is 0.4 μm or more and 0.5 μm or less.

9. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The thickness of the internal dielectric layer is 0.4 μm or more and 0.45 μm or less.

10. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The thickness of the internal electrode layer is 0.3 μm or more and 0.4 μm or less.

11. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The thickness of the internal electrode layer is 0.3 μm or more and 0.35 μm or less.

12. The multilayer ceramic capacitor according to claim 1 or claim 2, wherein, The side margin portion contains Ni.

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