Semiconductor devices and their manufacturing methods

Abstract

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate. The method includes: forming a plurality of first trenches extending along a first direction in the substrate; forming a plurality of second trenches extending along a second direction on the substrate where the first trenches are formed; the first direction is perpendicular to the second direction; the first depth of the first trench is equal to the second depth of the second trench; forming a first insulating layer, a conductive layer, and a second insulating layer sequentially in the first trenches and the second trenches; separating the conductive layer in the first trench in a cross section along the second direction to form two bit lines connected to the sidewalls on both sides of the first trench and extending along the first direction; and forming word lines extending along the second direction in the first trenches and the second trenches and on the conductive layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a semiconductor device and a method for manufacturing the same. Background Technology

[0002] With the advancement of chip and memory technologies, the integration requirements in semiconductor manufacturing processes are becoming increasingly stringent. To improve the utilization rate of semiconductor substrates and increase integration density, vertical channel (VCD) semiconductor devices are gradually being adopted. In a VCD, the transistor channels are perpendicular to the substrate surface, allowing for easy array arrangement. However, for VCD semiconductor devices, the routing layout and manufacturing processes still require further optimization and improvement. Summary of the Invention

[0003] In view of this, embodiments of this application provide a semiconductor device and a method for manufacturing the same.

[0004] In a first aspect, embodiments of this application provide a method for manufacturing a semiconductor device, the semiconductor device including a substrate, the method comprising:

[0005] Multiple first trenches extending along a first direction are formed on the substrate;

[0006] A plurality of second trenches extending along a second direction are formed on the substrate in which the first trench is formed; the first direction is perpendicular to the second direction; the first depth of the first trench is equal to the second depth of the second trench;

[0007] A first insulating layer, a conductive layer, and a second insulating layer are sequentially formed in the first trench and the second trench;

[0008] The conductive layer in the first trench is separated in the cross section in the second direction to form two bit lines that are connected to the sidewalls on both sides of the first trench and extend along the first direction.

[0009] Word lines extending in the second direction are formed on the conductive layer within the first and second trenches.

[0010] In some embodiments, separating the conductive layer in the first trench in a cross-section in the second direction includes:

[0011] Along the first direction, a first gap having a third depth is formed on the first insulating layer, the conductive layer, and the second insulating layer within the first trench; the third depth is less than the total thickness of the first insulating layer, the conductive layer, and the second insulating layer, and the third depth is greater than the sum of the thicknesses of the first insulating layer and the conductive layer;

[0012] A first insulating material is filled into the first gap to form a first insulating layer; wherein the conductive layer in the first trench is separated by the first insulating layer in the cross section in the second direction.

[0013] In some embodiments, the first insulating material comprises an oxide.

[0014] In some embodiments, after the first insulating layer, the conductive layer, and the second insulating layer are sequentially formed in the first trench and the second trench, the method further includes:

[0015] The second insulating layer and the substrate surface are planarized to expose the substrate surface outside the first trench and the second trench.

[0016] In some embodiments, forming word lines extending in the second direction within the first and second trenches and on the conductive layer includes:

[0017] Remove the portion of the second insulating layer above the conductive layer in the first and second trenches to form a recessed area;

[0018] The letter lines are formed within the recessed area.

[0019] In some embodiments, forming the letter line within the recessed area includes:

[0020] A gate oxide layer is formed on the sidewall of the recessed region;

[0021] A gate conductive layer is formed between the gate oxide layers in the recessed region;

[0022] The gate conductive layer in the recessed region is separated into two word lines extending along the second direction in a cross section in the first direction.

[0023] In some embodiments, forming a gate conductive layer between the gate oxide layers in the recessed region includes:

[0024] A conductive material is deposited between the gate oxide layers in the recessed region to form a gate conductive layer; the thickness of the gate conductive layer is less than or equal to the height of the gate oxide layer.

[0025] In some embodiments, separating the gate conductive layer in the recessed region into two word lines extending along the second direction in a cross-section in the first direction includes:

[0026] Along the second direction, a second gap having a fourth depth is formed on the gate conductive layer; the fourth depth is greater than or equal to the thickness of the gate conductive layer; the second gap separates the gate conductive layer in a cross section in the first direction;

[0027] A second insulating material is filled into the second gap to form a second isolation layer; wherein the gate conductive layers connected by the conductive materials on both sides of the second isolation layer constitute the word line.

[0028] In some embodiments, the second insulating material comprises a nitride.

[0029] In some embodiments, the thickness of the gate conductive layer is less than the height of the gate oxide layer, and after separating the gate conductive layer in the recessed region in a cross section in the first direction, the method further includes:

[0030] A third insulating material is filled between the gate oxide layers in the recessed region to form a third isolation layer; wherein the bottom of the third isolation layer is connected to the top of the second isolation layer and the gate conductive layer.

[0031] On the other hand, embodiments of this application provide a semiconductor device, including:

[0032] Substrate;

[0033] The substrate has a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; wherein the first direction is perpendicular to the second direction; and the first depth of the first trench is equal to the second depth of the second trench.

[0034] The first insulating layer is located at the bottom of the first trench and the second trench;

[0035] A conductive layer located on the first insulating layer; the conductive layer is separated in a cross section in the second direction, and the separated conductive layer forms two bit lines that are respectively connected to the sidewalls on both sides of the first trench and extend along the first direction;

[0036] The first and second trenches, and the conductive layer therein, have word lines extending along the second direction.

[0037] In some embodiments, the semiconductor device further includes:

[0038] A first isolation layer is located on the first insulating layer within the first trench; wherein the conductive layer in the first trench is separated by the first isolation layer in a cross section in the second direction.

[0039] In some embodiments, the semiconductor device further includes:

[0040] A second insulating layer is located between the conductive layer and the word line; wherein the second insulating layer in the first trench is separated from the first insulating layer in the cross section of the second direction.

[0041] In some embodiments, the semiconductor device further includes:

[0042] A gate oxide layer is located on a portion of the sidewalls of the first trench and the second trench on the second insulating layer;

[0043] The word line includes: a gate conductive layer corresponding to each semiconductor pillar located between adjacent gate oxide layers; the gate conductive layers are connected in the second direction.

[0044] In some embodiments, the semiconductor device further includes:

[0045] A second isolation layer is located on the second insulating layer within the second trench; wherein the gate conductive layer in the second trench is separated by the second isolation layer in the cross section of the first direction.

[0046] The technical solution provided in this application involves forming trenches on a substrate during the manufacturing process of a semiconductor device. A first insulating layer, a conductive layer, and a second insulating layer are formed within these trenches. The conductive layer in the first trench is then separated in a cross-section along a second direction, forming a bit line structure buried within the substrate. This approach offers several advantages. First, compared to bit lines formed by doping the semiconductor substrate, the bit lines formed by depositing conductive material in this application exhibit higher conductivity, thereby improving the overall performance of the semiconductor device. Second, the parallel and separated dual bit line structure formed on the sidewalls of the first trench enhances the integration density of the semiconductor device and reduces parasitic capacitance between the bit lines. Attached Figure Description

[0047] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor device as provided in this application embodiment;

[0048] Figures 2A to 2E Top view and cross-sectional views of the first groove formed in the manufacturing method provided in the embodiments of this application;

[0049] Figures 3A to 3B A top view and a cross-sectional view of a portion thereof, showing the formation of the second trench in the manufacturing method provided in the embodiments of this application;

[0050] Figures 4A to 4C A top view and a cross-sectional view of a portion thereof, showing the manufacturing method provided in this application for forming a first insulating layer, a conductive layer, and a second insulating layer.

[0051] Figures 5A to 5CA top view and a cross-sectional view of a portion thereof, showing the formation of the first gap in the manufacturing method provided in the embodiments of this application;

[0052] Figures 6A to 6C A top view and a cross-sectional view of a portion thereof, showing the formation of the first isolation layer in the manufacturing method provided in the embodiments of this application;

[0053] Figures 7A to 7D Cross-sectional views of the recessed region formed in the manufacturing method provided in the embodiments of this application;

[0054] Figures 8A to 8D A cross-sectional view of a portion of the cross-section in the manufacturing method provided in the embodiments of this application, in which the gate oxide layer and the gate conductive layer are formed;

[0055] Figures 9A to 9B A cross-sectional view of the second isolation layer and a portion thereof formed in the manufacturing method provided in the embodiments of this application;

[0056] Figures 10A to 10G This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application. Detailed Implementation

[0057] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0058] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0059] like Figure 1 As shown in the embodiments of this application, a method for manufacturing a semiconductor device is provided. The semiconductor device includes a substrate, and the method includes:

[0060] Step S101: Form a plurality of first trenches extending along a first direction on the substrate;

[0061] Step S102: Form a plurality of second trenches extending along a second direction on the substrate on which the first trench is formed; the first direction is perpendicular to the second direction; the first depth of the first trench is equal to the second depth of the second trench;

[0062] Step S103: A first insulating layer, a conductive layer, and a second insulating layer are sequentially formed in the first trench and the second trench;

[0063] Step S104: Separate the conductive layer in the first trench on the cross section in the second direction to form two bit lines that are connected to the sidewalls on both sides of the first trench and extend along the first direction.

[0064] Step S105: In the first trench and the second trench, on the conductive layer, word lines extending along the second direction are formed.

[0065] In this embodiment, patterned trenches can be formed on the substrate surface by etching. Here, the first direction is a direction extending parallel to the substrate surface, and multiple first trenches can be formed in this direction, with these first trenches being parallel to each other. Exemplarily, the multiple first trenches are parallel to each other and can have equal spacing, depth, and width. Therefore, these first trenches can be formed simultaneously by etching. Of course, the above etching can be a single etching or multiple etching processes.

[0066] like Figure 2A The image shown is a top view after the first trench has been formed. Figure 2B , Figure 2C , Figure 2D as well as Figure 2E They are respectively Figure 2A The cross-sectional views are shown on sections aa', bb', cc', and dd'. Multiple parallel first trenches 110 are formed on the substrate 100.

[0067] After forming the first trench, a second trench, perpendicular to the first trench, can be formed using etching. The second trench extends parallel to the substrate surface but perpendicular to the first direction. This creates a mesh-like structure on the substrate surface, consisting of multiple intersecting first and second trenches. The unetched areas form semiconductor pillars perpendicular to the substrate surface. These pillars can be used as vertical channels for transistors, thus forming a transistor array.

[0068] like Figure 3A The image shown is a top view after the second groove 120 has been formed. Figure 3B for Figure 3A The cross-sectional view on the cc' section shows that multiple semiconductor pillars 130 are formed in the region outside the first and second trenches.

[0069] In this embodiment of the application, after the first trench and the second trench are formed, as follows: Figure 4AThe image shown is a top view of a first insulating layer 220, a conductive layer 230, and a second insulating layer 240 sequentially formed in the first trench 110 and the second trench 120. Figure 4B and Figure 4C They are respectively Figure 4A Cross-sectional views of sections bb' and cc'.

[0070] Here, the first insulating layer is a layer covering the bottom of the first and second trenches, and is composed of an insulating material, such as an oxide, nitride, or other insulating material. The conductive layer is a layer deposited on the first insulating layer, and is composed of a conductive material, such as metallic materials like copper, metallurgical materials, doped semiconductor materials, or other conductive materials. The second insulating layer is a layer filling the conductive layer, and is composed of an insulating material, such as an oxide, nitride, or other insulating material. Here, the insulating material constituting the first insulating layer can be the same as or different from the insulating material constituting the second insulating layer. The sum of the thicknesses of the first insulating layer, the conductive layer, and the second insulating layer is equal to the height of the semiconductor pillar, that is, it completely fills the first and second trenches.

[0071] The conductive layer within the first trench is continuous and extends in a first direction. In a cross-section in a second direction, the conductive layer connects to the sidewalls on both sides of the first trench. An isolation structure can be formed in the middle of the conductive layer to separate the conductive layer in the second direction cross-section; for example, a slit can be formed and filled with insulating material. Thus, the conductive layer within the first trench extends along the sidewalls on both sides of the first trench, forming two bit lines. These two bit lines are parallel to each other and separated in the cross-section in the second direction. Each first trench has two bit lines on its first insulating layer, thus forming a dual bit line structure for the semiconductor device.

[0072] Since the isolation structure in the first trench does not extend into the second trench, word lines can be formed on the conductive layer of the first trench and within the second trench. In fact, the word lines extend along the second trench, i.e., along the second direction. However, because a portion of the material constituting the word lines may be located within the first trench, it is necessary to form them within both the first and second trenches. Of course, adjacent word lines can be isolated using an insulating material.

[0073] Thus, for vertical channel semiconductor devices, this application embodiment provides a method of forming buried word lines and bit lines within a substrate, and each transistor channel has a dual bit line structure, i.e., both sides have conductive layers formed by depositing conductive materials. In this way, on the one hand, compared to bit lines formed by doping the semiconductor substrate, the bit lines formed by depositing conductive materials used in this application embodiment have higher conductivity, thereby improving the overall performance of the semiconductor device. On the other hand, the dual bit line structure, which is parallel to each other and separated in the second direction, formed within the first gaps on both sides of the first trench, can improve the integration density of the semiconductor device and reduce parasitic capacitance between bit lines.

[0074] In some embodiments, separating the conductive layer in the first trench in a cross-section in the second direction includes:

[0075] Along the first direction, a first gap with a third depth is formed on the first insulating layer, the conductive layer and the second insulating layer within the first trench; the third depth is less than the total thickness of the first insulating layer, the conductive layer and the second insulating layer, and the third depth is greater than the sum of the thicknesses of the first insulating layer and the conductive layer.

[0076] A first insulating material is filled into the first gap to form a first insulating layer; wherein the conductive layer in the first trench is separated by the first insulating layer in the cross section in the second direction.

[0077] like Figure 5A The image shown is a top view of the formation of the first gap 330. Figure 5B and Figure 5C They are respectively Figure 5A Cross-sectional views of sections bb' and cc'; Figure 6A To form a top view of the first isolation layer 340, Figure 6B and Figure 6C They are respectively Figure 6A Cross-sectional views of sections bb' and cc'.

[0078] In this embodiment, the first gap can be formed on the first insulating layer, conductive layer, and second insulating layer within the first trench by etching. Here, the depth of the first gap is greater than the sum of the thicknesses of the first insulating layer and the conductive layer, allowing the conductive layer to be separated by the first gap in a cross-section in the second direction. Exemplarily, the first gaps within each first trench can have equal spacing, depth, and width. Therefore, these first gaps can also be formed simultaneously by etching.

[0079] After the first gap is formed, a first insulating material can be filled into the first gap by epitaxial growth or deposition, for example, by chemical vapor deposition (CVD), atomic layer deposition (ALD), or physical vapor deposition (PVD). Here, the first insulating material can be an oxide, nitride, or other insulating material. The first insulating material can fill the entire inner wall of the first gap, including the bottom and sidewalls. Thus, the conductive layer within the first trench is separated from the first insulating material, i.e., the first insulating layer, in the cross-section in the second direction.

[0080] The process of forming the first isolation layer in this embodiment can be carried out simultaneously, which can reduce process steps and improve manufacturing efficiency.

[0081] In some embodiments, the first insulating material comprises an oxide.

[0082] Since oxides can have good insulating properties and are inexpensive, they can be used as the first insulating material in the embodiments of this application. Exemplarily, the first insulating material may include silicon oxide, nitrogen oxide, or other oxides, etc.

[0083] In some embodiments, after the first insulating layer, the conductive layer, and the second insulating layer are sequentially formed in the first trench and the second trench, the method further includes:

[0084] The second insulating layer and the substrate surface are planarized to expose the substrate surface outside the first trench and the second trench.

[0085] In this embodiment, after filling the first and second trenches with insulating material to form a second insulating layer, some excess insulating material may cover the semiconductor pillars, thereby affecting the performance of the semiconductor device. Therefore, planarization can be achieved by chemical mechanical polishing (CMP).

[0086] In some embodiments, forming word lines extending in the second direction within the first and second trenches and on the conductive layer includes:

[0087] Remove the portion of the second insulating layer above the conductive layer in the first and second trenches to form a recessed area;

[0088] The letter lines are formed within the recessed area.

[0089] In this embodiment of the application, a portion of the second insulating layer can be removed by etching to form a patterned recessed area. For example... Figures 7A to 7D As shown, they are respectively Figure 6A Schematic diagrams showing the formation of the concave region after sections aa', bb', cc', and dd' are formed.

[0090] The recessed region has a mesh-like structure formed by the first and second grooves, and its depth is less than the thickness of the second insulating layer. Therefore, the bottom of the recessed region exposes part of the second insulating layer, and the sidewalls expose part of the sidewalls of the semiconductor pillars. Here, the recessed region is separated from the bit lines by the second insulating layer. Word lines can be formed within the recessed region by deposition; therefore, the bit lines and word lines can also be separated by the second insulating layer.

[0091] In this embodiment, bit lines buried in the substrate are formed first, followed by word lines, which can reduce the size of semiconductor devices and improve integration.

[0092] In some embodiments, forming the letter line within the recessed area includes:

[0093] A gate oxide layer is formed on the sidewall of the recessed region;

[0094] A gate conductive layer is formed between the gate oxide layers in the recessed region;

[0095] The gate conductive layer in the recessed region is separated into two word lines extending along the second direction in a cross section in the first direction.

[0096] like Figures 8A to 8D As shown, where, Figure 8A and Figure 8B They are respectively in Figure 7B and Figure 7C A schematic diagram of the formation of the gate oxide layer 440 based on the above. Figure 8C and Figure 8D They are respectively in Figure 8A and 8B A schematic diagram of the conductive layer 450 formed on the basis.

[0097] In this embodiment, the sidewalls of some semiconductor pillars are exposed within the recessed region. It should be noted that each sidewall within the recessed region is in contact with its corresponding semiconductor pillar; therefore, the sidewall of the semiconductor pillar is also the sidewall of the recessed region. The sidewalls of the semiconductor pillars can be oxidized to form a gate oxide layer on the sidewalls within the recessed region. This gate oxide layer is part of the gate and is used for electrical isolation from the semiconductor pillars, i.e., the conductive channel. Exemplarily, the height of the gate oxide layer is the same as the depth of the recessed region, and its thickness is less than the width of the recessed region. Therefore, the gate oxide layers of each semiconductor pillar within the recessed region are separated from each other, and the bottom of the remaining recessed region still exposes a portion of the second insulating layer.

[0098] A conductive material can be deposited in the remaining recessed area to form a gate conductive layer. This gate conductive layer is located between the gate oxide layers and connects the semiconductor pillars in the recessed area. Here, the gate conductive layer surrounding each semiconductor and the aforementioned gate oxide layer constitute the corresponding gate of each semiconductor. The method for depositing the conductive material can be CVD, ALD, or PVD, etc.

[0099] In this embodiment, the gate conductive layer is continuous within the recessed region, and a two-bit line structure extending in the first direction has been formed in the first trench. Therefore, a word line structure extending in the second direction can be formed in the second trench. Accordingly, the gate conductive layer connects the gate oxide layers on both sides of the recessed region in the second trench on the cross-section in the first direction. An isolation structure can be formed in the middle of the gate conductive layer to separate the gate conductive layer on the cross-section in the first direction, for example, by forming a slit and filling it with insulating material. In this way, the gate conductive layer separated in the second trench and the corresponding gate conductive layer in the first trench form a word line extending in the second direction, and connect multiple semiconductor pillars in the second direction and the corresponding gate oxide layers.

[0100] In some embodiments, forming a gate conductive layer between the gate oxide layers in the recessed region includes:

[0101] A conductive material is deposited between the gate oxide layers in the recessed region to form a gate conductive layer; the thickness of the gate conductive layer is less than or equal to the height of the gate oxide layer.

[0102] In this embodiment, the deposited conductive material can be a metallic material, a doped semiconductor material, or other conductive material. It should be noted that the depth of the recessed region is equal to the height of the exposed portion of the semiconductor pillar, and the height of the gate oxide layer is equal to the depth of the recessed region. Therefore, when the thickness of the gate conductive layer is less than the height of the gate oxide layer, the bottom of the remaining portion of the recessed region contacts the gate conductive layer, and the sidewalls contact a portion of the gate oxide layer; when the thickness of the gate conductive layer is equal to the height of the gate oxide layer, the recessed region is completely filled.

[0103] In some embodiments, separating the gate conductive layer in the recessed region into two word lines extending along the second direction in a cross-section in the first direction includes:

[0104] Along the second direction, a second gap having a fourth depth is formed on the gate conductive layer; the fourth depth is greater than or equal to the thickness of the gate conductive layer; the second gap separates the gate conductive layer in a cross section in the first direction;

[0105] A second insulating material is filled into the second gap to form a second isolation layer; wherein the gate conductive layers connected by the conductive materials on both sides of the second isolation layer constitute the word line.

[0106] In this embodiment, the second gap can be formed on the gate conductive layer within the second groove by etching. For example... Figure 9A As shown, in Figure 8D A schematic diagram showing the formation of the second gap 550 based on this; Figure 9B In order to be in Figure 9A A schematic diagram of forming a second isolation layer 560 based on the above. Since the second gap is formed in the second trench, therefore, Figure 8C The cross-sectional view in the diagram remains unchanged.

[0107] Here, the depth of the second slit is greater than or equal to the thickness of the gate conductive layer, allowing the gate conductive layer to be separated by the second slit in the cross-section of the first direction. For example, the second slits within each second trench can have equal spacing, depth, and width. Therefore, these second slits can also be formed simultaneously by etching.

[0108] After the second gap is formed, a second insulating material can be filled into the second gap by deposition, such as by CVD, ALD, or PVD. Here, the second insulating material can be an oxide, nitride, or other insulating material. Thus, the conductive layer within the second trench is separated from the second insulating material, i.e., the aforementioned second insulating layer, in the cross-section of the first direction.

[0109] It should be noted that after the second isolation layer is formed, the second isolation layer is in contact with the first isolation layer in the area where each first trench and second trench intersects.

[0110] In some embodiments, the second insulating material comprises a nitride.

[0111] Because nitrides possess good insulating properties and are inexpensive, they can be used as the second insulating material in the embodiments of this application. Exemplarily, the second insulating material may include silicon nitride, titanium nitride, or other nitrides, etc.

[0112] In some embodiments, the thickness of the gate conductive layer is less than the height of the gate oxide layer, and after separating the gate conductive layer in the recessed region in a cross section in the first direction, the method further includes:

[0113] A third insulating material is filled between the gate oxide layers in the recessed region to form a third isolation layer; wherein the bottom of the third isolation layer is connected to the top of the second isolation layer and the gate conductive layer.

[0114] In this embodiment, when the thickness of the gate conductive layer is less than the height of the gate oxide layer, the bottom of the remaining portion of the recessed region contacts the gate conductive layer, and the sidewalls contact a portion of the gate oxide layer. A third insulating material can be deposited between the gate oxide layers. This third insulating material can be an oxide, nitride, or other insulating material. Exemplarily, the third insulating material can be the same as or different from the second insulating material, and the deposition process can be carried out simultaneously to form a third isolation layer.

[0115] This application also provides a semiconductor device, such as... Figure 10A The image shown is a top view of semiconductor device 1100. Figure 10B and Figure 10C They are respectively Figure 10A Cross-sectional views of sections bb' and cc'. The semiconductor device 1100 includes:

[0116] Substrate 1000;

[0117] The substrate 1000 has a plurality of first trenches 1010 extending along a first direction D1 and a plurality of second trenches 1020 extending along a second direction D2; wherein the first direction D1 is perpendicular to the second direction D2; and the first depth of the first trenches 1010 is equal to the second depth of the second trenches 1020.

[0118] A first insulating layer 1030 is located at the bottom of the first trench 1010 and the second trench 1020;

[0119] A conductive layer 1040 is located on the first insulating layer 1030; the conductive layer 1040 is separated in the cross section of the second direction D2, and the separated conductive layer 1040 forms two bit lines 1200 that are respectively connected to the sidewalls on both sides of the first trench 1010 and extend along the first direction D1.

[0120] Within the first trench 1010 and the second trench 1020, word lines 1300 extending along the second direction D2 are present on the conductive layer 1040.

[0121] In this embodiment, the first direction is a direction extending parallel to the substrate surface. Multiple parallel first trenches extend along this first direction, each first trench being a strip-shaped structure. Exemplarily, the multiple first trenches are parallel to each other and may have equal spacing, depth, and width.

[0122] Accordingly, multiple parallel second trenches extend in a second direction perpendicular to the first direction. Each second trench is a strip-shaped structure extending in the second direction. Exemplarily, the multiple second trenches are parallel to each other and may have equal spacing, depth, and width. Here, the second trenches have the same depth as the first trenches described above. Thus, the second trenches and the first trenches form a mesh structure on the substrate surface.

[0123] The first insulating layer, composed of an insulating material such as an oxide, nitride, or other insulating material, serves to electrically isolate the conductive layer from the substrate. The conductive layer is composed of a conductive material such as metallic copper, metallic ore, doped semiconductor material, or other conductive material. The conductive layer within the second trench directly connects to the sidewalls on both sides of the second trench and extends in the second direction. The conductive layer within the first trench is separated into two parallel bit lines in the cross-section in the second direction, respectively connecting to the sidewalls on both sides of the second trench and extending in the first direction. This constitutes the dual bit line structure of this embodiment.

[0124] In this embodiment, the word line is located above the two-bit line structure, and electrical isolation between the two can be achieved through insulating material. Accordingly, the word line extends in the second direction.

[0125] In some embodiments, such as Figure 10D As shown, Figure 10D for Figure 10A A cross-sectional view of section bb', the semiconductor device 1100 further includes:

[0126] A first isolation layer 1050 is located on the first insulating layer within the first trench; wherein the conductive layer in the first trench is separated by the first isolation layer 1050.

[0127] In this embodiment, the conductive layer in the first trench can be separated into two parallel bit lines in a cross-section in the second direction by a first insulating layer. The first insulating layer can be made of an oxide material and extends in the first direction.

[0128] In some embodiments, such as Figure 10E As shown, Figure 10E for Figure 10A A cross-sectional view of section bb', the semiconductor device 1100 further includes:

[0129] A second insulating layer 1060 is located between the conductive layer and the word line; wherein the second insulating layer 1060 in the first trench is separated by the first insulating layer 1050 in the cross section in the second direction.

[0130] In this embodiment, electrical isolation between the conductive layer and the word lines can be achieved through a second insulating layer, which can be composed of nitride, oxide, or other insulating materials. Since a dual bit line structure is formed in the first trench, the two bit lines are separated by the first insulating layer. Correspondingly, the second insulating layer in the first trench can also be separated by the aforementioned first insulating layer.

[0131] In some embodiments, such as Figure 10F As shown, Figure 10F for Figure 10A A cross-sectional view at section cc', the semiconductor device 1100 further includes:

[0132] A gate oxide layer 1070 is located on the first trench and a portion of the sidewalls of the second trench on the second insulating layer;

[0133] The word line includes: a gate conductive layer 1080 corresponding to each semiconductor pillar located between adjacent gate oxide layers 1070; the gate conductive layer is connected in the second direction.

[0134] In this embodiment, the gate includes a gate oxide layer and a gate conductive layer, and the gate is located on a second insulating layer. The gate oxide layer covers the sidewalls of the remaining portions of the first and second trenches; the gate conductive layers are located between the gate oxide layers. Here, the gate conductive layers within the second trench are interconnected and separated in a cross-section in a first direction, forming a word line extending along a second direction.

[0135] In some embodiments, such as Figure 10G As shown, Figure 10G for Figure 10A A cross-sectional view at section cc', the semiconductor device 1100 further includes:

[0136] The second isolation layer 1090 is located on the second insulating layer within the second trench; wherein the gate conductive layer in the second trench is separated by the second isolation layer 1090 in the cross section of the first direction.

[0137] In this embodiment, the gate conductive layer in the second trench can be separated into two parallel word lines in a cross-section along a first direction by a second isolation layer. This second isolation layer can be made of a nitride material and extends in a second direction. Here, the material constituting the second isolation layer can be the same as the material constituting the second insulating layer described above.

[0138] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0139] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, The semiconductor device includes a substrate, and the method includes: Multiple first trenches extending along a first direction are formed on the substrate; A plurality of second trenches extending along a second direction are formed on the substrate in which the first trench is formed; the first direction is perpendicular to the second direction; the first depth of the first trench is equal to the second depth of the second trench; A first insulating layer, a conductive layer, and a second insulating layer are sequentially formed in the first trench and the second trench; The conductive layer in the first trench is separated in the cross section in the second direction to form two bit lines that are connected to the sidewalls on both sides of the first trench and extend along the first direction. Word lines extending in the second direction are formed on the conductive layer within the first and second trenches.

2. The method according to claim 1, characterized in that, The step of separating the conductive layer in the first trench on a cross-section in the second direction includes: Along the first direction, a first gap having a third depth is formed on the first insulating layer, the conductive layer, and the second insulating layer within the first trench; the third depth is less than the total thickness of the first insulating layer, the conductive layer, and the second insulating layer, and the third depth is greater than the sum of the thicknesses of the first insulating layer and the conductive layer; A first insulating material is filled into the first gap to form a first insulating layer; wherein the conductive layer in the first trench is separated by the first insulating layer in the cross section in the second direction.

3. The method according to claim 2, characterized in that, The first insulating material includes oxides.

4. The method according to claim 1, characterized in that, After the first insulating layer, the conductive layer, and the second insulating layer are sequentially formed in the first trench and the second trench, the method further includes: The second insulating layer and the substrate surface are planarized to expose the substrate surface outside the first trench and the second trench.

5. The method according to claim 1, characterized in that, The formation of word lines extending in the second direction within the first and second trenches and on the conductive layer includes: Remove the portion of the second insulating layer above the conductive layer in the first and second trenches to form a recessed area; The letter lines are formed within the recessed area.

6. The method according to claim 5, characterized in that, The process of forming the letter line within the recessed area includes: A gate oxide layer is formed on the sidewall of the recessed region; A gate conductive layer is formed between the gate oxide layers in the recessed region; The gate conductive layer in the recessed region is separated into two word lines extending along the second direction in a cross section in the first direction.

7. The method according to claim 6, characterized in that, The formation of a gate conductive layer between the gate oxide layers in the recessed region includes: A conductive material is deposited between the gate oxide layers in the recessed region to form a gate conductive layer; the thickness of the gate conductive layer is less than or equal to the height of the gate oxide layer.

8. The method according to claim 7, characterized in that, The step of separating the gate conductive layer in the recessed region into two word lines extending along the second direction in a cross-section in the first direction includes: Along the second direction, a second gap having a fourth depth is formed on the gate conductive layer; the fourth depth is greater than or equal to the thickness of the gate conductive layer; the second gap separates the gate conductive layer in a cross section in the first direction; A second insulating material is filled into the second gap to form a second isolation layer; wherein the gate conductive layers connected by the conductive materials on both sides of the second isolation layer constitute the word line.

9. The method according to claim 8, characterized in that, The second insulating material includes nitrides.

10. The method according to claim 9, characterized in that, The thickness of the gate conductive layer is less than the height of the gate oxide layer. After separating the gate conductive layer in the recessed region in a cross-section in the first direction, the method further includes: A third insulating material is filled between the gate oxide layers in the recessed region to form a third isolation layer; wherein the bottom of the third isolation layer is connected to the top of the second isolation layer and the gate conductive layer.

11. A semiconductor device manufactured by the method according to any one of claims 1-10, characterized in that, include: Substrate; The substrate has a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction; wherein the first direction is perpendicular to the second direction; and the first depth of the first trench is equal to the second depth of the second trench. The first insulating layer is located at the bottom of the first trench and the second trench; A conductive layer located on the first insulating layer; the conductive layer is separated in a cross section in the second direction, and the separated conductive layer forms two bit lines that are respectively connected to the sidewalls on both sides of the first trench and extend along the first direction; The first and second trenches, and the conductive layer therein, have word lines extending along the second direction.

12. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: A first isolation layer is located on the first insulating layer within the first trench; wherein the conductive layer in the first trench is separated by the first isolation layer in a cross section in the second direction.

13. The semiconductor device according to claim 12, characterized in that, The semiconductor device further includes: A second insulating layer is located between the conductive layer and the word line; wherein the second insulating layer in the first trench is separated from the first insulating layer in the cross section of the second direction.

14. The semiconductor device according to claim 13, characterized in that, The semiconductor device further includes: A gate oxide layer is located on a portion of the sidewalls of the first trench and the second trench on the second insulating layer; The word line includes: a gate conductive layer corresponding to each semiconductor pillar located between adjacent gate oxide layers; the gate conductive layers are connected in the second direction.

15. The semiconductor device according to claim 14, characterized in that, The semiconductor device further includes: A second isolation layer is located on the second insulating layer within the second trench; wherein the gate conductive layer in the second trench is separated by the second isolation layer in the cross section of the first direction.

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