Vertical device based on aln substrate and method of manufacturing thereof

Abstract

The application discloses a vertical device based on an AlN substrate and a manufacturing method thereof. The vertical device comprises an epitaxial wafer and a first passivation layer, an N ohmic contact layer, a cathode electrode layer and a second passivation layer, a Schottky layer, a P ohmic contact layer and an anode electrode layer grown at two ends of the epitaxial wafer. The epitaxial wafer comprises a substrate layer, a buffer layer and an epitaxial layer, wherein the epitaxial layer comprises an AlGaN layer, a U-GaN layer and a P-GaN layer. The first passivation layer and the N ohmic contact layer penetrate through to the epitaxial layer on one side, and the cathode electrode layer covers the surface of the substrate layer, the first passivation layer and the N ohmic contact layer. The P ohmic contact layer is located on the surface of the P-GaN layer, the Schottky layer penetrates through to the buffer layer and partially covers the surface of the P ohmic contact layer, the second passivation layer covers part of the buffer layer, the Schottky layer, the P ohmic contact layer, the P-GaN layer and the U-GaN layer, and the anode electrode layer penetrates through to the Schottky layer and covers the surface of the second passivation layer. The vertical device provided by the application has good heat dissipation effect, simple packaging process, low possibility of virtual welding and good performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to vertical devices based on AlN substrates and their manufacturing methods. Background Technology

[0002] refer to Figure 1 This is a schematic diagram of a conventional SBD power device, where A is the anode electrode layer, C is the cathode electrode layer, N is the N-ohm contact layer, and P is the P-ohm contact layer. Most third-generation semiconductor epitaxial wafers typically grow an AlN layer on a substrate to grow higher-quality GaN epitaxial material. However, due to the non-conductive nature of AlN, chip design can only use electrodes on the same side, meaning the anode and cathode are located on the same side, significantly impacting the chip's electrical performance. Simultaneously, the resistance and thermal resistance formed by the substrate also greatly affect the overall device performance.

[0003] In addition, the length of the PSJ is directly affected by the fact that the anode and cathode of the chip are on the same side, which in turn affects the electrical performance of the two-dimensional electron gas of the device.

[0004] Third, most existing semiconductor devices are manufactured in a conventional form, and their packaging process requires separate wire bonding to connect the various electrodes on the chip and the package pins, which may lead to a certain possibility of poor soldering.

[0005] Fourth, conventional semiconductor chips have poor heat dissipation performance, often requiring special working environments or auxiliary heat dissipation measures, which greatly limits their application and increases their cost. Summary of the Invention

[0006] One advantage of this invention is that it provides a vertical device based on an AlN substrate and a method for manufacturing the same device. The vertical device is manufactured in a vertical packaging form. The original case of wire bonding on the same side of the electrode is changed to wire bonding on one side and surface mounting on the other side, which greatly reduces the possibility of poor soldering of the packaging wires, simplifies the packaging process, and reduces the cost of using packaging gold wires.

[0007] One advantage of this invention is that it provides a vertical device based on an AlN substrate and a method for manufacturing the same. The device is manufactured in a vertical packaging manner, which can greatly increase the effective length of the PSJ based on the size of the N-ohm contact layer, greatly increase the total amount of two-dimensional electron gas, and thus greatly improve the electrical performance of the device.

[0008] One advantage of this invention is that it provides a vertical device based on an AlN substrate and a method for manufacturing the same, in which heat dissipation can be achieved by connecting the anode electrode layer to the package holder or by connecting the cathode electrode layer to the package holder, resulting in better heat dissipation and more flexible and convenient packaging.

[0009] One advantage of this invention is that it provides a vertical device based on an AlN substrate and a method for manufacturing the same, wherein the cathode electrode layer is led out from one side of the substrate to the outer surface of the substrate. This not only solves the problem that conventional substrates are non-conductive and cannot be used to fabricate vertical structure chips, thus improving the electrical performance of the device, especially high-power devices, but also greatly reduces the influence of the substrate on the device in terms of resistance and thermal resistance, further improving the overall performance of the device.

[0010] To achieve at least one of the above advantages of the present invention, in a first aspect, the present invention provides a vertical device based on an AlN substrate, comprising an epitaxial wafer, wherein the epitaxial wafer comprises a substrate layer, a buffer layer and an epitaxial layer grown sequentially from a first end to a second end, wherein the epitaxial layer comprises an AlGaN layer, a U-GaN layer and a P-GaN layer grown sequentially from the buffer layer, the vertical device having a first passivation layer, an N-ohm contact layer and a cathode electrode layer disposed at the first end of the epitaxial wafer, and a second passivation layer, a Schottky layer, a P-ohm contact layer and an anode electrode layer disposed at the second end of the epitaxial wafer;

[0011] The first passivation layer and the N-ohm contact layer extend through the substrate layer and the buffer layer to the epitaxial layer on one side of the epitaxial wafer. The thickness of the N-ohm contact layer is less than the thickness of the first passivation layer. The cathode electrode layer covers the surface of the substrate layer, the first passivation layer and the N-ohm contact layer.

[0012] The P-GaN layer is located on the side of the epitaxial layer closest to the epitaxial layer. The P-ohm contact layer is located on the surface of the P-GaN layer away from the buffer layer. The Schottky base layer extends through the epitaxial layer to the buffer layer on the side where the P-GaN layer is located, and partially covers the surface of the P-ohm contact layer. The second passivation layer covers a portion of the buffer layer, the Schottky base layer, the P-ohm contact layer, the P-GaN layer, and the U-GaN layer. The anode electrode layer extends through the second passivation layer to the Schottky base layer on the surface of the second passivation layer away from the buffer layer, and at least partially covers the surface of the second passivation layer.

[0013] According to one embodiment of the present invention, the thickness of the cathode electrode layer covering the surface of the substrate layer is 2 μm to 10 μm.

[0014] According to one embodiment of the present invention, the thickness of the anode electrode layer covering the surface of the second passivation layer is 2 μm to 10 μm.

[0015] According to one embodiment of the present invention, the thickness of the first passivation layer in the lateral direction is 1µm to 3µm.

[0016] According to one embodiment of the present invention, the thickness of the second passivation layer covering the surface of the U-GaN layer is 1µm to 8µm.

[0017] According to one embodiment of the present invention, the anode electrode layer completely covers the surface of the second passivation layer away from the buffer layer, or partially covers the surface of the second passivation layer away from the buffer layer on both sides.

[0018] Secondly, the present invention also provides a method for manufacturing the aforementioned vertical device based on an AlN substrate, comprising, in sequence, a method for manufacturing the vertical device at a first end of an epitaxial wafer and a method for manufacturing the vertical device at a second end of the epitaxial wafer, wherein the method for manufacturing the vertical device at the first end of the epitaxial wafer includes the following steps:

[0019] S110, after grinding, the substrate layer is thinned to a predetermined thickness, and the pattern of the first passivation layer and the N-ohm contact layer is etched using a positive photoresist photolithography process. Then, the substrate layer is etched, and then the buffer layer exposed in the pattern of the first passivation layer and the N-ohm contact layer is etched using an ICP etching process. The photoresist is removed and the substrate is cleaned.

[0020] S120, fabricate the PV layer by photolithography using positive photoresist to create the pattern of the first passivation layer, then remove the portion of the PV layer outside the first passivation layer, and then remove the photoresist and clean.

[0021] S130, the pattern of the N-ohm contact layer is etched by photolithography using negative photoresist, then metal electrode evaporation is performed, then metal stripping is performed to fabricate the N-ohm contact layer, and finally RTA annealing is performed.

[0022] S140, fabricate the negative electrode layer;

[0023] The method for manufacturing the vertical device at the second end of the epitaxial wafer includes the following steps:

[0024] S210, the U-GaN layer and the AlGaN layer are patterned using a positive photolithography process, and then the U-GaN layer and the AlGaN layer are etched using an ICP etching process, followed by photoresist removal and cleaning.

[0025] S220, the pattern of the P-GaN layer is formed by photolithography using positive photoresist, and then the P-GaN layer is etched by ICP etching, followed by photoresist removal and cleaning.

[0026] S230, the pattern of the P-ohm contact layer is etched using a positive photolithography process, then the metal electrode of the P-ohm contact layer is evaporated using a PVD process, then the layer is peeled off, the photoresist is removed and cleaned, and then an RTA annealing process is performed.

[0027] S240, the pattern of the Schottky substrate area is etched using a positive photolithography process, and then the metal electrode of the Schottky substrate is evaporated using a PVD process;

[0028] S250, deposit, evaporate, or photolithography to create the second passivation layer;

[0029] S260, the pattern of the anode electrode layer is formed by photolithography using a positive photoresist process, and then the pattern of the anode electrode layer is evaporated using a PVD process, followed by photoresist removal and cleaning.

[0030] S270, finally, laser scribing, chipping and expansion inversion are performed to complete the grain manufacturing of the vertical device.

[0031] According to one embodiment of the present invention, when the substrate layer is a Si substrate, in step S110, the thickness of the substrate layer is thinned to 1 mm to 1.5 mm, and the substrate layer is etched by wet etching, wherein the solution used for wet etching is a mixed solution of HNO3:CH3COOH:HF = 1:3:6.

[0032] According to an embodiment of the present invention, when the substrate layer is a sapphire substrate or a SiC substrate, in step S110, the thickness of the substrate layer is reduced to 0.2 mm to 0.3 mm, and Al2O3 or SiC on the first passivation layer and the N-ohm contact layer is removed by ICP etching technology, laser technology or physical polishing method.

[0033] According to an embodiment of the present invention, in step S130, the annealing environment is an N2@1SLM environment, and the annealing temperature is 750℃~950℃;

[0034] In step S230, the annealing environment is atmospheric, and the annealing temperature is 600℃~650℃.

[0035] These and other objects, features and advantages of the present invention will become fully apparent from the following detailed description. Attached Figure Description

[0036] Figure 1 A schematic diagram of a conventional SBD power device is shown.

[0037] Figure 2 A schematic diagram of a vertical device based on an AlN substrate according to a preferred embodiment of this application is shown.

[0038] Figure 3 A schematic diagram of a vertical device based on an AlN substrate, according to another preferred embodiment of this application, is shown.

[0039] Reference numerals: 10-Epipolar wafer, 11-Substrate layer, 12-Buffer layer, 13-Epipolar layer, 21-First passivation layer, 22-N-ohm contact layer, 23-Cathode electrode layer, 31-Second passivation layer, 32-Schott layer, 33-P-ohm contact layer, 34-Anode electrode layer. Detailed Implementation

[0040] The following description is intended to disclose the present invention and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of the invention defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of the invention.

[0041] Those skilled in the art should understand that, in the disclosure of this specification, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limiting the present invention.

[0042] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0043] refer to Figure 2 and Figure 3A preferred embodiment of the present invention, a vertical device based on an AlN substrate, will be described in detail below. The vertical device based on the AlN substrate includes an epitaxial wafer 10, wherein the epitaxial wafer 10 includes a substrate layer 11, a buffer layer 12, and an epitaxial layer 13 grown sequentially from a first end to a second end. The substrate layer 11 may be a Si substrate, a sapphire substrate, or a SiC substrate. The buffer layer 12 includes an AlN layer and a GaN layer grown sequentially from the substrate layer 11. The thickness of the AlN layer is 20 nm to 30 nm, and the thickness of the GaN layer is 3 μm. The epitaxial layer 13 includes an AlGaN layer, a U-GaN layer, and a P-GaN layer grown sequentially from the buffer layer. It is also worth mentioning that the vertical device has a first passivation layer 21, an N-ohm contact layer 22, and a cathode electrode layer 23 at the first end of the epitaxial wafer 10, and a second passivation layer 31, a Schottky layer 32, a P-ohm contact layer 33, and an anode electrode layer 34 at the second end of the epitaxial wafer 10.

[0044] The first passivation layer 21 and the N-ohm contact layer 22 extend through the substrate layer 11 and the buffer layer 12 to the epitaxial layer 13 on the right side of the epitaxial wafer 10. It should be noted that in order to ensure that the first passivation layer 21 can completely isolate the N-ohm contact layer 22, the cathode electrode layer 23 and the buffer layer 12, the first passivation layer 21 and the N-ohm contact layer 22 generally extend directly into the epitaxial layer 13 until they are etched into the AlGaN layer to a thickness of 20% to 25%. At the same time, the thickness of the N-ohm contact layer 22 is less than the thickness of the first passivation layer 21. In addition, the cathode electrode layer 23 covers the surface of the substrate layer 11, the first passivation layer 21 and the N-ohm contact layer 22.

[0045] The P-GaN layer is located near the left side of the epitaxial layer 13. Meanwhile, the P-ohm contact layer 33 is located on the surface of the P-GaN layer away from the buffer layer 12. The Schottky base layer 32 extends through the epitaxial layer 13 to the buffer layer 12 on the side where the P-GaN layer is located, i.e., on the left side of the epitaxial layer 13, and partially covers the surface of the P-ohm contact layer 33 on the other side. The second passivation layer 31 covers a portion of the buffer layer 12, the Schottky base layer 32, the P-ohm contact layer 33, the P-GaN layer, and the U-GaN layer. The anode electrode layer 34 extends through the second passivation layer 31 to the Schottky base layer 32 on the surface of the second passivation layer 31 away from the buffer layer 12, and at least partially covers the surface of the second passivation layer 31. In this way, the vertical device provided in this application, by changing the positions of the cathode electrode layer 23 and the N-ohm contact layer 22, allows them to be led out from the other side of the epitaxial wafer 12 opposite to the anode electrode layer 34 for conduction and connection to the packaging bracket. This effectively solves the problem that conventional substrates cannot be used to fabricate vertical structure chips due to non-conductivity, and improves the electrical performance of the device, especially high-power devices, including withstand voltage and current resistance. At the same time, the cathode electrode layer 23 penetrates the substrate layer 11 and is led out, which greatly reduces the influence of the substrate on the device in terms of resistance and thermal resistance, further improving the overall performance of the vertical device.

[0046] In addition, it should be noted that the vertical device provided in this application can be connected to the packaging bracket not only at the anode electrode layer 34, but also at the cathode electrode layer 23, making the installation method more flexible and the application range wider. At the same time, based on the characteristic that the thermal conductivity of metal is much higher than that of substrate, the heat dissipation performance of the vertical device provided in this application is also greatly improved.

[0047] In addition, in the conventional case where wire bonding is performed on both the anode and cathode electrodes on the same side, the vertical device provided in this application only requires wire bonding on the electrode on the other side that is not connected to the packaging bracket when the anode electrode layer 34 or the cathode electrode layer 23 is connected to the packaging bracket. This simplifies the process, improves work efficiency, and greatly reduces the possibility of poor soldering of the packaging wire (single wire bonding reduces this by about 50% compared to double wire bonding). It also reduces the cost of using packaging gold wire.

[0048] In addition, it should be noted that because the anode and cathode electrodes are located on the same side in conventional semiconductor chips, the effective length of the PSJ is greatly limited, which significantly affects the total amount of two-dimensional electron gas formed between the U-GaN layer and the AlGaN layer. However, in the vertical device provided in this application, the cathode electrode layer 23 and the N-ohm contact layer 22 are located at the second end of the epitaxial wafer 10. At the same time, the cathode electrode layer 23 covers the surface of the substrate layer 11, the first passivation layer 21 and the N-ohm contact layer 22, which allows the lateral thickness of the N-ohm contact layer 22 to be appropriately reduced. This allows the effective length of the PSJ to be increased as much as possible, thus providing unlimited possibilities for increasing the total amount of two-dimensional electrons and improving the overall electrical performance of the vertical device.

[0049] In one embodiment, the cathode electrode layer 23 covering the surface of the substrate layer 11 has a thickness of 2um to 10um, such as 3um, 4um, 5um, 6um, 7um, 8um or 9um.

[0050] More preferably, the thickness of the anode electrode layer 34 covering the surface of the second passivation layer 31 is 2um to 10um, such as 3um, 4um, 5um, 6um, 7um, 8um or 9um.

[0051] More preferably, the thickness of the first passivation layer 21 in the lateral direction is 1um to 3um, such as 1.5um, 2um or 2.5um.

[0052] More preferably, the thickness of the second passivation layer 31 covering the surface of the U-GaN layer is 1um to 8um, such as 1.5um, 2um, 3um, 4um, 5um or 6.5um.

[0053] In one embodiment, the anode electrode layer 34 completely covers the surface of the second passivation layer 31 away from the buffer layer 12, or partially covers the surface of the second passivation layer 31 away from the buffer layer 12 on both sides (e.g., Figure 2 As shown in the diagram, when the second passivation layer 31 has a larger lateral width on the right side, the portion of the anode electrode layer 34 covering the right side is larger than the portion covering the left side. Furthermore, when the second passivation layer 31 has partial coverage on both sides, the lateral width of the coverage on both sides is not mandatory; the coverage on both sides can be the same width, or the width of the coverage on the right side can be smaller than the width of the coverage on the left side.

[0054] Secondly, based on the same technical principle, the present invention also provides a method for manufacturing the aforementioned vertical device based on an AlN substrate, which sequentially includes a method for manufacturing the vertical device at a first end of an epitaxial wafer 10 and a method for manufacturing the vertical device at a second end of an epitaxial wafer 10. That is, the vertical device is first manufactured at the first end of the epitaxial wafer 10, and then manufactured at the second end of the epitaxial wafer 10. The method for manufacturing the vertical device at the first end of the epitaxial wafer 10 includes the following steps:

[0055] S110, the substrate layer 11 is thinned to a predetermined thickness, and the pattern of the first passivation layer 21 and the N-ohm contact layer 22 is etched using a positive photoresist photolithography process. Then, the substrate layer 11 is etched, and then the buffer layer 12 exposed in the pattern of the first passivation layer 21 and the N-ohm contact layer 22 is etched using an ICP etching process. In addition, in order to ensure that the first passivation layer 21 can completely isolate the N-ohm contact layer 22, the cathode electrode layer 23 and the buffer layer 12, 20% to 25% of the thickness of the AlGaN layer can be directly etched away, the photoresist is removed and the layer is cleaned.

[0056] S120, a PV (SiO2) layer is fabricated using processes such as ALD / PVD / CVD, and the pattern of the first passivation layer 21 is then etched using a positive photolithography process. The PV layer outside the first passivation layer 21 is then removed using wet HF etching or ICP etching technology, and then the photoresist is removed and the surface is cleaned.

[0057] S130, the pattern of the N-ohmic contact layer 22 is etched by photolithography using negative photoresist, and then the metal electrode (Ni / Al / Ni / Au) is evaporated by PVD or ALD process, and then the N-ohmic contact layer (N-ohmic) 22 is fabricated by metal stripping process, and finally RTA annealing is performed.

[0058] S140, fabricate the negative electrode layer 23;

[0059] The method for manufacturing the vertical device at the second end of the epitaxial wafer 10 includes the following steps:

[0060] S210, the U-GaN layer and the AlGaN layer are patterned using a positive photolithography process, and then the U-GaN layer and the AlGaN layer are etched using an ICP etching process, followed by photoresist removal and cleaning.

[0061] S220, the pattern of the P-GaN layer is formed by photolithography using positive photoresist, and then the P-GaN layer is etched by ICP etching, followed by photoresist removal and cleaning.

[0062] S230, the pattern of the P-ohm contact layer 33 is etched using a positive photolithography process, then the metal electrode of the P-ohm contact layer 33 is evaporated using a PVD process, then the layer is peeled off, the photoresist is removed and cleaned, and then an RTA annealing process is performed.

[0063] S240, the pattern of the Schottky base layer 32 is etched using a positive photolithography process, and then the metal electrode (Ni / Au) of the Schottky base layer 32 is evaporated using a PVD process;

[0064] S250, the second passivation layer 31 is deposited or evaporated using processes such as PECVD or PVD, or the second passivation layer 31 is formed by photolithography using a positive photoresist process;

[0065] S260, the pattern of the anode electrode layer 34 is formed by photolithography using a positive photoresist process, and then the pattern of the anode electrode layer 34 is evaporated using a PVD process, followed by photoresist removal and cleaning.

[0066] S270, finally, laser scribing, chipping and expansion inversion are performed to complete the grain manufacturing of the vertical device.

[0067] In one embodiment, when the substrate layer 11 is a Si substrate, in step S110, the thickness of the substrate layer 11 is thinned to 1 mm to 1.5 mm, such as 1.1 mm, 1.2 mm, 1.3 mm or 1.4 mm, and the substrate layer 11 is etched by wet etching, wherein the solution used for wet etching is a mixed solution of HNO3:CH3COOH:HF = 1:3:6.

[0068] In another embodiment, when the substrate layer 11 is a sapphire substrate, in step S110, the thickness of the substrate layer is thinned to 0.2 mm to 0.3 mm, for example, any value from 0.21 mm to 0.29 mm, and the Al2O3 on the first passivation layer 21 and the N-ohm contact layer 22 is removed using ICP etching, laser technology, or physical polishing method; or, when the substrate layer 11 is a SiC substrate, in step S110, the thickness of the substrate layer 11 is thinned to 0.2 mm to 0.3 mm, for example, any value from 0.21 mm to 0.29 mm, and the SiC on the first passivation layer 21 and the N-ohm contact layer 22 is removed using ICP etching, laser technology, or physical polishing method.

[0069] More preferably, in step S130, the annealing environment is an N2@1SLM environment, or the N2 flow rate is 1L / min, and the annealing temperature is 750℃~950℃, such as a high temperature environment of 770℃, 800℃, 830℃, 860℃, 890℃, 920℃ or 940℃.

[0070] In step S230, the annealing environment is an atmospheric environment, and the annealing temperature is 600℃~650℃, such as 610℃, 620℃, 630℃, 635℃ or 640℃.

[0071] It should be noted that the terms "first" and "second" used in this invention are for descriptive purposes only and do not indicate any order. They should not be construed as indicating or implying relative importance, and can be interpreted as names.

[0072] Those skilled in the art should understand that the embodiments of the present invention described above and shown in the accompanying drawings are merely examples and do not limit the invention. The advantages of the present invention have been fully and effectively realized. The functional and structural principles of the present invention have been demonstrated and explained in the embodiments; any variations or modifications can be made to the implementation of the present invention without departing from these principles.

Claims

1. A vertical device based on an AlN substrate comprising an epitaxial wafer, wherein the epitaxial wafer comprises a substrate layer, a buffer layer and an epitaxial layer formed by growth in order from a first end to a second end, wherein the epitaxial layer comprises an AlGaN layer, a U-GaN layer and a P-GaN layer grown in order from the buffer layer, characterized in that, The vertical device is provided with a first passivation layer, an N ohmic contact layer and a cathode electrode layer at the first end of the epitaxial wafer, and a second passivation layer, a Schottky layer, a P ohmic contact layer and an anode electrode layer at the second end of the epitaxial wafer; Wherein the first passivation layer and the N ohmic contact layer extend through the substrate layer and the buffer layer to the epitaxial layer on one side of the epitaxial wafer, the thickness of the N ohmic contact layer is less than the thickness of the first passivation layer, and the cathode electrode layer covers the surface of the substrate layer, the first passivation layer and the N ohmic contact layer; Wherein the P-GaN layer is close to one side of the epitaxial layer, the P ohmic contact layer is located on the surface of the P-GaN layer away from the buffer layer, the Schottky layer extends through the epitaxial layer to the buffer layer on the side where the P-GaN layer is located, and partially covers the surface of the P ohmic contact layer, the second passivation layer covers part of the buffer layer, the Schottky layer, the P ohmic contact layer, the P-GaN layer and the U-GaN layer, and the anode electrode layer extends through the second passivation layer to the Schottky layer on the surface of the second passivation layer away from the buffer layer, and at least partially covers the surface of the second passivation layer.

2. The vertical device based on an AlN substrate according to claim 1, wherein, The thickness of the cathode electrode layer covering the surface of the substrate layer is 2 μm to 10 μm.

3. The vertical device based on an AlN substrate according to claim 2, wherein, The thickness of the anode electrode layer covering the surface of the second passivation layer is 2 μm to 10 μm.

4. The vertical device based on an AlN substrate according to claim 3, wherein, The thickness of the first passivation layer laterally is 1 μm to 3 μm.

5. The vertical device based on an AlN substrate according to claim 4, wherein, The thickness of the second passivation layer covering the surface of the U-GaN layer is 1 μm to 8 μm.

6. The AlN substrate based vertical device according to any one of claims 1 to 5, wherein The anode electrode layer either completely covers the surface of the second passivation layer away from the buffer layer, or partially covers the surface of the second passivation layer away from the buffer layer on both sides.

7. A method of fabricating a vertical device based on AlN substrates according to any one of claims 1 to 6, characterized in that, The manufacturing method of the vertical device at the first end of the epitaxial wafer and the manufacturing method at the second end of the epitaxial wafer are sequentially included, wherein the manufacturing method of the vertical device at the first end of the epitaxial wafer comprises the following steps: S110, thinning the substrate layer to a predetermined thickness, using a positive photoresist lithography process to etch the pattern of the first passivation layer and the N ohmic contact layer, then etching the substrate layer, then using an ICP etching process to etch the exposed buffer layer in the pattern of the first passivation layer and the N ohmic contact layer, removing the photoresist and cleaning; S120, making a PV layer, using a positive photoresist lithography process to etch the pattern of the first passivation layer, then removing the PV layer except the first passivation layer, then removing the photoresist and cleaning; S130, using a negative photoresist to etch the pattern of the N ohmic contact layer by a lithography process, then performing metal electrode evaporation, then performing a metal stripping process to make the N ohmic contact layer, and finally performing an RTA annealing process; S140, making the cathode electrode layer; The manufacturing method of the vertical device at the second end of the epitaxial wafer comprises the following steps: S210, using a positive photoresist lithography process to pattern the U-GaN layer and the AlGaN layer, and then using an ICP etching process to etch the U-GaN layer and the AlGaN layer, and then removing the photoresist and cleaning; S220, using a positive photoresist lithography process to pattern the P-GaN layer, and then using an ICP etching process to etch the P-GaN layer, and then removing the photoresist and cleaning; S230, using a positive photoresist lithography process to pattern the P-ohmic contact layer, and then using a PVD process to evaporate the metal electrode of the P-ohmic contact layer, and then removing the photoresist and cleaning, and then performing RTA annealing treatment; S240, using a positive photoresist lithography process to pattern the Schottky layer, and then using a PVD process to evaporate the metal electrode of the Schottky layer; S250, depositing, or evaporating, or patterning the second passivation layer; S260, using a positive photoresist lithography process to pattern the anode electrode layer, and then using a PVD process to evaporate the anode electrode layer, and then removing the photoresist and cleaning; S270, finally performing laser scribing, chipping and expansion inversion to complete the wafer manufacturing of the vertical device.

8. The method of manufacturing an AlN substrate-based vertical device according to claim 7, wherein, When the substrate layer is a Si substrate, in step S110, the thickness of the substrate layer is thinned to 1mm-1.5mm, and the substrate layer is etched by using a wet etching method, wherein the solution used in the wet etching method is a mixed solution of HNO3:CH3COOH:HF=1:3:

6.

9. The method of manufacturing an AlN substrate-based vertical device according to claim 7, wherein, When the substrate layer is a sapphire substrate or a SiC substrate, in step S110, the thickness of the substrate layer is thinned to 0.2mm-0.3mm, and the substrate layer exposed in the pattern of the first passivation layer and the N-ohmic contact layer is removed by using an ICP etching technology, a laser technology or a physical grinding method.

10. The method of manufacturing an AlN substrate-based vertical device according to claim 8 or 9, wherein, In step S130, the annealing environment is N2@1SLM, and the annealing temperature is 750℃-950℃. In step S230, the annealing environment is an atmospheric environment, and the annealing temperature is 600℃-650℃.

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