Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the method comprising: forming an insulating medium layer on a substrate, a plurality of initial composite layers on a part of a surface of the insulating medium layer, a pseudo gate structure across the initial composite layers, the initial composite layers extending along a first direction, a first opening in the initial composite layers on both sides of the pseudo gate structure, the first opening exposing the insulating medium layer, the pseudo gate structure being on a sidewall and a top surface of the initial composite layers, the pseudo gate structure comprising a pseudo gate layer, the initial composite layers comprising a plurality of vertically overlapped channel layers and a plurality of sacrificial layers between adjacent two channel layers; forming source-drain layers on a surface of the channel layers of the sidewall of the first opening by using a selective epitaxial growth process until the source-drain layers cover the sidewall of the first opening and have third openings exposing the insulating medium layer between adjacent source-drain layers; and forming a conductive structure in the third openings, thereby improving the performance of a device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has been reduced to its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.

[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.

[0004] However, the performance of existing gate-all-around devices needs further improvement. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.

[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; an insulating dielectric layer on the substrate; a plurality of composite layers located on a portion of the surface of the insulating dielectric layer, the composite layers extending along a first direction, the composite layers having a first opening that exposes the insulating dielectric layer, the composite layers including a plurality of vertically overlapping channel layers and a second opening located between two adjacent channel layers, the second opening suspending adjacent channel layers; a gate structure located on the surface of the channel layers and annularly surrounding the channel layers; the composite layers further including an inner sidewall located between two adjacent channel layers and located on the sidewall of the second opening, the outer sidewall of the inner sidewall sharing a vertical plane with the sidewall of the channel layers; a source / drain layer located on the surface of the channel layers on the sidewall of the first opening, the source / drain layer covering the first opening sidewall, and a third opening exposing the insulating dielectric layer between adjacent source / drain layers; and a conductive structure located within the third opening.

[0007] Optionally, it further includes: a first dielectric layer located on the substrate surface, the top of the source / drain layer, and the sidewall of the gate structure, the first dielectric layer having a fourth opening, the fourth opening being located above the third opening and communicating with the third opening; the conductive structure is also located within the fourth opening.

[0008] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layers on the substrate, wherein the initial composite layers extend along a first direction, and a first opening is located in the initial composite layers on both sides of the dummy gate structure, the first opening exposing the insulating dielectric layer, the dummy gate structure being located on the sidewalls and top surface of the initial composite layer, the dummy gate structure including a dummy gate layer, the initial composite layers including a plurality of vertically overlapping channel layers, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer, the outer sidewall of the inner sidewall sharing a vertical plane with the sidewall of the channel layer; forming a source / drain layer on the surface of the channel layer on the sidewall of the first opening using a selective epitaxial growth process until the source / drain layer covers the first opening sidewall, and a third opening exposing the insulating dielectric layer is present between adjacent source / drain layers; and forming a conductive structure within the third opening.

[0009] Optionally, before forming the conductive structure and after forming the source / drain layer, the method further includes: forming an interlayer dielectric material layer on the substrate, the interlayer dielectric material layer being located within the third opening and on the sidewall and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed to form a first dielectric layer; removing the dummy gate layer to form a gate opening within the first dielectric layer; removing the sacrificial layer exposed by the gate opening to form a second opening between adjacent channel layers, forming a composite layer with the initial composite layer; and forming a gate structure within the gate opening and the second opening.

[0010] Optionally, after forming the gate structure and before forming the conductive structure, the method further includes: forming a fourth opening in the first dielectric layer, the fourth opening being located above the third opening and communicating with the third opening; forming a first sidewall on the sidewall of the fourth opening; and using the first sidewall as a mask to remove the first dielectric layer in the third opening, thereby exposing the third opening.

[0011] Optionally, the process for removing the first dielectric layer within the third opening includes one or a combination of dry etching and wet etching.

[0012] Optionally, the process for removing the first dielectric layer within the third opening includes a dry etching process; the process parameters of the dry etching process include: using asynchronous pulsed plasma with a pressure range of 3 mTorr to 20 mTorr, and the etching gas including fluorocarbon, wherein the carbon and fluorine composition ratio ranges from 1:2 to 1:6.

[0013] Optionally, before forming the fourth opening, a second dielectric layer is also formed on the surface of the first dielectric layer and the gate structure; the fourth opening is also located within the second dielectric layer; the method for forming the fourth opening includes: forming a first mask layer on the surface of the second dielectric layer, the first mask layer exposing a portion of the surface of the second dielectric layer on the third opening; using the first mask layer as a mask, etching the second dielectric layer and the first dielectric layer until the bottom of the fourth opening is at a target size from the top surface of the source / drain layer.

[0014] Optionally, the target size ranges from 5 angstroms to 100 angstroms.

[0015] Optionally, the conductive structure is also located within the fourth opening; the method of forming the conductive structure includes: forming a conductive material layer within the third opening, the fourth opening, and the top surface of the second dielectric layer; planarizing the conductive material layer until the top surface of the second dielectric layer is exposed.

[0016] Optionally, the process for forming the conductive structure includes: a metal material growth process and an annealing process following the metal material growth process.

[0017] Optionally, the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film.

[0018] Optionally, the process parameters of the etching process include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

[0019] Optionally, the method for forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure includes: forming a first sacrificial material layer on the surface of the substrate, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer including a plurality of vertically overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a second mask layer on the surface of the initial composite material layer, the second mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the second mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers, the composite material layers extending along the first direction; forming a structure spanning the composite material layers. Several dummy gate structures are described, the dummy gate structures being located on a portion of the sidewalls and surface of the composite material layer; using the dummy gate structures as a mask, the composite material layer is etched until the first sacrificial material layer is exposed, forming the first opening within the composite material layer; a transition sacrificial layer is formed using the second sacrificial material layer; and the channel layer is formed using the channel material layer; after forming the first opening, the first sacrificial material layer is removed to form an insulating trench on the substrate surface; an insulating dielectric layer is formed within the insulating trench; after forming the insulating dielectric layer, the transition sacrificial layer is etched to form the sacrificial layer and a fifth opening located on the sidewall of the sacrificial layer between two adjacent channel layers; and an inner sidewall is formed within the fifth opening.

[0020] Optionally, the method for forming the inner sidewall further includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; and etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed.

[0021] Optionally, the material of the first sacrificial material layer includes germanium and silicon, wherein the ratio of germanium to silicon in the first sacrificial material layer ranges from 1:10 to 1:2; the material of the second sacrificial layer includes germanium and silicon, wherein the ratio of germanium to silicon in the second sacrificial material layer ranges from 2:5 to 7:10; and the material of the channel material layer includes silicon.

[0022] Optionally, the etching process for removing the first sacrificial layer has a selection ratio of 10:1 to 150:1 for the first sacrificial material layer and the second sacrificial material layer.

[0023] Optionally, the substrate has a well region containing a first doped ion; before forming the first sacrificial material layer, a second doped ion is implanted on the surface of the substrate, the second doped ion having a different conductivity type than the first doped ion.

[0024] Optionally, the method for forming the insulating dielectric layer includes: forming a first dielectric material layer in the insulating trench, the first dielectric material layer also being located on the first opening sidewall, and on the dummy gate structure sidewall and top surface; etching the first dielectric material layer until the dummy gate structure sidewall and top surface, as well as the first opening sidewall, are exposed.

[0025] Optionally, the etching process for the first dielectric material layer includes inductively coupled plasma etching or capacitively coupled plasma etching.

[0026] Optionally, the formation process of the first dielectric material layer includes atomic layer deposition.

[0027] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0028] In the semiconductor structure formation method provided by the present invention, on the one hand, a selective epitaxial growth process is used to epitaxially grow source and drain layers from the sidewall of the channel layer, and a third opening is provided between adjacent source and drain layers. The source and drain layers on the sidewall of adjacent channel layers along the first direction are separated from each other. Therefore, defects caused by the initial nucleation surface not being a whole seed crystal and the uneven distribution of nucleation points are reduced, thereby reducing stress release in the channel caused by defects and improving device performance. On the other hand, a conductive structure is formed in the third opening, so that the conductive structure wraps the source and drain layers. Therefore, the contact area between the source and drain layers and the conductive structure is increased, the contact resistance is reduced, and the device performance is further improved.

[0029] Furthermore, using the first sidewall as a mask, the first dielectric layer inside the third opening is removed, exposing the third opening. Due to the difference in materials between the first dielectric layer and the source / drain layer, the etching process for removing the first dielectric layer inside the third opening can achieve self-aligned etching.

[0030] Furthermore, the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film. The selective epitaxial growth process causes the source / drain layer material to grow epitaxially on the sidewalls of the channel layer, and reduces the merging of the source / drain layers on adjacent sidewalls of the channel layer along the first direction.

[0031] Furthermore, during the formation of the conductive structure, the annealing process causes a change in the volume of the conductive structure, resulting in compressive stress on the channel. This compressive stress can reduce the effective conductivity mass of holes in the channel direction of the PMOS device, thereby improving the speed of the PMOS device.

[0032] In the semiconductor structure provided by the present invention, on the one hand, the source / drain layers located on the sidewalls of the channel layer are separated from each other along the first direction, and there is a third opening between the adjacent source / drain layers. The source / drain layers on the sidewalls of the adjacent channel layer along the first direction are not connected, which reduces defects caused by the initial nucleation surface not being a whole seed crystal and the uneven distribution of nucleation points, thereby reducing stress release in the channel caused by defects and thus improving the performance of the device. On the other hand, the conductive structure located in the third opening is also located on the sidewalls of the source / drain layers, so that the conductive structure wraps the source / drain layers. Therefore, the contact area between the source / drain layers and the conductive structure is increased, the contact resistance is reduced, and the performance of the device is further improved. Attached Figure Description

[0033] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;

[0034] Figures 4 to 12 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention. Detailed Implementation

[0035] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.

[0036] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process.

[0037] Please refer to Figure 1A substrate 100 is provided; an insulating dielectric layer 101, a composite layer on a portion of the surface of the insulating dielectric layer 101, and a gate structure on the surface of the composite layer are formed on the substrate 100. The gate structure includes a gate layer 104 and a protective layer 105 on the surface of the gate layer. The composite layer includes a plurality of vertically overlapping sacrificial layers 102 and a channel layer 103 located between two adjacent sacrificial layers 102.

[0038] Please refer to Figure 3 Source / drain layers 107 are formed on the substrates 100 on both sides of the gate structure, and the source / drain layers 107 are located on the sidewall surface of the channel layer 103.

[0039] The above method is used in GAA device structures, where the insulating dielectric layer 101 is used to isolate the channel layer of the device from the substrate to reduce the leakage current of the formed device. The method for forming the source / drain layer 107 includes: forming an epitaxial layer on the sidewall of the channel layer 103 by epitaxial growth technology; and implanting dopant ions into the epitaxial layer. Figure 2 The diagram shows the distribution of epitaxial material 106 on the sidewalls of the channel layer 103 during the initial formation of the source / drain layer 107. Since the substrate surface 100 is covered by the insulating dielectric layer 101, the epitaxial material can only grow from the surface of the sidewalls of the channel layer 103. Ultimately, the epitaxial materials on adjacent sidewalls of the channel layer 103 along the channel direction merge and connect, and the epitaxial materials on adjacent sidewalls of the channel layer 103 along the substrate normal direction merge and connect, thereby forming the source / drain layer 107.

[0040] Because the channel layers 103 are discretely separated along the substrate normal, the source / drain layers 107 use the sidewalls of the channel layers 103 as initial nucleation surfaces. Since the initial nucleation surfaces are not a single seed crystal and the nucleation points are unevenly distributed, a large number of defects are generated within the final source / drain layers 107. For example... Figure 3 As shown, the epitaxial material layer interface of adjacent channel layer 103 sidewalls along the channel direction is relatively rough, making it prone to defects such as voids; this is referred to as vertical defect B. Conversely, the epitaxial material layer interface of adjacent channel layer 103 sidewalls along the substrate normal direction is also relatively rough, making it prone to defects such as voids; this is referred to as horizontal defect A. Both horizontal defect A and vertical defect B cause stress release due to these defects, affecting the stress within the channel layer 103 and further impacting the mobility of electrons or holes within the channel, thus reducing device performance.

[0041] To address the aforementioned issues, this invention provides a semiconductor structure formation method that reduces defects caused by the initial nucleation surface not being a single seed crystal and uneven distribution of nucleation points. This, in turn, reduces stress release in the channel due to defects, thereby improving device performance. Furthermore, a conductive structure is formed within the third opening, encapsulating the source / drain layer. This increases the contact area between the source / drain layer and the conductive structure, reduces contact resistance, and further enhances device performance.

[0042] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0043] Figures 4 to 12 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention.

[0044] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 Top view structural diagram, Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the DD1 direction is provided, showing the substrate 200.

[0045] In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon-on-insulator, or germanium-on-insulator.

[0046] In this embodiment, the substrate has a well region (not shown in the figure), and the well region contains a first dopant ion. Specifically, in this embodiment, the first dopant ion is an N-type ion, used to form the well region of a PMOS device. In other embodiments, the first dopant ion is a P-type ion, used to form the well region of an NMOS device.

[0047] Subsequently, an insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layers are formed on the substrate 200. The initial composite layers extend along a first direction. First openings are located within the initial composite layers on both sides of the dummy gate structure, exposing the insulating dielectric layer. The dummy gate structure is located on the sidewalls and top surface of the initial composite layers. The dummy gate structure includes a dummy gate layer. The initial composite layers include a plurality of vertically overlapping channel layers, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer. The outer sidewall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. For the method of forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure, please refer to [reference needed]. Figures 4 to 7 .

[0048] Please continue to refer to this. Figures 4 to 5 A first sacrificial material layer 201 is formed on the surface of the substrate 200, and an initial composite material layer (not shown in the figure) is formed on the surface of the first sacrificial material layer 201. The initial composite material layer includes several vertically overlapping channel material layers (not shown in the figure) and a second sacrificial material layer (not shown in the figure) located between two adjacent channel layers. A second mask layer (not shown in the figure) is formed on the surface of the initial composite material layer, and the second mask layer exposes a portion of the initial composite material layer. The initial composite material layer is etched using the second mask layer as a mask until the surface of the first sacrificial material layer 201 is exposed, forming several composite material layers 202, which extend along the first direction X. Several dummy gate structures 203 are formed across the composite material layers 202, and the dummy gate structures 203 are located on a portion of the sidewalls and surface of the composite material layers 202.

[0049] The first direction X is the channel direction.

[0050] The dummy gate structure 203 includes a dummy gate layer 204. In this embodiment, the dummy gate structure 203 further includes a protective layer 205 located on the surface of the dummy gate layer 204.

[0051] The first sacrificial material layer 201 occupies space for the subsequent formation of the insulating dielectric layer.

[0052] In this embodiment, before forming the first sacrificial material layer 201, a second dopant ion is implanted onto the surface of the substrate 200. The second dopant ion has a different conductivity type than the first dopant ion. Specifically, the second dopant ion is a p-type ion.

[0053] The material of the second sacrificial material layer is different from that of the channel material layer. The channel material layer is used to form the channel layer, and the second sacrificial material layer is used to form the second sacrificial layer subsequently. The second sacrificial layer occupies space for the subsequent formation of the gate structure and will be removed later. The material of the second sacrificial material layer has a higher etch selectivity than the material of the channel material layer, so that the subsequent removal of the second sacrificial layer has less impact on the channel layer; the material of the second sacrificial material layer has better lattice matching than the material of the channel material layer, so as to obtain a smooth interface between the second sacrificial layer and the channel layer, making the surface of the subsequently formed channel layer flat, which is conducive to obtaining a device with good performance.

[0054] The material of the second sacrificial material layer includes silicon; the material of the channel material layer includes germanium-silicon. In this embodiment, the material of the channel material layer is silicon; the material of the second sacrificial material layer is germanium-silicon. In other embodiments, the channel material layer is Ge or GeSi. In other embodiments, the material of the second sacrificial material layer can be ZnS, ZnSe, BeS, or GaP, etc.

[0055] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 Top view structural diagram, Figure 7 for Figure 6 A cross-sectional view along the DD1 direction is shown. Using the pseudo gate structure 203 as a mask, the composite material layer 202 is etched until the first sacrificial material layer 201 is exposed, forming the first opening 206 in the composite material layer 202. The second sacrificial material layer forms a transition sacrificial layer (not shown in the figure), and the channel material layer forms the channel layer 208.

[0056] The material of the first sacrificial material layer 201 is different from the material of the second sacrificial material layer. The sacrificial layer is formed by the second sacrificial material layer. Therefore, the material of the first sacrificial material layer 201 is different from the material of the second sacrificial material layer, and the material of the first sacrificial material layer is different from that of the substrate 200. This allows for the selection of an etching process with a larger etching selectivity between the first sacrificial material layer 201 and the second sacrificial material layer, and between the first sacrificial material layer 201 and the substrate 200, when removing the first sacrificial material layer 201, thereby reducing etching damage to the sacrificial layer and the substrate 200.

[0057] The first sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 1:10 to 1:2. The second sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 2:5 to 7:10. The channel material layer comprises silicon. The germanium and silicon composition ranges in the first and second sacrificial material layers are different to ensure that the first sacrificial material layer 201 has a larger etching selectivity relative to the second sacrificial layer during the etching process.

[0058] Please continue to refer to this. Figure 6 and Figure 7After forming the first opening, the first sacrificial material layer 201 is removed to form an insulating trench (not shown in the figure) on the surface of the substrate 200; an insulating dielectric layer 210 is formed in the insulating trench; after forming the insulating dielectric layer 210, the transition sacrificial layer is etched to form the sacrificial layer 207 and a fifth opening (not shown in the figure) located on the sidewall of the sacrificial layer 207 between the two adjacent channel layers 208; the inner sidewall 209 is formed in the fifth opening.

[0059] The initial composite layer includes several vertically overlapping channel layers 208, a sacrificial layer 207 located between two adjacent channel layers 208, and an inner wall 209 located on the sidewall of the sacrificial layer 207, wherein the outer wall of the inner wall 209 shares a vertical plane with the sidewall of the channel layer 208.

[0060] The method for forming the insulating dielectric layer 210 includes: forming a first dielectric material layer (not shown in the figure) in the insulating trench, the first dielectric material layer also being located on the sidewall of the first opening 206, and on the sidewall and top surface of the dummy gate structure 203; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure 203 and the sidewall of the first opening 206 are exposed.

[0061] The etching process for the first dielectric material layer includes inductively coupled plasma etching or capacitively coupled plasma etching.

[0062] The formation process of the first dielectric material layer includes atomic layer deposition (ALD). ALD facilitates the formation of a uniform first dielectric material layer and has excellent trench filling capability, thereby improving the performance of the insulating dielectric layer 210.

[0063] The etching process for removing the first sacrificial material layer has a selection ratio of 10:1 to 150:1 for the first sacrificial material layer and the second sacrificial material layer.

[0064] In this embodiment, the sidewall of the sacrificial layer 207 is recessed relative to the sidewall of the channel layer 208, and the initial composite layer also includes an inner sidewall 209 located on the sidewall of the sacrificial layer 207.

[0065] The method for forming the inner sidewall 209 further includes: forming a second dielectric material layer (not shown in the figure) on the surface of the insulating dielectric layer 210, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall and top surface of the dummy gate structure 203; and etching back the second dielectric material layer until the surface of the insulating dielectric layer 210, the surface of the initial composite layer sidewall, the sidewall and top surface of the dummy gate structure 203 are exposed.

[0066] The inner wall 209 is used to isolate the subsequently formed gate structure and source / drain layer, preventing the mutual diffusion of ions between the source / drain layer and the gate structure, thereby improving the stability of device performance.

[0067] It should be noted here that subsequent references Figures 8 to 12 The view direction is the same Figure 7 .

[0068] Please refer to Figure 8 A source / drain layer 212 is formed on the surface of the channel layer 208 on the sidewall of the first opening 206 using a selective epitaxial growth process until the source / drain layer 212 covers the sidewall of the first opening 206, and a third opening 211 is formed between adjacent source / drain layers 212 to expose the insulating dielectric layer.

[0069] A selective epitaxial growth process is used to epitaxially grow source / drain layers 212 from the sidewall of the channel layer 208, and a third opening 211 is provided between adjacent source / drain layers 212. The source / drain layers on the sidewall of adjacent channel layers are separated from each other along the first direction X. Therefore, the generation of defects in the final source / drain layers 212 caused by the separation of the channel layers 208 as seed crystals along the normal direction of the substrate is reduced, thereby reducing the stress release in the channel caused by defects and improving the performance of the device.

[0070] The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film and an etching process following the formation of the material film. The selective epitaxial growth process causes the source / drain layer 212 material to grow epitaxially on the sidewall of the channel layer 208, and reduces the merging of the source / drain layers 212 along the sidewall of adjacent channel layers 208 along the first direction.

[0071] The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

[0072] Subsequently, a conductive structure is formed within the third opening 211. In this embodiment, before forming the conductive structure and after forming the source / drain layer, please refer to... Figures 9 to 11 .

[0073] Please refer to Figure 9An interlayer dielectric material layer (not shown in the figure) is formed on the substrate 200. The interlayer dielectric material layer is located within the third opening 211 and on the sidewall and top surface of the dummy gate structure 203. The interlayer dielectric material layer is planarized until the dummy gate layer 204 is exposed, forming a first dielectric layer 213. The dummy gate layer 203 is removed, and a gate opening (not shown in the figure) is formed within the first dielectric layer 213. The sacrificial layer 207 exposed by the gate opening is removed, forming a second opening (not shown in the figure) between adjacent channel layers 208, forming a composite layer with the initial composite layer. A gate structure 214 is formed within the gate opening and the second opening.

[0074] The composite layer includes several vertically overlapping channel layers 208, a second opening located between two adjacent channel layers 208, and an inner wall 209 located between two adjacent channel layers 208 and on the sidewall of the second opening. The outer wall of the inner wall 209 shares a vertical plane with the sidewall of the channel layer 208.

[0075] In this embodiment, while forming the first dielectric layer 213, a second sidewall 215 is also formed with the protective layer 205.

[0076] Subsequently, a fourth opening is formed within the first dielectric layer 213. In this embodiment, before forming the fourth opening, a second dielectric layer 216 is also formed on the surfaces of the first dielectric layer 213 and the gate structure 214; the fourth opening is also located within the second dielectric layer 216.

[0077] Please refer to Figure 10 After forming the gate structure 214 and before forming the conductive structure, the method further includes: forming a fourth opening 218 in the first dielectric layer 213, the fourth opening 218 being located above the third opening 211 and communicating with the third opening 211; and forming a first sidewall 319 on the sidewall of the fourth opening 218.

[0078] The first sidewall 319 is used to protect the first dielectric layer 213 during the etching process of removing the first dielectric layer 213 in the third opening 211, and to reduce etching damage to the first dielectric layer 213.

[0079] In this embodiment, the fourth opening 218 is also located within the second dielectric layer 216.

[0080] The method for forming the fourth opening 218 includes: forming a first mask layer 217 on the surface of the second dielectric layer 216, the first mask layer 217 exposing a portion of the surface of the second dielectric layer 216 on the third opening 211; using the first mask layer 217 as a mask, etching the second dielectric layer 216 and the first dielectric layer 213 until the bottom of the fourth opening 218 is a target dimension m away from the top surface of the source / drain layer 212.

[0081] The target size m ranges from 5 angstroms to 100 angstroms. The purpose of selecting the target size m range is that if the target size is too large, it will affect the performance of the subsequent formation of the conductive structure; conversely, if the target size is too small, the surface of the source / drain layer 212 may be damaged due to over-etching during the process of removing the first dielectric layer 213 in the third opening 211.

[0082] Please refer to Figure 11 Using the first sidewall 319 as a mask, the first dielectric layer 213 inside the third opening 211 is removed, exposing the third opening 211.

[0083] Using the first sidewall 319 as a mask, the first dielectric layer 213 inside the third opening 211 is removed, exposing the third opening 211. Due to the different materials of the first dielectric layer 213 and the source / drain layer 212, the etching process of removing the first dielectric layer 213 inside the third opening 211 can achieve self-aligned etching.

[0084] The process for removing the first dielectric layer 213 within the third opening 211 includes one or a combination of dry etching and wet etching.

[0085] In this embodiment, the process of removing the first dielectric layer 213 within the third opening 211 includes a dry etching process; the process parameters of the dry etching process include: using asynchronous pulsed plasma, with a pressure range of 3 mTorr to 20 mTorr, and the etching gas including fluorocarbon, wherein the composition ratio of carbon to fluorine ranges from 1:2 to 1:6.

[0086] The selection of the process conditions and parameter range of the dry etching process is beneficial to improving the etching selectivity of the first dielectric layer 213 relative to the source / drain layer 212 and reducing damage to the source / drain layer 212 during the etching process. In this embodiment, the etching selectivity range of the dry etching process for the first dielectric layer 213 and the source / drain layer 212 is greater than 20.

[0087] Please refer to Figure 12 A conductive structure 219 is formed within the third opening 211.

[0088] A conductive structure 219 is formed within the third opening 211, which encloses the source / drain layer 212. This increases the contact area between the source / drain layer 212 and the conductive structure 219, reduces the contact resistance, and further improves the device performance.

[0089] In this embodiment, the conductive structure 219 is also located within the fourth opening 218.

[0090] The method for forming the conductive structure 219 includes: forming a conductive material layer (not shown in the figure) in the third opening 211, the fourth opening 218 and the top surface of the second dielectric layer 216; planarizing the conductive material layer until the top surface of the second dielectric layer 216 is exposed.

[0091] The formation process of the conductive structure 219 includes a metal material growth process and an annealing process following the metal material growth process. During the formation of the conductive structure, the annealing process causes a change in the volume of the conductive structure, resulting in compressive stress on the channel. This compressive stress can reduce the effective conductivity mass of holes in the channel direction of the PMOS device, thereby improving the speed of the PMOS device.

[0092] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 12 The system includes: a substrate 200; an insulating dielectric layer 210 located on the substrate 200; and a plurality of composite layers located on a portion of the surface of the insulating dielectric layer 210, the composite layers extending along a first direction X, and each composite layer having a first opening 206 (e.g., ...). Figure 11 As shown in the figure, the first opening 206 exposes the insulating dielectric layer 210. The composite layer includes several vertically overlapping channel layers 208 and a second opening (not shown) located between two adjacent channel layers 208, which suspends the adjacent channel layers 208. A gate structure 214 is located on the surface of the channel layer 208 and surrounds the channel layer 208 in an annular shape. The composite layer also includes an inner sidewall 209, which is located between two adjacent channel layers 208 and on the sidewall of the second opening. The outer sidewall of the inner sidewall 209 is perpendicular to the sidewall of the channel layer 208. A source / drain layer 212 is located on the surface of the channel layer 208 on the sidewall of the first opening 206. The source / drain layer 212 covers the sidewall of the first opening 206 and has a third opening 211 between adjacent source / drain layers 212 that exposes the insulating dielectric layer. A conductive structure 219 is located within the third opening 211.

[0093] On the one hand, the source / drain layers 212 located on the sidewall of the channel layer 208 have a third opening 211 between adjacent source / drain layers 212. The source / drain layers on the sidewalls of adjacent channel layers along the first direction X are separated from each other. Therefore, defects caused by the initial nucleation surface not being a whole seed crystal and the uneven distribution of nucleation points are reduced, thereby reducing stress release in the channel caused by defects and improving device performance. On the other hand, the conductive structure 219 located in the third opening 211 is also located on the sidewall of the source / drain layer 212, so that the conductive structure 219 wraps the source / drain layer 212. Therefore, the contact area between the source / drain layer 212 and the conductive structure 219 is increased, the contact resistance is reduced, and the device performance is further improved.

[0094] In this embodiment, it further includes: a first dielectric layer 213 located on the surface of the substrate 200, the top of the source / drain layer 212, and the sidewall of the gate structure 214, wherein the first dielectric layer 213 has a fourth opening 218 (e.g., Figure 10 As shown), the fourth opening 218 is located above the third opening 211 and is connected to the third opening 211; the conductive structure 219 is also located within the fourth opening 218.

[0095] The inner wall 209 is used to isolate the gate structure 214 and the source / drain layer 212, thereby preventing the mutual diffusion of ions between the source / drain layer 212 and the gate structure 214 and improving the stability of device performance.

[0096] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Substrate; An insulating dielectric layer is located on the substrate, and a plurality of composite layers are located on a portion of the surface of the insulating dielectric layer. The composite layers extend along a first direction and have a first opening that exposes the insulating dielectric layer. The composite layers include a plurality of vertically overlapping channel layers and a second opening located between two adjacent channel layers, the second opening suspending the adjacent channel layers. A gate structure is located on the surface of the channel layer and surrounds the channel layer in a ring shape. The composite layer also includes an inner sidewall, which is located between two adjacent channel layers and on the second opening sidewall. The outer sidewall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. A source / drain layer is located on the surface of the channel layer on the sidewall of the first opening, the source / drain layer covers the sidewall of the first opening, and the source / drain layers on the sidewalls of adjacent channel layers along the first direction are separated from each other, and there is a third opening between adjacent source / drain layers that exposes the insulating dielectric layer. A conductive structure located within the third opening, the conductive structure enveloping the source / drain layer, and the conductive structure providing compressive stress to the channel layer.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: A first dielectric layer is located on the surface of the substrate, on top of the source / drain layer, and on the sidewall of the gate structure. The first dielectric layer has a fourth opening, which is located above and communicates with the third opening. The conductive structure is also located within the fourth opening.

3. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; An insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layer are formed on the substrate. The initial composite layer extends along a first direction. A first opening is located in the initial composite layer on both sides of the dummy gate structure, and the first opening exposes the insulating dielectric layer. The dummy gate structure is located on the sidewall and top surface of the initial composite layer. The dummy gate structure includes a dummy gate layer. The initial composite layer includes a plurality of vertically overlapping channel layers, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer. The outer sidewall of the inner sidewall is perpendicular to the sidewall of the channel layer. A source / drain layer is formed on the surface of the channel layer on the first opening sidewall using a selective epitaxial growth process until the source / drain layer covers the first opening sidewall, and the source / drain layers on the adjacent channel layer sidewalls along the first direction are separated from each other, with a third opening between the adjacent source / drain layers exposing the insulating dielectric layer. A conductive structure is formed within the third opening, such that the conductive structure encloses the source / drain layer, and the conductive structure provides compressive stress to the channel layer.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, Before forming the conductive structure and after forming the source / drain layer, the method further includes: forming an interlayer dielectric material layer on the substrate, the interlayer dielectric material layer being located within the third opening and on the sidewall and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed to form a first dielectric layer; removing the dummy gate layer to form a gate opening within the first dielectric layer; removing the sacrificial layer exposed by the gate opening to form a second opening between adjacent channel layers, forming a composite layer with the initial composite layer; and forming a gate structure within the gate opening and the second opening.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, After forming the gate structure and before forming the conductive structure, the method further includes: forming a fourth opening in the first dielectric layer, the fourth opening being located above the third opening and communicating with the third opening; forming a first sidewall on the sidewall of the fourth opening; and using the first sidewall as a mask to remove the first dielectric layer in the third opening, thereby exposing the third opening.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The process for removing the first dielectric layer within the third opening includes one or a combination of dry etching and wet etching.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for removing the first dielectric layer within the third opening includes a dry etching process; the process parameters of the dry etching process include: using asynchronous pulsed plasma with a pressure range of 3 mTorr to 20 mTorr, and the etching gas including fluorocarbon, wherein the carbon and fluorine composition ratio ranges from 1:2 to 1:

6.

8. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before forming the fourth opening, a second dielectric layer is also formed on the surface of the first dielectric layer and the gate structure; the fourth opening is also located within the second dielectric layer; the method for forming the fourth opening includes: forming a first mask layer on the surface of the second dielectric layer, the first mask layer exposing a portion of the surface of the second dielectric layer on the third opening; using the first mask layer as a mask, etching the second dielectric layer and the first dielectric layer until the bottom of the fourth opening is at a target size from the top surface of the source / drain layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, The target size ranges from 5 angstroms to 100 angstroms.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The conductive structure is also located within the fourth opening; The method for forming the conductive structure includes: forming a conductive material layer inside the third opening, inside the fourth opening, and on the top surface of the second dielectric layer; The conductive material layer is planarized until the top surface of the second dielectric layer is exposed.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for forming the conductive structure includes: a metal material growth process and an annealing process following the metal material growth process.

12. The method for forming a semiconductor structure as described in claim 3, characterized in that, The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process after forming the material film.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.

14. The method for forming a semiconductor structure as described in claim 3, characterized in that, The method for forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure includes: forming a first sacrificial material layer on the surface of a substrate, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer comprising a plurality of vertically overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a second mask layer on the surface of the initial composite material layer, the second mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the second mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers, the composite material layers extending along the first direction; forming the plurality of... A pseudo-gate structure is provided, wherein the pseudo-gate structure is located on a portion of the sidewall and surface of the composite material layer; using the pseudo-gate structure as a mask, the composite material layer is etched until the first sacrificial material layer is exposed, forming the first opening in the composite material layer; a transition sacrificial layer is formed with the second sacrificial material layer, and the channel layer is formed with the channel material layer; after forming the first opening, the first sacrificial material layer is removed to form an insulating trench on the surface of the substrate; an insulating dielectric layer is formed in the insulating trench; after forming the insulating dielectric layer, the transition sacrificial layer is etched to form the sacrificial layer and a fifth opening located on the sidewall of the sacrificial layer between two adjacent channel layers; and the inner sidewall is formed in the fifth opening.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; and etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The first sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the first sacrificial material layer is in the range of 1:10 to 1:2; the second sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the second sacrificial material layer is in the range of 2:5 to 7:

10. The material of the channel material layer includes silicon.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The etching process for removing the first sacrificial material layer has a selection ratio of 10:1 to 150:1 for the first sacrificial material layer and the second sacrificial material layer.

18. The method for forming a semiconductor structure as described in claim 14, characterized in that, The substrate has a well region containing a first doped ion; before forming the first sacrificial material layer, a second doped ion is implanted on the surface of the substrate, the second doped ion having a different conductivity type than the first doped ion.

19. The method for forming a semiconductor structure as described in claim 14, characterized in that, The method for forming the insulating dielectric layer includes: forming a first dielectric material layer in the insulating trench, the first dielectric material layer also being located on the first opening sidewall and on the sidewall and top surface of the dummy gate structure; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure and the first opening sidewall are exposed.

20. The method for forming a semiconductor structure as described in claim 19, characterized in that, The etching process for the first dielectric material layer includes inductively coupled plasma etching or capacitively coupled plasma etching.

21. The method for forming a semiconductor structure as described in claim 19, characterized in that, The formation process of the first dielectric material layer includes atomic layer deposition.

Images