Semiconductor structure and method of forming the same
By performing plasma and thermal treatment on the initial seed layer, a high-quality source/drain layer is formed. Combined with the inner sidewall design, the performance degradation problem caused by defects in all-around gate devices at small scales is solved, thereby improving the device's performance and speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SEMICON MFG INT (SHANGHAI) CORP
- Filing Date
- 2021-09-29
- Publication Date
- 2026-05-26
AI Technical Summary
The performance of existing gate-all-around devices needs improvement, especially as transistor sizes shrink to below a few nanometers. Defects in the source and drain layers cause stress release in the channel, affecting device performance.
By plasma processing the initial seed layer, a seed layer is formed on the surface of the channel layer and the sacrificial layer. After heat treatment, a high-quality source/drain layer is formed. Combined with the design of the inner sidewall, the contact area between the source/drain layer and the conductive structure is increased and defects are reduced.
It improves device performance, reduces stress release in the channel due to defects, enhances the contact area between the source/drain layer and the conductive structure, reduces contact resistance, and increases the speed of PMOS devices.
Smart Images
Figure CN115881815B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] In the current semiconductor field, the FinFET (Fin Field-Effect Transistor) is an emerging multi-gate device. Compared with planar metal-oxide-semiconductor field-effect transistors (MOSFETs), FinFETs have stronger short-channel rejection and higher operating current, and are now widely used in various semiconductor devices. However, with the further development of semiconductor technology, the transistor size has shrunk to below a few nanometers. The size of FinFETs themselves has already reached its limit. Limitations in fin spacing, short-channel effect, leakage current, and materials have made transistor manufacturing precarious, and even the physical structure cannot be completed.
[0003] Gate-all-around (GAA) devices have become a new direction for research and development in the industry. This technology is characterized by the gate completely surrounding the channel on all four sides. The source and drain no longer contact the substrate; instead, multiple source and drain electrodes, arranged laterally and perpendicularly to the gate in linear (rod-like), planar, or sheet-like shapes, are used to achieve the basic structure and function of a MOSFET. This design largely solves various problems caused by reducing the gate spacing, including capacitance effects. Furthermore, since the channel is surrounded by the gate on all four sides, the channel current flows more smoothly than with the three-sided enclosure of a FinFET.
[0004] However, the performance of existing gate-all-around devices needs further improvement. Summary of the Invention
[0005] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of semiconductor structures.
[0006] To solve the above-mentioned technical problems, the present invention provides a semiconductor structure comprising: a substrate; an insulating dielectric layer on the substrate; a plurality of composite layers located on a portion of the surface of the insulating dielectric layer, the composite layers extending along a first direction, the composite layers having a first opening that exposes the insulating dielectric layer, the composite layers including a plurality of vertically overlapping channel layers and a second opening located between two adjacent channel layers, the second opening suspending the adjacent channel layers; a gate structure located on the surface of the channel layers and annularly surrounding the channel layers; an inner sidewall located between two adjacent channel layers and located on the sidewall of the second opening, the outer sidewall of the inner sidewall being recessed relative to the sidewall of the channel layers, or the outer sidewall of the inner sidewall sharing a vertical plane with the sidewall of the channel layers; a seed layer located on the surface of the channel layers on the sidewall of the first opening and on the surface of the inner sidewall; and a source / drain layer located on the surface of the seed layer.
[0007] Optionally, it may also include: a conductive structure located on the source / drain layer.
[0008] Optionally, the source / drain layer has a third opening, and the third opening exposes the insulating dielectric layer; the conductive structure is also located within the third opening.
[0009] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layers on the substrate, wherein the initial composite layers extend along a first direction, and the initial composite layers on both sides of the dummy gate structure have first openings that expose the insulating dielectric layer, the dummy gate structure is located on the sidewalls and top surface of the initial composite layers, the dummy gate structure includes a dummy gate layer, and the initial composite layers include a plurality of vertical... The system comprises an overlapping channel layer, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer. The outer sidewall of the inner sidewall is recessed relative to the sidewall of the channel layer, or the outer sidewall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. An initial seed layer is formed on the surface of the channel layer on the first opening sidewall using a selective epitaxial growth process. Each initial seed layer is discrete from the others. The initial seed layers are subjected to plasma treatment to form seed layers on the surface of the sacrificial layer and the surface of the inner sidewall. A source / drain layer is formed on the surface of the seed layer using the seed layer as a seed.
[0010] Optionally, it also includes forming a conductive structure on the source / drain layer.
[0011] Optionally, before forming the conductive structure and after forming the source / drain layer, the method further includes: forming an interlayer dielectric material layer on the substrate and the surface of the source / drain layer, the dielectric material layer also being located on the sidewalls and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed, thereby forming an interlayer dielectric layer.
[0012] Optionally, after forming the interlayer dielectric layer and before forming the conductive structure, the method further includes: removing the dummy gate layer and forming a gate opening within the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening to form a second opening between adjacent channel layers, the second opening suspending adjacent channel layers, forming a composite layer with the initial composite layer, the composite layer including a plurality of vertically overlapping channel layers and the second opening located between two adjacent channel layers; and forming a gate structure within the gate opening and the second opening.
[0013] Optionally, the method for forming the conductive structure includes: forming a fourth opening within the interlayer dielectric layer, the fourth opening exposing the top surface of the source / drain layer; and forming the conductive structure within the fourth opening.
[0014] Optionally, the source / drain layer has a third opening that exposes the insulating dielectric layer.
[0015] Optionally, the source / drain layer formation process includes the selective epitaxial growth process; the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process after forming the material film.
[0016] Optionally, the process parameters of the etching process include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
[0017] Optionally, the method for forming the conductive structure includes: forming a fourth opening within the interlayer dielectric layer, the fourth opening exposing the surface of the interlayer dielectric layer within the third opening; removing the interlayer dielectric layer within the third opening to expose the third opening; and forming the conductive structure within the third opening and the fourth opening.
[0018] Optionally, the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film.
[0019] Optionally, the process parameters of the etching process include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
[0020] Optionally, the method for forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure includes: forming a first sacrificial material layer on the substrate surface, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer including a plurality of vertically overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a second mask layer on the surface of the initial composite material layer, the second mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the second mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers extending along the first direction; forming a structure spanning the composite material layers. A plurality of dummy gate structures are provided, the dummy gate structures being located on the sidewalls and surface of a portion of the composite material layer; the composite material layer is etched using the dummy gate structures as a mask until the first sacrificial material layer is exposed, the first opening is formed in the composite material layer, the second sacrificial material layer is used as a transition sacrificial layer, and the channel material layer is used as a channel layer; after the first opening is formed, the first sacrificial material layer is removed to form an insulating trench on the surface of the substrate; the insulating dielectric layer is formed in the insulating trench; after the insulating dielectric layer is formed, the transition sacrificial layer is etched to form the sacrificial layer and a fifth opening located on the sidewall of the sacrificial layer between two adjacent channel layers; the inner sidewall is formed in the fifth opening.
[0021] Optionally, the outer wall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. The method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed, and forming the inner sidewall inside the fifth opening.
[0022] Optionally, the outer wall of the inner sidewall is recessed relative to the sidewall of the channel layer. The method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed, forming an initial inner sidewall inside the fifth opening; and etching back the initial inner sidewall until the sidewall of the initial inner sidewall is recessed relative to the sidewall of the channel layer.
[0023] Optionally, the process of re-etching the initial inner wall includes multiple dry etching processes, each of which includes: oxidizing the surface of the inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film.
[0024] Optionally, the oxidation process includes a plasma treatment process; the process gas of the plasma treatment process includes a plasma mixture of argon, oxygen and helium.
[0025] Optionally, the etching process is a pulsed laser process, and the process gas of the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.
[0026] Optionally, the material of the first sacrificial material layer includes germanium and silicon, wherein the ratio of germanium to silicon in the first sacrificial material layer ranges from 1:10 to 1:2; the material of the second sacrificial layer includes germanium and silicon, wherein the ratio of germanium to silicon in the second sacrificial material layer ranges from 2:5 to 7:10; and the material of the channel material layer includes silicon.
[0027] Optionally, the method for forming the insulating dielectric layer includes: forming a first dielectric material layer on the substrate surface and within the insulating trench, the first dielectric material layer also being located on the first opening sidewall and on the dummy gate structure sidewall and top surface; etching the first dielectric material layer until the dummy gate structure sidewall and top surface, as well as the first opening sidewall, are exposed.
[0028] Optionally, the plasma processing technology includes one of remote plasma technology, inductively coupled plasma etching technology, or capacitively coupled plasma etching technology.
[0029] Optionally, the process parameters of the plasma treatment process include: a pressure range of 100 mTorr to 500 mTorr, a temperature range of 200 degrees Celsius to 600 degrees Celsius, and the plasma gas including hydrogen or argon, with an argon flow rate of less than 60 standard milliliters per minute.
[0030] Optionally, after the plasma treatment process and before forming the source / drain layer, the seed crystal layer is further subjected to heat treatment; the process parameters of the heat treatment process include a temperature range of 300 degrees Celsius to 900 degrees Celsius.
[0031] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0032] In the semiconductor structure formation method provided by the present invention, the initial seed layer is subjected to plasma treatment to form a seed layer on the surface of the sacrificial layer and the surface of the channel layer. Using the seed layer as a seed, a source / drain layer is formed on the surface of the seed layer. The seed layer helps to improve the quality of the formed source / drain layer, reduce defects such as voids in the source / drain layer, and thus reduce stress release in the channel caused by defects, thereby improving the performance of the device.
[0033] Furthermore, after the plasma treatment process and before forming the source / drain layer, the seed crystal layer is also subjected to heat treatment. This heat treatment helps to reduce defects in the seed crystal layer, improve the quality of the seed crystal layer, and thus improve the quality of the subsequently formed source / drain layer.
[0034] Furthermore, the source / drain layer has a third opening that exposes the insulating dielectric layer; the conductive structure is also located within the third opening. On one hand, by having the conductive structure enclose the source / drain layer, the contact area between the source / drain layer and the conductive structure is increased, the contact resistance is reduced, and the device performance is further improved. On the other hand, the annealing process used during the formation of the conductive structure causes a change in the volume of the conductive structure, resulting in compressive stress on the channel. This compressive stress can reduce the effective conductivity mass of holes in the channel direction of the PMOS device, thereby increasing the speed of the PMOS device.
[0035] In the semiconductor structure provided by the present invention, a seed layer is located on the inner wall surface and the channel layer surface; a source / drain layer is located on the surface of the seed layer. The presence of the seed layer helps to improve the quality of the formed source / drain layer, reduce defects such as voids in the source / drain layer, and thus reduce stress release in the channel caused by defects, thereby improving the performance of the device.
[0036] Furthermore, the source / drain layer has a third opening that exposes the insulating dielectric layer, and the conductive structure is located within the third opening, thereby enveloping the source / drain layer. This increases the contact area between the source / drain layer and the conductive structure, reduces the contact resistance, and further improves the device performance. Attached Figure Description
[0037] Figures 1 to 3 This is a schematic cross-sectional view of the semiconductor structure formation process;
[0038] Figures 4 to 14 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention;
[0039] Figures 15 to 17This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to another embodiment of the present invention. Detailed Implementation
[0040] As described in the background section, the performance of semiconductor devices formed in the prior art needs improvement. The following analysis will illustrate this with reference to the structure of a semiconductor.
[0041] Figures 1 to 3 This is a cross-sectional schematic diagram of the semiconductor structure formation process.
[0042] Please refer to Figure 1 A substrate 100 is provided; an insulating dielectric layer 101, a plurality of composite layers on a portion of the surface of the insulating dielectric layer 101, and a gate structure on the surface of the composite layer are formed on the substrate 100. The gate structure includes a gate layer 104 and a protective layer 105 on the surface of the gate layer. The composite layer includes a plurality of vertically overlapping sacrificial layers 102 and a channel layer 103 located between two adjacent sacrificial layers 102.
[0043] Please refer to Figure 3 Source / drain layers 107 are formed on the substrates 100 on both sides of the composite layer, and the source / drain layers 107 are located on the sidewall surface of the channel layer 103.
[0044] The above method is used in GAA device structures, where the insulating dielectric layer 101 is used to isolate the channel layer of the device from the substrate to reduce the leakage current of the formed device. The method for forming the source / drain layer 107 includes: forming an epitaxial layer on the sidewall of the channel layer 103 by epitaxial growth technology; and implanting dopant ions into the epitaxial layer. Figure 2 The diagram shows the distribution of epitaxial material 106 on the sidewalls of the channel layer 103 during the initial formation of the source / drain layer 107. Since the substrate surface 100 is covered by the insulating dielectric layer 101, the epitaxial material can only grow from the surface of the sidewalls of the channel layer 103. Ultimately, the epitaxial materials on adjacent sidewalls of the channel layer 103 along the channel direction merge and connect, and the epitaxial materials on adjacent sidewalls of the channel layer 103 along the substrate normal direction merge and connect, thereby forming the source / drain layer 107.
[0045] Because the channel layers 103 are discretely separated along the substrate normal, the source / drain layers 107 use the sidewalls of the channel layers 103 as initial nucleation surfaces. Since the initial nucleation surfaces are not a single seed crystal and the nucleation points are unevenly distributed, a large number of defects are generated within the final source / drain layers 107. For example... Figure 3As shown, the epitaxial material layer interface of adjacent channel layer 103 sidewalls along the channel direction is relatively rough, making it prone to defects such as voids; this is referred to as vertical defect B. Conversely, the epitaxial material layer interface of adjacent channel layer 103 sidewalls along the substrate normal direction is also relatively rough, making it prone to defects such as voids; this is referred to as horizontal defect A. Both horizontal defect A and vertical defect B cause stress release due to these defects, affecting the stress within the channel layer 103 and further impacting the mobility of electrons or holes within the channel, thus reducing device performance.
[0046] To address the aforementioned problems, this invention provides a semiconductor structure formation method. The initial seed layer is subjected to plasma treatment to form a seed layer on the surface of the sacrificial layer and the surface of the channel layer. Using the seed layer as a seed, a source / drain layer is formed on the surface of the seed layer. The seed layer helps improve the quality of the formed source / drain layer, reduces defects such as voids within the source / drain layer, and thus reduces stress release in the channel caused by defects, thereby improving device performance.
[0047] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0048] Figures 4 to 14 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to an embodiment of the present invention.
[0049] Please refer to Figure 4 and Figure 5 , Figure 4 for Figure 5 A top-view structural diagram. Figure 5 for Figure 4 A schematic diagram of the cross-sectional structure along the DD1 direction is provided, showing the substrate 200.
[0050] In this embodiment, the substrate 200 is made of monocrystalline silicon; in other embodiments, the substrate may also be a semiconductor material such as polycrystalline silicon, germanium, silicon germanide, gallium arsenide, silicon-on-insulator, or germanium-on-insulator.
[0051] In this embodiment, the substrate has a well region (not shown in the figure), and the well region contains a first dopant ion. Specifically, in this embodiment, the first dopant ion is an N-type ion, used to form the well region of a PMOS device. In other embodiments, the first dopant ion is a P-type ion, used to form the well region of an NMOS device.
[0052] Subsequently, an insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layers are formed on the substrate 200. The initial composite layers extend along a first direction, and each initial composite layer on both sides of the dummy gate structure has a first opening that exposes the insulating dielectric layer. The dummy gate structure is located on the sidewalls and top surface of the initial composite layers. The dummy gate structure includes a dummy gate layer. The initial composite layers include a plurality of vertically overlapping channel layers, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer. The outer sidewall of the inner sidewall is recessed relative to the sidewall of the channel layer, or the outer sidewall of the inner sidewall is perpendicular to the sidewall of the channel layer. For the method of forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure, please refer to [reference needed]. Figures 4 to 9 .
[0053] Please continue to refer to this. Figures 4 to 5 A first sacrificial material layer 201 is formed on the surface of the substrate 200, and an initial composite material layer (not shown in the figure) is formed on the surface of the first sacrificial material layer 201. The initial composite material layer includes several vertically overlapping channel material layers (not shown in the figure) and a second sacrificial material layer (not shown in the figure) located between two adjacent channel layers. A second mask layer (not shown in the figure) is formed on the surface of the initial composite material layer, and the second mask layer exposes a portion of the initial composite material layer. The initial composite material layer is etched using the second mask layer as a mask until the surface of the first sacrificial material layer 201 is exposed, forming several composite material layers 202, which extend along the first direction X. Several dummy gate structures 203 are formed across the composite material layers 202, and the dummy gate structures 203 are located on a portion of the sidewalls and surface of the composite material layers 202.
[0054] The first direction X is the channel direction.
[0055] The dummy gate structure 203 includes a dummy gate layer 204. In this embodiment, the dummy gate structure 203 further includes a protective layer 205 located on the surface of the dummy gate layer 204.
[0056] The first sacrificial material layer 201 occupies space for the subsequent formation of the insulating dielectric layer.
[0057] In this embodiment, before forming the first sacrificial material layer 201, a second dopant ion is implanted onto the surface of the substrate 200. The second dopant ion has a different conductivity type than the first dopant ion. Specifically, the second dopant ion is a p-type ion.
[0058] The material of the second sacrificial material layer is different from that of the channel material layer. The channel material layer is used to form the channel layer, and the second sacrificial material layer is used to form the second sacrificial layer subsequently. The second sacrificial layer occupies space for the subsequent formation of the gate structure and will be removed later. The material of the second sacrificial material layer has a higher etch selectivity than the material of the channel material layer, so that the subsequent removal of the second sacrificial layer has less impact on the channel layer; the material of the second sacrificial material layer has better lattice matching than the material of the channel material layer, so as to obtain a smooth interface between the second sacrificial layer and the channel layer, making the surface of the subsequently formed channel layer flat, which is conducive to obtaining a device with good performance.
[0059] The material of the second sacrificial material layer includes silicon; the material of the channel material layer includes germanium-silicon. In this embodiment, the material of the channel material layer is silicon; the material of the second sacrificial material layer is germanium-silicon. In other embodiments, the channel material layer is Ge or GeSi. In other embodiments, the material of the second sacrificial material layer can be ZnS, ZnSe, BeS, or GaP, etc.
[0060] Please refer to Figure 6 and Figure 7 , Figure 6 for Figure 7 A top-view structural diagram. Figure 7 for Figure 6 A cross-sectional view along the DD1 direction is shown. Using the pseudo gate structure 203 as a mask, the composite material layer 202 is etched until the first sacrificial material layer 201 is exposed. The first opening 206 is formed in the composite material layer 202. The second sacrificial material layer forms the transition sacrificial layer 207. The channel layer 208 is formed with the channel material layer.
[0061] The material of the first sacrificial material layer 201 is different from the material of the second sacrificial material layer. The sacrificial layer is formed by the second sacrificial material layer. Therefore, the material of the first sacrificial material layer 201 is different from the material of the second sacrificial material layer, and the material of the first sacrificial material layer is different from that of the substrate 200. This allows for the selection of an etching process with a larger etching selectivity between the first sacrificial material layer 201 and the second sacrificial material layer, and between the first sacrificial material layer 201 and the substrate 200, when removing the first sacrificial material layer 201, thereby reducing etching damage to the sacrificial layer and the substrate 200.
[0062] The first sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 1:10 to 1:2. The second sacrificial material layer comprises germanium and silicon, with a germanium to silicon composition ratio ranging from 2:5 to 7:10. The channel material layer comprises silicon. The germanium and silicon composition ranges in the first and second sacrificial material layers are different to ensure that the first sacrificial material layer 201 has a larger etching selectivity relative to the second sacrificial layer during the etching process.
[0063] Please continue to refer to this. Figure 6 and Figure 7 After forming the first opening 206, the first sacrificial material layer 201 is removed to form an insulating groove (not shown in the figure) on the surface of the substrate 200; the insulating dielectric layer 209 is formed in the insulating groove.
[0064] The method for forming the insulating dielectric layer 209 includes: forming a first dielectric material layer (not shown in the figure) on the surface of the substrate 200 and in the insulating trench, the first dielectric material layer being located on the sidewall of the first opening 206, and on the sidewall and top surface of the dummy gate structure 203; etching the first dielectric material layer until the sidewall and top surface of the dummy gate structure 203 and the sidewall of the first opening 206 are exposed.
[0065] The etching process for the first dielectric material layer includes inductively coupled plasma etching or capacitively coupled plasma etching.
[0066] The formation process of the first dielectric material layer includes atomic layer deposition (ALD). ALD facilitates the formation of a uniform first dielectric material layer and has excellent trench filling capability, thereby improving the performance of the insulating dielectric layer 209.
[0067] The etching process for removing the first sacrificial material layer has a selection ratio of 10:1 to 150:1 for the first sacrificial material layer and the second sacrificial material layer.
[0068] Subsequently, an initial seed layer is formed on the surface of the channel layer 208 on the sidewall of the first opening 206 using a selective epitaxial growth process, with each initial seed layer being separate from the others.
[0069] Please refer to Figure 8 and Figure 9 , Figure 8 for Figure 9 A top-view structural diagram. Figure 9 for Figure 8A cross-sectional structural diagram along the DD1 direction is shown. After the insulating dielectric layer 209 is formed, the transition sacrificial layer 207 is etched. The sacrificial layer 300 and a fifth opening (not shown in the figure) located on the sidewall of the sacrificial layer are formed between the two adjacent channel layers 208. The inner sidewall 210 is formed in the fifth opening.
[0070] In this embodiment, the outer sidewall of the inner sidewall 210 is recessed relative to the sidewall of the channel layer 208. The method for forming the inner sidewall 210 includes: forming a second dielectric material layer (not shown in the figure) on the surface of the insulating dielectric layer 209, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure 203, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer 209, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure 203, and the top surface are exposed, forming an initial inner sidewall (not shown in the figure) inside the fifth opening; etching back the initial inner sidewall until the sidewall of the initial inner sidewall is recessed relative to the sidewall of the channel layer 208.
[0071] The inner wall 210 is used to isolate the subsequently formed gate structure and source / drain layer, preventing the mutual diffusion of ions between the source / drain layer and the gate structure, thereby improving the stability of device performance.
[0072] In this embodiment, the process of re-etching the initial inner wall includes multiple dry etching processes. Each dry etching process includes: oxidizing the surface of the inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film. The dry etching process helps to improve the uniformity of the formed inner wall and improve the quality of the inner wall.
[0073] The oxidation process includes a plasma treatment process; the process gas for the plasma treatment process includes a plasma mixture of argon, oxygen, and helium.
[0074] The etching process is a pulsed laser process, and the process gas for the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.
[0075] In this embodiment, while re-etching the initial inner wall, the protective layer 205 is also etched, so that the protective layer 205 is thinned in the first direction X.
[0076] In another embodiment, the outer wall of the inner sidewall shares a vertical plane with the sidewall of the channel layer; the method of forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed, and forming the inner sidewall inside the fifth opening.
[0077] It should be noted here that subsequent references... Figure 10 For reference Figure 17 The view direction is the same Figure 9 .
[0078] Please refer to Figure 10 An initial seed layer 211 is formed on the surface of the channel layer 208 on the sidewall of the first opening 206 using a selective epitaxial growth process, and each of the initial seed layers 211 is independent of each other.
[0079] In this embodiment, the sidewall of the channel layer 208 protrudes relative to the inner sidewall 210, which increases the initial crystal growth area and facilitates the growth of grains along the direction of the substrate normal, thereby improving the uniformity of the seed crystal layer exposed by the subsequently formed opening 206 and thus improving the performance of the formed source and drain layers.
[0080] The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process following the formation of the material film. The selective epitaxial growth process allows the initial seed layer 211 material to grow epitaxially on the sidewall of the channel layer 208, and precisely controls the shape and size of the initial seed layer 211, thereby improving the quality of the formed initial seed layer 211.
[0081] The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
[0082] Please refer to Figure 11 The initial seed crystal layer 211 is subjected to plasma treatment to form a seed crystal layer 212 on the surface of the inner sidewall 210 and the surface of the channel layer 208.
[0083] Specifically, the seed crystal layer 212 covers the surface of the inner sidewall 210.
[0084] The plasma processing technology includes one of remote plasma technology, inductively coupled plasma etching technology, or capacitively coupled plasma etching technology.
[0085] The process parameters of the plasma treatment process include: a pressure range of 100 mTorr to 500 mTorr, a temperature range of 200 degrees Celsius to 600 degrees Celsius, and plasma gas including hydrogen or argon, with an argon flow rate of less than 60 standard milliliters per minute.
[0086] The seed layer 212 is used as a seed for the subsequent formation of the source / drain layer. The seed layer 212 helps to improve the quality of the formed source / drain layer, reduce defects such as voids in the source / drain layer, and thus reduce stress release in the channel caused by defects, thereby improving the performance of the device.
[0087] After the plasma treatment process and before the formation of the source / drain layer, the seed crystal layer 212 is also subjected to heat treatment; the process parameters of the heat treatment process include a temperature range of 300 degrees Celsius to 900 degrees Celsius.
[0088] The heat treatment helps to reduce defects in the seed layer 212, improve the quality of the seed layer 212, and thus improve the quality of the source / drain layer formed subsequently.
[0089] Please refer to Figure 12 Using the seed crystal layer 212 as the seed crystal, a source / drain layer 213 is formed on the surface of the seed crystal layer 212.
[0090] In this embodiment, the seed layer 212 fills the first opening 206, that is, the source / drain layers on the surfaces of adjacent seed layers 212 are merged along the first direction X. In this embodiment, the resulting source / drain layer structure is compatible with existing production line processes.
[0091] In another embodiment, the source / drain layer further has a third opening that exposes the insulating dielectric layer. That is, the source / drain layers on adjacent seed layer surfaces are discrete from each other along the first direction X.
[0092] Please refer to Figure 13An interlayer dielectric material layer (not shown in the figure) is formed on the substrate 200 and the surface of the source / drain layer 213. The dielectric material layer is also located on the sidewalls and top surface of the dummy gate structure 203. The interlayer dielectric material layer is planarized until the dummy gate layer 204 is exposed, forming an interlayer dielectric layer 214. After forming the interlayer dielectric layer 214, the dummy gate layer 204 is removed, and a gate opening (not shown in the figure) is formed in the interlayer dielectric layer 214. The sacrificial layer 300 exposed by the gate opening is removed, forming a second opening (not shown in the figure) between adjacent channel layers 208. The second opening suspends the adjacent channel layers 208, forming a composite layer with the initial composite layer. The composite layer includes several vertically overlapping channel layers 208 and the second opening located between two adjacent channel layers 208. A gate structure 215 is formed in the gate opening and the second opening.
[0093] The gate structure 215 includes a gate dielectric layer (not shown in the figure) located on the surface of the gate opening and the second opening, and a metal gate (not shown in the figure) on the surface of the gate dielectric layer.
[0094] In this embodiment, the planarization process also causes the protective layer 205 to form a grid sidewall 216.
[0095] Please refer to Figure 14 Conductive structures 217 are formed on the source / drain layer 213.
[0096] The method for forming the conductive structure 217 includes: forming a fourth opening (not shown in the figure) in the interlayer dielectric layer 214, the fourth opening exposing the top surface of the source / drain layer 213; and forming the conductive structure 217 in the fourth opening.
[0097] In this embodiment, before forming the fourth opening, a dielectric layer 218 is formed on the surface of the interlayer dielectric layer 214 and the surface of the gate structure, and the fourth opening is also located within the dielectric layer 218.
[0098] The method for forming the fourth opening includes: forming a mask layer (not shown in the figure) on the surface of the dielectric layer 218, the mask layer exposing part of the surface of the dielectric layer 218 on the source / drain layer 213; using the mask layer as a mask, etching the dielectric layer 218 and the interlayer dielectric layer 214 until the surface of the source / drain layer 213 is exposed.
[0099] Accordingly, one embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [the original text]. Figure 14The system includes: a substrate 200; an insulating dielectric layer 209 on the substrate 200; a plurality of composite layers on a portion of the surface of the insulating dielectric layer 209; and a gate structure 215 spanning the composite layers, wherein the composite layers extend along a first direction X and have a first opening 206 (e.g., ...). Figure 11 As shown in the figure, the first opening 206 exposes the insulating dielectric layer 209. The composite layer includes several vertically overlapping channel layers 208 and a second opening located between two adjacent channel layers 208 (as shown in the figure). The second opening suspends the adjacent channel layers 208. The gate structure 215 is located on the surface of the channel layer 208 and surrounds the channel layer 208 in an annular shape. The inner sidewall 210 is located between two adjacent channel layers 208 and on the sidewall of the second opening. The outer sidewall of the inner sidewall 210 is recessed relative to the sidewall of the channel layer 208, or the outer sidewall of the inner sidewall is perpendicular to the sidewall of the channel layer. The seed layer 212 is located on the surface of the channel layer 208 on the sidewall of the first opening 206 and on the surface of the inner sidewall 210. The source / drain layer 213 is located on the surface of the seed layer 212.
[0100] In this embodiment, the outer wall of the inner wall 210 is recessed relative to the sidewall of the channel layer 208. In another embodiment, the outer wall of the inner wall shares a vertical plane with the sidewall of the channel layer.
[0101] In this embodiment, the semiconductor structure further includes a conductive structure 217 located on the source / drain layer 213.
[0102] Figures 15 to 17 This is a schematic cross-sectional view of each step in a semiconductor structure formation method according to another embodiment of the present invention.
[0103] Please Figure 11 Based on this, continue to refer to Figure 15 The source / drain layer 301 has a third opening 302 that exposes the insulating dielectric layer 209.
[0104] In this embodiment, the formation process of the source / drain layer 301 includes the selective epitaxial growth process; the selective epitaxial growth process includes multiple film deposition processes, each of which includes: forming a material film, and an etching process after forming the material film. The selective epitaxial growth process facilitates ensuring that the materials of the source / drain layers formed on the surfaces of adjacent channel layers 208 along the first direction X are not connected, that is, the source / drain layers 301 on the surfaces of adjacent channel layers 208 are separated from each other.
[0105] The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
[0106] Subsequently, a conductive structure is formed on the source / drain layer 301, and the conductive structure is also located within the third opening 302.
[0107] Please refer to Figure 16 An interlayer dielectric material layer (not shown in the figure) is formed on the substrate 200 and the surface of the source / drain layer 301. The dielectric material layer is also located on the sidewalls and top surface of the dummy gate structure 203. The interlayer dielectric material layer is planarized until the dummy gate layer 204 is exposed, forming an interlayer dielectric layer 303. After forming the interlayer dielectric layer 303, the dummy gate layer 204 is removed, and a gate opening (not shown in the figure) is formed in the interlayer dielectric layer 303. The sacrificial layer 300 exposed by the gate opening is removed, forming a second opening (not shown in the figure) between adjacent channel layers 208. The second opening suspends the adjacent channel layers 208, forming a composite layer with the initial composite layer. The composite layer includes several vertically overlapping channel layers 208 and the second opening located between two adjacent channel layers 208. A gate structure 304 is formed in the gate opening and the second opening.
[0108] Specifically, the dielectric material layer is also located within the third opening 302. Subsequently, the dielectric material layer within the third opening 302 needs to be removed to expose the third opening 302, thereby forming a conductive structure within the third opening 302.
[0109] In this embodiment, the protective layer 205 is etched to form a gate sidewall 305 during the planarization process.
[0110] Please refer to Figure 17 A conductive structure 307 is formed on the source / drain layer 303.
[0111] The method for forming the conductive structure 307 includes: forming a fourth opening (not shown in the figure) in the interlayer dielectric layer 303, the fourth opening exposing the surface of the interlayer dielectric layer 303 in the third opening 302; removing the interlayer dielectric layer 303 in the third opening 302 to expose the third opening 302; and forming the conductive structure 307 in the third opening 302 and the fourth opening.
[0112] The conductive structure 307 is located within the third opening 302, thereby enclosing the source / drain layer 301. This increases the contact area between the source / drain layer 301 and the conductive structure 307, reduces contact resistance, and further improves device performance.
[0113] In this embodiment, before forming the fourth opening, a dielectric layer 306 is formed on the surface of the interlayer dielectric layer 214 and the surface of the gate structure, and the fourth opening is also located within the dielectric layer 306.
[0114] The method for forming the fourth opening includes: forming a mask layer (not shown in the figure) on the surface of the dielectric layer 306, the mask layer exposing part of the surface of the dielectric layer 306 on the source / drain layer 213; using the mask layer as a mask, etching the dielectric layer 306 and the interlayer dielectric layer 303 until the surface of the source / drain layer 213 is exposed.
[0115] The formation process of the conductive structure 307 includes a metal material growth process and an annealing process following the metal material growth process. During the formation of the conductive structure, the annealing process causes a change in the volume of the conductive structure, resulting in compressive stress on the channel. This compressive stress can reduce the effective conductivity mass of holes in the channel direction of the PMOS device, thereby improving the speed of the PMOS device.
[0116] Accordingly, another embodiment of the present invention also provides a semiconductor structure formed using the above method. Please refer to [link / reference needed]. Figure 17 The system includes: a substrate 200; an insulating dielectric layer 209 located on the substrate 200; and a plurality of composite layers located on a portion of the surface of the insulating dielectric layer 209, the composite layers extending along a first direction X, and each composite layer having a first opening 206 (e.g., ...). Figure 11 As shown in the figure, the first opening 206 exposes the insulating dielectric layer 209. The composite layer includes several vertically overlapping channel layers 208, a second opening (not shown) located between two adjacent channel layers 208, which suspends the adjacent channel layers 208; a gate structure 304 located on the surface of the channel layer 208 and surrounding the channel layer 208; an inner sidewall 210 located between two adjacent channel layers 208 and on the sidewall of the second opening, the outer sidewall of the inner sidewall 210 being recessed relative to the sidewall of the channel layer 208, or the outer sidewall of the inner sidewall sharing a vertical plane with the sidewall of the channel layer; a seed layer 212 located on the surface of the channel layer 208 on the sidewall of the first opening 206 and on the surface of the inner sidewall 210; and a source / drain layer 301 located on the surface of the seed layer 212.
[0117] In this embodiment, the outer wall of the inner sidewall 210 is recessed relative to the sidewall of the channel layer 208. In another embodiment, the outer wall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. The inner sidewall 210 is used to isolate the gate structure 304 and the source / drain layer 301, preventing the mutual diffusion of ions between the source / drain layer 301 and the gate structure 304, thereby improving the stability of device performance.
[0118] In this embodiment, the semiconductor structure further includes a conductive structure 307 located on the source / drain layer 301.
[0119] In this embodiment, the source / drain layer 301 has a third opening 302 (e.g., Figure 15 As shown in the diagram, the third opening 302 exposes the insulating dielectric layer 209; the conductive structure 307 is also located within the third opening 302. Because the conductive structure 307 encloses the source / drain layer 301, the contact area between the source / drain layer 301 and the conductive structure 307 is increased, the contact resistance is reduced, and the device performance is further improved.
[0120] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; An insulating dielectric layer is located on the substrate, and a plurality of composite layers are located on a portion of the surface of the insulating dielectric layer. The composite layers extend along a first direction and have a first opening that exposes the insulating dielectric layer. The composite layers include a plurality of vertically overlapping channel layers and a second opening located between two adjacent channel layers, the second opening suspending the adjacent channel layers. A gate structure is located on the surface of the channel layer and surrounds the channel layer in a ring shape. The inner wall is located between two adjacent channel layers and on the second opening sidewall. The outer wall of the inner wall is recessed relative to the channel layer sidewall, or the outer wall of the inner wall shares a vertical plane with the channel layer sidewall. A seed crystal layer is located on the surface of the channel layer on the sidewall of the first opening and on the surface of the inner wall, the seed crystal layer completely covers the surface of the inner wall and the seed crystal layer is continuous; The source / drain layer located on the surface of the seed crystal layer.
2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The conductive structure located on the source / drain layer.
3. The semiconductor structure as described in claim 2, characterized in that, The source / drain layer has a third opening, and the third opening exposes the insulating dielectric layer; the conductive structure is also located within the third opening.
4. A method for forming a semiconductor structure, characterized in that, include: Provide substrate; An insulating dielectric layer, a plurality of initial composite layers located on a portion of the surface of the insulating dielectric layer, and a dummy gate structure spanning the initial composite layers are formed on the substrate. The initial composite layers extend along a first direction. The initial composite layers on both sides of the dummy gate structure have first openings that expose the insulating dielectric layer. The dummy gate structure is located on the sidewalls and top surface of the initial composite layers. The dummy gate structure includes a dummy gate layer. The initial composite layer includes a plurality of vertically overlapping channel layers, a sacrificial layer located between two adjacent channel layers, and an inner sidewall located on the sidewall of the sacrificial layer. The outer sidewall of the inner sidewall is recessed relative to the sidewall of the channel layer, or the outer sidewall of the inner sidewall is perpendicular to the sidewall of the channel layer. An initial seed layer is formed on the surface of the channel layer on the sidewall of the first opening using a selective epitaxial growth process, and each of the initial seed layers is independent of the others; The initial seed crystal layer is subjected to plasma treatment to form a seed crystal layer on the inner sidewall surface and the channel layer surface, and the seed crystal layer covers the inner sidewall surface. Using the seed crystal layer as a seed crystal, a source / drain layer is formed on the surface of the seed crystal layer.
5. The method for forming a semiconductor structure as described in claim 4, characterized in that, Also includes: A conductive structure is formed on the source / drain layer.
6. The method for forming a semiconductor structure as described in claim 5, characterized in that, Before forming the conductive structure and after forming the source / drain layer, the method further includes: forming an interlayer dielectric material layer on the substrate and the surface of the source / drain layer, the dielectric material layer also being located on the sidewalls and top surface of the dummy gate structure; planarizing the interlayer dielectric material layer until the dummy gate layer is exposed, thereby forming an interlayer dielectric layer.
7. The method for forming a semiconductor structure as described in claim 6, characterized in that, After forming the interlayer dielectric layer and before forming the conductive structure, the method further includes: removing the dummy gate layer and forming a gate opening within the interlayer dielectric layer; removing the sacrificial layer exposed by the gate opening to form a second opening between adjacent channel layers, the second opening suspending adjacent channel layers, forming a composite layer with the initial composite layer, the composite layer including a plurality of vertically overlapping channel layers and the second opening located between two adjacent channel layers; and forming a gate structure within the gate opening and the second opening.
8. The method for forming a semiconductor structure as described in claim 6, characterized in that, The method for forming the conductive structure includes: forming a fourth opening within the interlayer dielectric layer, the fourth opening exposing the top surface of the source / drain layer; and forming the conductive structure within the fourth opening.
9. The method for forming a semiconductor structure as described in claim 6, characterized in that, The source / drain layer has a third opening that exposes the insulating dielectric layer.
10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The process for forming the source / drain layer includes the selective epitaxial growth process; the selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process after forming the material film.
11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
12. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the conductive structure includes: forming a fourth opening in the interlayer dielectric layer, the fourth opening exposing the surface of the interlayer dielectric layer in the third opening; removing the interlayer dielectric layer in the third opening to expose the third opening; and forming the conductive structure in the third opening and the fourth opening.
13. The method for forming a semiconductor structure as described in claim 4, characterized in that, The selective epitaxial growth process includes multiple film formation processes, each of which includes: forming a material film, and an etching process after forming the material film.
14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The etching process parameters include: etching gas including hydrogen chloride or chlorine, etching temperature range of 100 degrees Celsius to 450 degrees Celsius, and pressure range of 5 millitor to 15 millitor.
15. The method for forming a semiconductor structure as described in claim 4, characterized in that, The method for forming the insulating dielectric layer, the plurality of initial composite layers, and the dummy gate structure includes: forming a first sacrificial material layer on the surface of the substrate, and an initial composite material layer on the surface of the first sacrificial material layer, the initial composite material layer including a plurality of vertically overlapping channel material layers and a second sacrificial material layer located between two adjacent channel layers; forming a second mask layer on the surface of the initial composite material layer, the second mask layer exposing a portion of the initial composite material layer; etching the initial composite material layer using the second mask layer as a mask until the surface of the first sacrificial material layer is exposed, forming a plurality of composite material layers, the composite material layers extending along the first direction; forming a plurality of composite material layers spanning the composite material layers. A pseudo-gate structure is provided, wherein the pseudo-gate structure is located on the sidewall and surface of a portion of the composite material layer; using the pseudo-gate structure as a mask, the composite material layer is etched until the first sacrificial material layer is exposed, forming the first opening within the composite material layer, using the second sacrificial material layer as a transition sacrificial layer, and using the channel material layer as a channel layer; after forming the first opening, the first sacrificial material layer is removed to form an insulating trench on the substrate surface; an insulating dielectric layer is formed within the insulating trench; after forming the insulating dielectric layer, the transition sacrificial layer is etched to form the sacrificial layer and a fifth opening located on the sidewall of the sacrificial layer between two adjacent channel layers; and an inner sidewall is formed within the fifth opening.
16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The outer wall of the inner sidewall shares a vertical plane with the sidewall of the channel layer. The method for forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed, and forming the inner sidewall inside the fifth opening.
17. The method for forming a semiconductor structure as described in claim 15, characterized in that, The outer wall of the inner sidewall is recessed relative to the sidewall of the channel layer. The method of forming the inner sidewall includes: forming a second dielectric material layer on the surface of the insulating dielectric layer, inside the fifth opening, on the surface of the initial composite layer sidewall, on the sidewall of the dummy gate structure, and on the top surface; etching back the second dielectric material layer until the surface of the insulating dielectric layer, the surface of the initial composite layer sidewall, the sidewall of the dummy gate structure, and the top surface are exposed, forming an initial inner sidewall inside the fifth opening; and etching back the initial inner sidewall until the sidewall of the initial inner sidewall is recessed relative to the sidewall of the channel layer.
18. The method for forming a semiconductor structure as described in claim 17, characterized in that, The process of re-etching the initial inner wall includes multiple dry etching processes. Each dry etching process includes: oxidizing the surface of the inner wall to form an oxide film on the surface of the initial inner wall; and etching away the oxide film.
19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The oxidation process includes a plasma treatment process; the process gas for the plasma treatment process includes a plasma mixture of argon, oxygen, and helium.
20. The method for forming a semiconductor structure as described in claim 18, characterized in that, The etching process is a pulsed laser process, and the process gas for the pulsed laser process includes fluorinated carbon or hydrofluoric carbon gas.
21. The method for forming a semiconductor structure as described in claim 15, characterized in that, The first sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the first sacrificial material layer is in the range of 1:10 to 1:2; the second sacrificial material layer is made of germanium-silicon, and the ratio of germanium to silicon in the second sacrificial material layer is in the range of 2:5 to 7:
10. The material of the channel material layer includes silicon.
22. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the insulating dielectric layer includes: forming a first dielectric material layer on the substrate surface and in the insulating trench, the first dielectric material layer being located on the first opening sidewall and on the dummy gate structure sidewall and top surface; etching the first dielectric material layer until the dummy gate structure sidewall and top surface, as well as the first opening sidewall, are exposed.
23. The method for forming a semiconductor structure as described in claim 4, characterized in that, The plasma processing technology includes one of remote plasma technology, inductively coupled plasma etching technology, or capacitively coupled plasma etching technology.
24. The method for forming a semiconductor structure as described in claim 23, characterized in that, The process parameters of the plasma treatment process include: a pressure range of 100 mTorr to 500 mTorr, a temperature range of 200 degrees Celsius to 600 degrees Celsius, and plasma gas including hydrogen or argon, with an argon flow rate of less than 60 standard milliliters per minute.
25. The method for forming a semiconductor structure as described in claim 4, characterized in that, After the plasma treatment process and before the formation of the source / drain layer, the seed crystal layer is further subjected to heat treatment; the process parameters of the heat treatment process include a temperature range of 300 degrees Celsius to 900 degrees Celsius.