Comparator circuit with false alarm prevention mechanism and method of operation thereof

Abstract

A comparator circuit with false alarm prevention mechanism and an operating method thereof are disclosed. The operating method includes receiving a first input voltage and a second input voltage from a first input terminal and a second input terminal in an operating state by an input pair circuit. The input pair circuit and a latch circuit operate together in the operating state to compare the first input voltage and the second input voltage, and generate a first output voltage and a second output voltage at a first output terminal and a second output terminal, respectively. The latch circuit includes a first latch transistor and a second latch transistor. A gate and a drain of the first latch transistor are electrically coupled to the first and second output terminals, respectively. A gate and a drain of the second latch transistor are electrically coupled to the second output terminal and the first output terminal, respectively. A conduction adjustment circuit triggers to strengthen a conduction degree of the latch circuit when triggered. A voltage detection circuit triggers the conduction adjustment circuit when the first output voltage and the second output voltage are not in a default range.

Description

TECHNICAL FIELD

[0001] The present invention relates to comparator technology, and more particularly, to a comparator circuit with false alarm prevention mechanism and its operating method. BACKGROUND

[0002] In modern electronic technology, many comparator circuits have been developed to compare two analog input signals and generate a digital output signal. The digital output signal represents the comparison result of which analog input signal is greater. Comparator circuits are commonly used as non-linear circuits to digitize analog signals, and can be combined with a latch circuit to store the value of the digital output signal.

[0003] However, the latch circuit uses the output terminal to generate the comparison result initially in a transient state and then in a stable state after a period of time. If the time from the transient state to the stable state is too long, it will easily lead to false alarm results. SUMMARY

[0004] In view of the problems of the prior art, one object of the present invention is to provide a comparator circuit with false alarm prevention mechanism and its operating method to improve the prior art.

[0005] The present invention comprises a comparator circuit with false alarm prevention mechanism, comprising: an input pair circuit, a latch circuit, a conduction adjustment circuit, and a voltage detection circuit. The input pair circuit corresponds to a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and is configured to receive a first input voltage and a second input voltage from the first input terminal and the second input terminal, respectively, in an operating state. The input pair circuit and the latch circuit operate together in the operating state to compare the first input voltage and the second input voltage, and generate a first output voltage and a second output voltage at the first output terminal and the second output terminal, respectively. The latch circuit comprises: a first latch transistor and a second latch transistor. The first latch transistor has a gate electrically coupled to the first output terminal and a drain electrically coupled to the second output terminal. The second latch transistor has a gate electrically coupled to the second output terminal and a drain electrically coupled to the first output terminal. The conduction adjustment circuit is configured to strengthen the conduction degree of the latch circuit when triggered. The voltage detection circuit is configured to detect the first output voltage and the second output voltage, and to trigger the conduction adjustment circuit when the first output voltage and the second output voltage are not in a default range.

[0006] The present application also includes a comparator circuit operation method with false alarm prevention mechanism, comprising: making an input pair circuit receive a first input voltage and a second input voltage from a first input terminal and a second input terminal respectively in an operation state; making the input pair circuit and a latch circuit operate together in the operation state to compare the first input voltage and the second input voltage, and generate a first output voltage and a second output voltage at a first output terminal and a second output terminal respectively, wherein the latch circuit comprises a first latch transistor and a second latch transistor, the first latch transistor has a gate electrically coupled to the first output terminal and a drain electrically coupled to the second output terminal, and the second latch transistor has a gate electrically coupled to the second output terminal and a drain electrically coupled to the first output terminal; making a voltage detection circuit detect the first output voltage and the second output voltage, so as to trigger a conduction adjustment circuit when the first output voltage and the second output voltage are not in a default range; and making the conduction adjustment circuit strengthen the conduction degree of the latch circuit when triggered.

[0007] The features, implementations and effects of the present application are described in detail below with reference to the preferred embodiments and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A circuit diagram of a comparator circuit with false alarm prevention mechanism in an embodiment of the present application is shown.

[0009] Figure 2 A circuit diagram of a comparator circuit in another embodiment of the present application is shown.

[0010] Figure 3 A circuit diagram of a comparator circuit in still another embodiment of the present application is shown.

[0011] Figure 4 A flowchart of a comparator circuit operation method with false alarm prevention mechanism in an embodiment of the present application is shown.

[0012] SYMBOL DESCRIPTION

[0013] 100: comparator circuit

[0014] 110: input pair circuit

[0015] 120: latch circuit

[0016] 130: conduction adjustment circuit

[0017] 140: voltage detection circuit

[0018] 150A: first output inverter

[0019] 150B: second output inverter

[0020] 160: switch circuit

[0021] 200: comparator circuit

[0022] 210: conduction adjustment circuit

[0023] 220: voltage dividing circuit

[0024] 300: comparator circuit

[0025] 400: method of operating a comparator circuit

[0026] S410-S440: steps

[0027] AOU1: first actual output

[0028] AOU2: second actual output

[0029] CLK: control frequency signal

[0030] GND: ground

[0031] IN1: first input

[0032] IN2: second input

[0033] MA1: first conduction adjustment transistor

[0034] MA2: second conduction adjustment transistor

[0035] MC1: first operation control transistor

[0036] MC2: second operation control transistor

[0037] MC3: third operation control transistor

[0038] MI1: first input transistor

[0039] MI2: second input transistor

[0040] ML1: first latch transistor

[0041] ML2: second latch transistor

[0042] NO1: first connection

[0043] NO2: second connection

[0044] OUT1: first output

[0045] OUT2: second output

[0046] VA: voltage source

[0047] VC1: first comparison result

[0048] VC2: second comparison result

[0049] VDD: supply power

[0050] Vin1: first input voltage

[0051] Vin2: second input voltage

[0052] Vout1: first output voltage

[0053] Vout2: second output voltage

[0054] VS: feed-in voltage DETAILED DESCRIPTION

[0055] One of the purposes of the present application is to provide a comparator circuit with false alarm prevention mechanism and its operation method. By means of the voltage detection circuit and the on adjustment circuit, the output voltage between the input pair circuit and the latch circuit is detected, so that when the output voltage is not in the default range, the on adjustment circuit is triggered to strengthen the on degree of the latch circuit, thereby adjusting the output voltage to prevent false alarms.

[0056] Figure 1 In an embodiment of the present application, a circuit diagram of a comparator circuit 100 with false alarm prevention mechanism is shown. The comparator circuit 100 comprises an input pair circuit 110, a latch circuit 120, an on adjustment circuit 130 and a voltage detection circuit 140.

[0057] The input pair circuit 110 corresponds to a first input terminal IN1, a second input terminal IN2, a first output terminal OUT1 and a second output terminal OUT2.

[0058] In an embodiment, the input pair circuit 110 comprises a first input transistor MI1 and a second input transistor MI2. In this embodiment, the input pair circuit 110 is a P-type transistor circuit, so the first input transistor MI1 and the second input transistor MI2 are P-type transistors respectively.

[0059] The first input transistor MI1 has a gate, a drain and a source. The gate is electrically coupled to the first input terminal IN1, and the drain is electrically coupled to the first output terminal OUT1. The second input transistor MI2 also has a gate, a drain and a source. The gate is electrically coupled to the second input terminal IN2, and the drain is electrically coupled to the second output terminal OUT2.

[0060] The latch circuit 120 comprises a first latch transistor ML1 and a second latch transistor ML2. In this embodiment, the first latch transistor ML1 and the second latch transistor ML2 are N-type transistors respectively.

[0061] The first latch transistor ML1 has a gate, a drain and a source. The gate is electrically coupled to the first output terminal OUT1, the drain is electrically coupled to the second output terminal OUT2, and the source is electrically coupled to the first supply terminal. In the embodiment, the first supply terminal is a ground terminal GND. The second latch transistor ML2 also has a gate, a drain and a source. The gate is electrically coupled to the second output terminal OUT2, the drain is electrically coupled to the first output terminal OUT1, and the source is electrically coupled to the first supply terminal.

[0062] In an embodiment, the comparator circuit 100 selectively includes a first output inverter 150A and a second output inverter 150B. The first output inverter 150A is electrically coupled to the first output terminal OUT1 to invert the voltage of the first output terminal OUT1 and output the inverted voltage to a first actual output terminal AOU1. The second output inverter 150B is electrically coupled to the second output terminal OUT2 to invert the voltage of the second output terminal OUT2 and output the inverted voltage to a second actual output terminal AOU2.

[0063] The turn-on adjustment circuit 130 is configured to enhance the turn-on degree of the latch circuit 120 when triggered. In an embodiment, the turn-on adjustment circuit 130 includes a first turn-on adjustment transistor MA1, a second turn-on adjustment transistor MA2 and a switch circuit 160.

[0064] The first turn-on adjustment transistor MA1 has a gate, a drain and a source. The gate is electrically coupled to the first connection terminal NO1, the drain is electrically coupled to the second connection terminal NO2, and the source is electrically coupled to the first supply terminal. The second turn-on adjustment transistor MA2 has a gate, a drain and a source. The gate is electrically coupled to the second connection terminal NO2, the drain is electrically coupled to the first connection terminal NO1, and the source is electrically coupled to the first supply terminal.

[0065] The switch circuit 160, when triggered, electrically couples the first connection terminal NO1 to the first output terminal OUT1 and electrically couples the second connection terminal NO2 to the second output terminal OUT2, so as to electrically connect the first turn-on adjustment transistor MA1 in parallel with the first latch transistor ML1 and electrically connect the second turn-on adjustment transistor MA2 in parallel with the second latch transistor ML2.

[0066] In addition, the switch circuit 160, when not triggered, electrically isolates the first connection terminal NO1 from the first output terminal OUT1 and electrically isolates the second connection terminal NO2 from the second output terminal OUT2, so as to electrically isolate the first turn-on adjustment transistor MA1 from the first latch transistor ML1 and electrically isolate the second turn-on adjustment transistor MA2 from the second latch transistor ML2.

[0067] The voltage detection circuit 140 is configured to detect the voltages of the first output terminal OUT1 and the second output terminal OUT2, so as to control whether to trigger the conduction adjustment circuit 130 according to the voltages of the first output terminal OUT1 and the second output terminal OUT2. In more detail, the voltage detection circuit 140 actually controls whether to trigger the switch circuit 160 according to the voltages of the first output terminal OUT1 and the second output terminal OUT2.

[0068] In an embodiment, the voltage detection circuit 140 is configured to trigger the conduction adjustment circuit 130 to enhance the conduction degree of the first latch transistor ML1 and the second latch transistor ML2 when the voltages of the first output terminal OUT1 and the second output terminal OUT2 are not in the default range. Moreover, the voltage detection circuit 140 is configured not to trigger the conduction adjustment circuit 130 to adjust the conduction degree of the first latch transistor ML1 and the second latch transistor ML2 when the voltages of the first output terminal OUT1 and the second output terminal OUT2 are in the default range.

[0069] In the present embodiment, the voltage detection circuit 140 judges that the voltages of the first output terminal OUT1 and the second output terminal OUT2 are not in the default range when the voltages are not less than a default value.

[0070] It should be noted that, in Figure 1 In order to make the figure neat, the first output terminal OUT1 is respectively drawn for the input pair circuit 110 and the latch circuit 120, the conduction adjustment circuit 130 and the voltage detection circuit 140, however, in fact, these first output terminals OUT1 are the same point. Similarly, the second output terminal OUT2 is respectively drawn for the input pair circuit 110 and the latch circuit 120, the conduction adjustment circuit 130 and the voltage detection circuit 140, however, in fact, these second output terminals OUT2 are the same point.

[0071] The operation of the comparator circuit 100 will be described in more detail below.

[0072] In an embodiment, the comparator circuit 100 can selectively include a first operation control transistor MC1, a second operation control transistor MC2 and a third operation control transistor MC3, so as to switch according to the control frequency signal CLK, and make the comparator circuit 100 operate in the reset state and the operation state.

[0073] In more detail, the first operation control transistor MC1 is electrically coupled between the first output terminal OUT1 and a first supply power terminal. The second operation control transistor MC2 is electrically coupled between the second output terminal OUT2 and the first supply power terminal. The third operation control transistor MC3 is electrically coupled between the first supply power terminal and the input pair circuit 110. The first supply power terminal is a supply power VDD, and the third operation control transistor MC3 is electrically coupled between the supply power VDD and the sources of the first input transistor MI1 and the second input transistor MI2.

[0074] In this embodiment, the first operation control transistor MC1 and the second operation control transistor MC2 are N-type transistors, and the third operation control transistor MC3 is a P-type transistor.

[0075] In the reset state, the control frequency signal CLK is at a high level. Therefore, the first operation control transistor MC1 and the second operation control transistor MC2 are enabled according to the control frequency signal CLK, and the third operation control transistor MC3 is disabled according to the control frequency signal CLK.

[0076] The input pair circuit 110 will not receive the supply power VDD due to the disabling of the third operation control transistor MC3. Therefore, the input pair circuit 110 will not operate regardless of the voltages received by the first input terminal IN1 and the second input terminal IN2. However, the first output terminal OUT1 and the second output terminal OUT2 are reset to low levels due to the enabling of the first operation control transistor MC1 and the second operation control transistor MC2.

[0077] The first output inverter 150A and the second output inverter 150B respectively invert the voltages of the first output terminal OUT1 and the second output terminal OUT2 and output the inverted voltages, so that the first actual output terminal AOU1 and the second actual output terminal AOU2 are reset to high levels.

[0078] At this time, the voltage detection circuit 140 determines that the voltages of the first output terminal OUT1 and the second output terminal OUT2 are less than a default value and are within a default range, because the voltages of the first output terminal OUT1 and the second output terminal OUT2 are at low levels. Therefore, the voltage detection circuit 140 does not trigger the conduction adjustment circuit 130 to adjust the conduction levels of the first latch transistor ML1 and the second latch transistor ML2.

[0079] In the operation state, the control frequency signal CLK is at a low level. Therefore, the first operation control transistor MC1 and the second operation control transistor MC2 are disabled according to the control frequency signal CLK, and the third operation control transistor MC3 is enabled according to the control frequency signal CLK.

[0080] The input pair circuit 110 will receive the power supply VDD due to the enablement of the third operation control transistor MC3, while the first output terminal OUT1 and the second output terminal OUT2 will not be affected due to the disablement of the first operation control transistor MC1 and the second operation control transistor MC2.

[0081] At this time, the input pair circuit 110 and the latch circuit 120 will operate together to compare the first input voltage Vinl received by the first input terminal IN1 and the second input voltage Vin2 received by the second input terminal IN2 according to the first input voltage Vinl and the second input voltage Vin2, and generate the first output voltage Voutl at the first output terminal OUT1 and the second output voltage Vout2 at the second output terminal OUT2.

[0082] The first output inverter 150A further inverts and outputs the first output voltage Voutl to the first actual output terminal AOUl as the first comparison result VC1. The second output inverter 150B further inverts and outputs the second output voltage Vout2 to the second actual output terminal AOU2 as the second comparison result VC2.

[0083] In this embodiment, when the first input voltage Vinl is greater than the second input voltage Vin2, the first output voltage Voutl will be at a low level and the second output voltage Vout2 will be at a high level. Therefore, the first comparison result VC1 will be at a high level and the second comparison result VC2 will be at a low level.

[0084] When the first input voltage Vinl is less than the second input voltage Vin2, the first output voltage Voutl will be at a high level and the second output voltage Vout2 will be at a low level. Therefore, the first comparison result VC1 will be at a low level and the second comparison result VC2 will be at a high level.

[0085] However, in the operation state, when the first input terminal IN1 and the second input terminal IN2 just receive the first input voltage Vinl and the second input voltage Vin2, the latch circuit 120 will first raise the first output voltage Voutl and the second output voltage Vout2 to a metastable state, and then gradually pull them to one of the high level and the low level according to the magnitude of the first input voltage Vinl and the second input voltage Vin2. If the voltage is not low enough due to the slow speed of the voltage drop from the metastable state to the low level, the final comparison result will be incorrect.

[0086] Therefore, the voltage detection circuit 140 will detect the first input voltage Vin1 and the second input voltage Vin2, so as to trigger the conduction adjustment circuit 130 when the first input voltage Vin1 and the second input voltage Vin2 are not within the default range.

[0087] As mentioned above, in this embodiment, the voltage detection circuit 140 determines that the voltage of the first input voltage Vin1 and the second input voltage Vin2 is not less than the default value, thereby triggering the switching circuit 160 in the conduction adjustment circuit 130, which in turn connects the first conduction adjustment transistor MA1 and the first latching transistor ML1 in parallel, and connects the second conduction adjustment transistor MA2 and the second latching transistor ML2 in parallel.

[0088] In this way, the first turn-on adjustment transistor MA1 and the second turn-on adjustment transistor MA2 of the turn-on adjustment circuit 130 effectively increase the width-to-length ratio (W / L ratio) of the first latching transistor ML1 and the second latching transistor ML2, thereby enhancing the conduction level of the latching circuit 120. The first output voltage Vout1 and the second output voltage Vout2 can be pulled down to accelerate the process from the metastable state to the steady state and prevent false alarms caused by erroneous comparison results.

[0089] On the other hand, in the operating state, when the voltage detection circuit 140 detects and determines that the first input voltage Vin1 and the second input voltage Vin2 are within the default range, the conduction adjustment circuit 130 is not triggered and the conduction degree of the latch circuit 120 is not adjusted.

[0090] Therefore, the comparator circuit of the present invention with a false alarm prevention mechanism can detect the output voltage between the input pair circuit and the latch circuit by setting up a voltage detection circuit and a conduction adjustment circuit. When the output voltage is not within the default range, the conduction adjustment circuit is triggered to enhance the conduction degree of the latch circuit, thereby adjusting the output voltage to prevent false alarms.

[0091] Please refer to Figure 2 . Figure 2 This shows a circuit diagram of comparator circuit 200 according to another embodiment of the present invention. Figure 2 Comparator circuit 200 and Figure 1 The comparator circuit 100 is largely the same, including the input pair circuit 110, the latch circuit 120, and the voltage detection circuit 140, so the same components will not be described in detail.

[0092] In this embodiment, the comparator circuit 200 comprises a turn-on adjustment circuit 210, and the turn-on adjustment circuit 210 is a voltage feeding circuit. In one embodiment, the voltage feeding circuit comprises a voltage source VA and a voltage dividing circuit 220. The voltage source VA is configured to generate a source voltage. The voltage dividing circuit 220 is configured to divide the source voltage VA to generate a feeding voltage VS.

[0093] The voltage detection circuit 140 is configured to trigger the voltage feeding circuit to make the feeding voltage VS have a boosting level and feed into the substrate of each of the first and second latching transistors ML1 and ML2 to adjust the threshold voltage of each of the first and second latching transistors ML1 and ML2 when the first and second output voltages Vin1 and Vin2 are not in the default range. It should be noted that, for the sake of neatness of the drawing, only the feeding voltage VS is shown as being directed to the first and second latching transistors ML1 and ML2. In fact, the feeding voltage VS is transmitted to the substrate of the first and second latching transistors ML1 and ML2. Figure 2

[0094] In one embodiment, since each of the first and second latching transistors ML1 and ML2 is an N-type transistor, the threshold voltage of each of the first and second latching transistors ML1 and ML2 will be lowered when the feeding voltage VS is larger, thereby boosting the turn-on degree of each of the first and second latching transistors ML1 and ML2.

[0095] On the other hand, the voltage detection circuit 140 does not feed the feeding voltage VS having the boosting level into the substrate of each of the first and second latching transistors ML1 and ML2 when the first and second output voltages Vin1 and Vin2 are in the default range.

[0096] Therefore, the comparator circuit 200 in this embodiment can adjust the output voltage by the turn-on adjustment circuit 210 implemented by the voltage feeding circuit when the output voltage is not in the default range, thereby achieving a mechanism for preventing false alarms.

[0097] Please refer to Figure 3 . Figure 3 A circuit diagram of a comparator circuit 300 in another embodiment of the present application is shown. Figure 3 The comparator circuit 300 is similar to the comparator circuit 100 shown in Figure 1 and comprises an input pair circuit 110, a latching circuit 120, a turn-on adjustment circuit 130 and a voltage detection circuit 140.

[0098] ​In this embodiment, the input pair circuit 110 is an N-type transistor circuit, and includes a first input transistor MI1 and a second input transistor MI2, which are N-type transistors respectively. The latch circuit 120 includes a first latch transistor ML1 and a second latch transistor ML2, which are P-type transistors respectively.

[0099] Furthermore, the conduction adjustment circuit 130 includes a first conduction adjustment transistor MA1 and a second conduction adjustment transistor MA2, both of which are P-type transistors. The first operation control transistor MC1 and the second operation control transistor MC2 are both P-type transistors, and the third operation control transistor MC3 is an N-type transistor. The first power supply terminal is the power supply VDD, and the second power supply terminal is the ground terminal VDD.

[0100] Therefore, the operating mechanism of comparator circuit 300 is opposite to that of comparator circuit 100. When voltage detection circuit 140 determines that the first input voltage Vin1 and the second input voltage Vin2 are not greater than the default value, it triggers conduction adjustment circuit 130 to enhance the conduction degree of latching circuit 120. The detailed operation method will not be described here.

[0101] It should be noted that, Figure 2 The illustrated conduction adjustment circuit 210 can also be applied to Figure 3 In the architecture, the output voltage is adjusted by applying voltage to the substrate of each first latching transistor ML1 and second latching transistor ML2 in the latching circuit 120, thereby achieving a mechanism to prevent false alarms.

[0102] Please refer to Figure 4 . Figure 4 This diagram shows a flowchart of a comparator circuit operation method 400 with a false alarm prevention mechanism in one embodiment of the present invention.

[0103] In step S410, the input pair circuit 110 is in the operating state to receive the first input voltage and the second input voltage from the first input terminal IN1 and the second input terminal IN2, respectively.

[0104] In step S420, the input pair circuit 110 and the latch circuit 120 operate together in the operating state to compare the first input voltage Vin1 and the second input voltage Vin2, and generate the first output voltage Vout1 and the second output voltage Vout2 at the first output terminal OUT1 and the second output terminal OUT2, respectively.

[0105] In step S430, the voltage detection circuit 140 detects the first output voltage and the second output voltage, so as to trigger the conduction adjustment circuit 130 when the first output voltage Vout1 and the second output voltage Vout2 are not within the default range.

[0106] In step S440, the conduction adjustment circuit is triggered to enhance the conduction of the latching circuit.

[0107] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0108] In summary, the comparator circuit and its operation method with a false alarm prevention mechanism in this invention detect the output voltage between the input pair circuit and the latch circuit by setting up a voltage detection circuit and a conduction adjustment circuit. When the output voltage is not within the default range, the conduction adjustment circuit is triggered to enhance the conduction degree of the latch circuit, thereby adjusting the output voltage to prevent false alarms.

[0109] Although the embodiments of this application are described above, these embodiments are not intended to limit this application. Those skilled in the art can make changes to the technical features of this application based on the express or implied content of this application. All such changes may fall within the scope of patent protection sought by this application. In other words, the scope of patent protection of this application shall be determined by the claims of this specification.

Claims

1. A comparator circuit having a false alarm prevention mechanism, characterized by A voltage sensing circuit is configured to detect the first output voltage and the second output voltage, and to trigger the conduction adjustment circuit when the first output voltage and the second output voltage are not within a default range. The conduction adjustment circuit includes: a first conduction adjustment transistor having a gate electrically coupled to a first connection terminal and a drain electrically coupled to a second connection terminal; a second conduction adjustment transistor having a gate electrically coupled to the second connection terminal and a drain electrically coupled to the first connection terminal; and a switch circuit; wherein the voltage sensing circuit is configured to trigger the switch circuit to electrically couple the first connection terminal and the second connection terminal to the first output terminal and the second output terminal when the first output voltage and the second output voltage are not within the default range, so as to cause the first conduction adjustment transistor to be connected in parallel with the first latch transistor and the second conduction adjustment transistor to be connected in parallel with the second latch transistor; the voltage sensing circuit is further configured to not trigger the switch circuit to electrically isolate the first connection terminal and the second connection terminal from the first output terminal and the second output terminal when the first output voltage and the second output voltage are within the default range, so as to cause the first conduction adjustment transistor to be electrically isolated from the first latch transistor and the second conduction adjustment transistor to be electrically isolated from the second latch transistor. The conduction adjustment circuit is a voltage feed-in circuit, and the voltage sensing circuit is configured to trigger the voltage feed-in circuit to feed in a feed-in voltage having an enhanced level to a substrate of each of the first latch transistor and the second latch transistor to adjust a threshold voltage of each of the first latch transistor and the second latch transistor when the first output voltage and the second output voltage are not within the default range, and not to trigger the voltage feed-in circuit to feed in the feed-in voltage having the enhanced level to the substrate when the first output voltage and the second output voltage are within the default range. The voltage feed-in circuit includes:

2. The comparator circuit of claim 1, wherein, a voltage source configured to generate a source voltage; and a voltage dividing circuit configured to divide the source voltage to generate the feed-in voltage. The input pair circuit includes: ​ ​ ​ 3. The comparator circuit of claim 1, wherein ​ 4. The comparator circuit of claim 3, wherein, ​ ​ ​ 5. The comparator circuit of claim 1, wherein, ​ a first input transistor having a gate electrically coupled to the first input terminal and a drain electrically coupled to the first output terminal; and a second input transistor having a gate electrically coupled to the second input terminal and a drain electrically coupled to the second output terminal.

6. The comparator circuit of claim 1, wherein, The first and second latch transistors are N-type transistors, and the input pair circuit is a P-type transistor circuit, the voltage detection circuit is configured to cause the turn-on adjustment circuit to strengthen the turn-on degree of the latch circuit when the first and second output voltages are not less than a default value.

7. The comparator circuit of claim 1, wherein, The first and second latch transistors are P-type transistors, and the input pair circuit is an N-type transistor circuit, the voltage detection circuit is configured to cause the turn-on adjustment circuit to strengthen the turn-on degree of the latch circuit when the first and second output voltages are not greater than a default value.

8. The comparator circuit of claim 1, wherein, The first latch transistor further has a source electrically coupled to a first supply terminal, the second latch transistor further has a source electrically coupled to the first supply terminal, and the comparator further includes: a first operation control transistor electrically coupled between the first output terminal and the first supply terminal; a second operation control transistor electrically coupled between the second output terminal and the first supply terminal; and a third operation control transistor electrically coupled between a second supply terminal and the input pair circuit; wherein in a reset state, the first and second operation control transistors are enabled according to a control frequency signal, and the third operation control transistor is disabled according to the control frequency signal; in the operation state, the first and second operation control transistors are disabled according to the control frequency signal, and the third operation control transistor is enabled according to the control frequency signal. further including:

9. The comparator circuit of claim 1, wherein, a first output inverter electrically coupled to the first output terminal, outputting a first comparison result to a first actual output terminal according to the first output voltage; and a second output inverter electrically coupled to the second output terminal, outputting a second comparison result to a second actual output terminal according to the second output voltage. including:

10. A method of operating a comparator circuit having a false alarm prevention mechanism, the method comprising: causing an input pair circuit to receive a first input voltage and a second input voltage from first and second input terminals, respectively; causing the input pair circuit and a latch circuit to operate together in an operation state to compare the first and second input voltages, and to generate a first output voltage and a second output voltage at first and second output terminals, respectively, wherein the latch circuit includes a first latch transistor having a gate electrically coupled to the first output terminal and a drain electrically coupled to the second output terminal, and a second latch transistor having a gate electrically coupled to the second output terminal and a drain electrically coupled to the first output terminal; causing a voltage detection circuit to detect the first and second output voltages, and to trigger a turn-on adjustment circuit when the first and second output voltages are not within a default range; ​ and the on adjustment circuit is triggered, the on degree of the latch circuit is enhanced.

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