A method for FPGA-assisted 5G module to improve IRIGB code timing accuracy and reliability

Abstract

The present invention relates to a method for improving the timing accuracy and reliability of IRIGB code by using FPGA to assist 5G module, comprising the following steps: outputting 1pps signal and IRIGB code by 5G module; performing jitter filtering and time-keeping processing on 1pps signal to obtain processed 1pps signal; performing precision calibration and time calculation on IRIGB code according to processed 1pps signal, and outputting calibrated IRIGB code. The present invention solves the problem of 100ms jitter in outputting IRIGB code by 5G module, and continues to provide high-precision IRIGB code to downstream equipment when 5G signal is poor or no signal.

Description

Technical Field

[0001] The present invention relates to a method for improving the timing accuracy and reliability of IRIGB codes by using an FPGA-assisted 5G module, and belongs to the technical field of communications. Background Art

[0002] The 5G module obtains time information through the 5G signal and sends a precise 1pps signal and an IRIGB code with jitter. The accuracy of the 1pps signal is within 200ns, and the accuracy of the IRIGB code is about 100ms. In many application scenarios, the downstream device only receives the IRIGB code to complete the time synchronization function. Since the accuracy of the IRIGB code output by the 5G module is about 100ms, the time obtained by the downstream device has a 100ms jitter. At the same time, when the 5G signal quality is poor or lost, the 1PPS has the problem of loss or large instantaneous jitter. However, some downstream devices have strict requirements on time accuracy and require the IRIGB code signal accuracy to be within 1ms. Therefore, the accuracy of the IRIGB code signal output by the 5G module cannot meet the application requirements. Summary of the invention

[0003] In order to overcome the above problems, the present invention provides a method for improving the timing accuracy and reliability of IRIGB code by using FPGA to assist 5G module. The method uses FPGA and clock synchronization design to solve the problem that when the 5G module outputs IRIGB code with 100ms jitter, or the 5G signal is poor or there is no signal, it continues to provide high-precision IRIGB code to downstream devices.

[0004] The technical solution of the present invention is as follows:

[0005] In a first aspect, a method for improving the IRIGB code timing accuracy and reliability by using an FPGA to assist a 5G module comprises the following steps:

[0006] The 5G module outputs 1pps signal and IRIGB code;

[0007] Perform jitter filtering and time-keeping processing on the 1pps signal to obtain a processed 1pps signal;

[0008] The IRIGB code is calibrated for accuracy and time is calculated according to the processed 1pps signal, and the calibrated IRIGB code is output.

[0009] Furthermore, the accuracy of the 1pps signal output by the 5G module is within 200ns, and the accuracy of the processed 1pps signal is within 100ns.

[0010] Furthermore, jitter filtering and timing of the 1pps signal are performed in the following ways:

[0011] Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter;

[0012] Synchronize the frequency and phase of the 1pps signal output by the 5G module;

[0013] Monitor the 1pps signal output by the 5G module. When the 1pps signal is lost, use the temperature compensation voltage control accuracy to output the 1pps signal to the processing unit.

[0014] Furthermore, the IRIGB code is calibrated for accuracy and time is calculated based on the processed 1pps signal, specifically:

[0015] Decode the IRIGB code to obtain the time information;

[0016] Calculate the time information of the next moment according to the time information as the time content of the calibrated IRIGB code;

[0017] After receiving the processed 1pps signal, the timing starts, and at the next moment, the calibrated IRIGB code is sent out.

[0018] Furthermore, the next moment is 1 second later.

[0019] In the second aspect, a device for improving the IRIGB code timing accuracy and reliability by using an FPGA-assisted 5G module, using the method for improving the IRIGB code timing accuracy and reliability by using an FPGA-assisted 5G module as described in the first aspect, including a 5G module, a clock synchronization module, and a processing unit;

[0020] The 5G module outputs a 1pps signal to the clock synchronization module and outputs an IRIGB code to the processing unit;

[0021] The clock synchronization module performs jitter filtering and time keeping on the 1pps signal, and outputs the processed 1pps signal to the processing unit;

[0022] The processing unit performs precision calibration and time calculation on the 1pps signal and the IRIGB code, and outputs the calibrated IRIGB code to a downstream device.

[0023] Furthermore, the accuracy of the 1pps signal output by the 5G module is within 200ns, and the accuracy of the processed 1pps signal is within 100ns.

[0024] Furthermore, the clock synchronization module implements the following functions:

[0025] Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter;

[0026] Synchronize the frequency and phase of the 1pps signal output by the 5G module;

[0027] Monitor the 1pps signal output by the 5G module. When the 1pps signal is lost, use the temperature-compensated voltage control accuracy to output the 1pps signal to the processing unit.

[0028] Further, the FPGA includes a clock module, an IRIGB code decoding module, a 1pps calculation module, a time recalculation module and an IRIGB code sending module;

[0029] The clock module is in communication with the IRIGB code decoding module and the 1pps calculation module to provide a high-frequency clock for the FPGA;

[0030] The IRIGB code decoding module receives the IRIGB code output by the 5G module, parses the event information therein, and transmits it to the time recalculation module;

[0031] The time recalculation module calculates the time information of the next moment according to the time information as the time content of the IRIGB code output by the FPGA module at the next moment;

[0032] After receiving the 1pps signal output by the clock synchronization module, the 1pps calculation module starts the time counting function, and when counting reaches the next moment, sends a signal to enable the IRIGB code sending module to send the IRIGB code.

[0033] Furthermore, the next moment is 1 second later.

[0034] The present invention has the following beneficial effects:

[0035] The clock synchronization module uses 1PPS as input, and uses the good long-term stability of 1PPS and the good short-term stability of the local crystal oscillator. After comparing the output signal with the local clock, it adjusts the voltage-controlled crystal oscillator and outputs the 1PPS signal after filtering out the jitter. When the 1PPS signal is temporarily lost, the local crystal oscillator generates 1PPS and sends it to the FPGA. The FPGA uses the 1pps signal with an accuracy of less than 100ns output by the clock synchronization module to recalibrate the IRIGB code, so that the FPGA output IRIGB code accuracy is within 100ns. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 This is the IRIGB code transmission process of the prior art.

[0037] Figure 2 This is the IRIGB code transmission process of the method of the present invention.

[0038] Figure 3 Schematic diagram of FPGA functional modules according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Figure 1 This is the IRIGB code transmission process of the prior art. In the prior art, the 5G module sends the IRIGB code with jitter to the downstream device, and the downstream device completes the time synchronization function according to the IRIGB code with jitter. Since the accuracy of the IRIGB code output by the 5G module is about 100ms, the time obtained by the downstream device has a jitter of 100ms.

[0041] First, refer to Figure 2 , a method for improving the IRIGB code timing accuracy and reliability of a 5G module using an FPGA, comprising the following steps:

[0042] The 5G module outputs 1pps signal and IRIGB code;

[0043] Perform jitter filtering and time-keeping processing on the 1pps signal to obtain a processed 1pps signal;

[0044] The IRIGB code is calibrated for accuracy and time is calculated according to the processed 1pps signal, and the calibrated IRIGB code is output.

[0045] In a specific embodiment of the present invention, the accuracy of the 1pps signal output by the 5G module is within 200ns, and the accuracy of the processed 1pps signal is within 100ns.

[0046] High-frequency jitter can be filtered out by setting different phase-locked loop bandwidths. When 1PPS is input, a 100Hz phase-locked loop bandwidth is generally selected. When the jitter of 1PPS is greater than 1 / 100Hz=10 milliseconds, since it is not within the set phase-locked loop bandwidth, the output does not respond to the input jitter and does not adjust the 1PPS output, thereby reducing the jitter value.

[0047] In one embodiment of the present invention, jitter filtering and timing of a 1 pps signal are performed in the following manner:

[0048] Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter;

[0049] Synchronize the frequency and phase of the 1pps signal output by the 5G module;

[0050] Monitor the 1pps signal output by the 5G module. When the 1pps signal is lost, use the temperature compensation voltage control accuracy to output the 1pps signal to the processing unit.

[0051] The 1PPS signal is generated by the 5G module. Due to the uncertainty of air interface transmission such as the ionosphere, troposphere, and multipath, there will be large random errors and follow a normal distribution. The jitter of the local crystal oscillator is mainly caused by its own aging. The daily aging rate of the temperature-compensated voltage-controlled crystal oscillator on the market can be controlled at ≤±2ppb, which is very stable in the short term. Taking advantage of the good long-term stability of 1PPS and the good short-term stability of the local crystal oscillator, the output signal is compared with the local clock to adjust the voltage-controlled crystal oscillator, and the 1PPS signal after filtering out the jitter is output.

[0052] In one embodiment of the present invention, the precision calibration and time calculation of the IRIGB code are performed according to the processed 1 pps signal, specifically:

[0053] Decode the IRIGB code to obtain the time information;

[0054] Calculate the time information of the next moment according to the time information as the time content of the calibrated IRIGB code;

[0055] After receiving the processed 1pps signal, the timing starts, and at the next moment, the calibrated IRIGB code is sent out.

[0056] Particularly, the next moment is 1 second later.

[0057] Second, refer to Figure 2 , a device for improving the IRIGB code timing accuracy and reliability of an FPGA-assisted 5G module, using a method for improving the IRIGB code timing accuracy and reliability of an FPGA-assisted 5G module as described in the first aspect, comprising a 5G module, a clock synchronization module, and a processing unit;

[0058] The 5G module outputs a 1pps signal to the clock synchronization module and outputs an IRIGB code to the processing unit;

[0059] The clock synchronization module performs jitter filtering and time keeping on the 1pps signal, and outputs the processed 1pps signal to the processing unit;

[0060] The processing unit performs precision calibration and time calculation on the 1pps signal and the IRIGB code, and outputs the calibrated IRIGB code to a downstream device.

[0061] In a specific embodiment of the present invention, the accuracy of the 1pps signal output by the 5G module is within 200ns, and the accuracy of the processed 1pps signal is within 100ns.

[0062] In one embodiment of the present invention, the clock synchronization module implements the following functions:

[0063] Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter;

[0064] Synchronize the frequency and phase of the 1pps signal output by the 5G module;

[0065] Monitor the 1pps signal output by the 5G module. When the 1pps signal is lost, use the temperature-compensated voltage control accuracy to output the 1pps signal to the processing unit.

[0066] In one embodiment of the present invention, the FPGA includes a clock module, an IRIGB code decoding module, a 1pps calculation module, a time recalculation module and an IRIGB code sending module;

[0067] The clock module is in communication with the IRIGB code decoding module and the 1pps calculation module to provide a high-frequency clock for the FPGA;

[0068] The IRIGB code decoding module receives the IRIGB code output by the 5G module, parses the event information therein, and transmits it to the time recalculation module;

[0069] The time recalculation module calculates the time information of the next moment according to the time information as the time content of the IRIGB code output by the FPGA module at the next moment;

[0070] After receiving the 1pps signal output by the time synchronization module, the 1pps calculation module starts the time counting function, and when counting reaches the next moment, sends a signal to enable the IRIGB code sending module to send the IRIGB code.

[0071] Particularly, the next moment is 1 second later.

[0072] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure made using the contents of the present invention's specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G modules, characterized in that: The following steps are involved: The 5G module outputs 1pps signal and IRIGB code; Perform jitter filtering and time-keeping processing on the 1pps signal to obtain a processed 1pps signal; According to the processed 1pps signal, the IRIGB code is calibrated for accuracy and time calculation, and the calibrated IRIGB code is output; The accuracy of the 1pps signal output by the 5G module is within 200ns, and the accuracy of the processed 1pps signal is within 100ns; The 1pps signal is jitter filtered and timed by: Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter; Synchronize the frequency and phase of the 1pps signal output by the 5G module; Monitor the 1pps signal output by the 5G module, and when the 1pps signal is lost, output the 1pps signal to the processing unit using temperature compensation and voltage control accuracy; According to the processed 1pps signal, the IRIGB code is calibrated for accuracy and time is calculated, specifically: Decode the IRIGB code to obtain the time information; Calculate the time information of the next moment according to the time information as the time content of the calibrated IRIGB code; After receiving the processed 1pps signal, the timing starts, and at the next moment, the calibrated IRIGB code is sent out.

2. The method for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G module according to claim 1, characterized in that: The next moment is 1 second later.

3. A device for improving the IRIGB code timing accuracy and reliability by using an FPGA-assisted 5G module, using a method for improving the IRIGB code timing accuracy and reliability by using an FPGA-assisted 5G module as claimed in claim 1 or 2, characterized in that: Including 5G module, clock synchronization module, and processing unit; The 5G module outputs a 1pps signal to the clock synchronization module and outputs an IRIGB code to the processing unit; The clock synchronization module performs jitter filtering and time keeping on the 1pps signal, and outputs the processed 1pps signal to the processing unit; The processing unit performs precision calibration and time calculation on the 1pps signal and the IRIGB code, and outputs the calibrated IRIGB code to a downstream device.

4. The device for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G module according to claim 3, characterized in that: The 1pps signal output by the 5G module has an accuracy within 200ns, and the processed 1pps signal has an accuracy within 100ns.

5. The device for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G module according to claim 3, characterized in that: The clock synchronization module implements the following functions: Set the PLL bandwidth of the clock synchronization chip to filter out high-frequency jitter; Synchronize the frequency and phase of the 1pps signal output by the 5G module; Monitor the 1pps signal output by the 5G module. When the 1pps signal is lost, use the temperature-compensated voltage control accuracy to output the 1pps signal to the processing unit.

6. The device for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G module according to claim 3, characterized in that: The FPGA includes a clock module, an IRIGB code decoding module, a 1pps calculation module, a time recalculation module and an IRIGB code sending module; The clock module is in communication with the IRIGB code decoding module and the 1pps calculation module to provide a high-frequency clock for the FPGA; The IRIGB code decoding module receives the IRIGB code output by the 5G module, parses the event information therein, and transmits it to the time recalculation module; The time recalculation module calculates the time information of the next moment according to the time information as the time content of the IRIGB code output by the FPGA module at the next moment; After receiving the 1pps signal output by the clock synchronization module, the 1pps calculation module starts the time counting function, and when counting reaches the next moment, sends a signal to enable the IRIGB code sending module to send the IRIGB code.

7. The device for improving the IRIGB code timing accuracy and reliability by using FPGA to assist 5G module according to claim 6, characterized in that: The next moment is 1 second later.

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