Semiconductor structure and method of manufacturing the same

Abstract

The application relates to a semiconductor structure and a preparation method thereof, which comprises a substrate with a first surface, a plurality of storage elements arranged on the first surface of the substrate according to a first preset pattern, a plurality of storage contact structures corresponding to the storage elements one by one, and the bottom of the storage contact structure is in contact with the top of the storage element, and the top of the storage contact structure is arranged according to a second preset pattern; wherein the bottom of the storage contact structure and the top of the storage contact structure are oppositely arranged. Through the arrangement, the device structure arranged according to the second preset pattern can be formed on the storage element arranged according to the first preset pattern, the arrangement or shape of the device structure formed on the storage element is not influenced by the arrangement shape of the storage element, the process difficulty is reduced, and the production cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Non-volatile memory has the characteristics of high-speed reading and writing, low power consumption, radiation resistance and long data retention time. It has an irreplaceable position in fields with high reliability requirements, such as national defense, aerospace, etc.

[0003] With the advancement of semiconductor technology, the demand for non-volatile memory capacity is increasing. To increase the capacity of non-volatile memory, storage elements need to be densely arranged. However, densely arranged storage elements restrict the shape of the bitline structure, increasing the production cost and process difficulty of non-volatile memory. How to reduce the production cost and process difficulty of non-volatile memory has become an urgent problem. Summary of the Invention

[0004] The embodiments of the present application provide a semiconductor structure and a method for manufacturing the same, which can optimize the manufacturing process of a non-volatile memory and achieve the purpose of reducing the production cost and process difficulty of the non-volatile memory.

[0005] A semiconductor structure comprising:

[0006] a substrate having a first surface;

[0007] A plurality of storage elements are located on the first surface of the substrate, and the storage elements are arranged in a first preset pattern;

[0008] a plurality of storage contact structures corresponding one to one with the storage elements, with the bottoms of the storage contact structures contacting the tops of the storage elements, and the tops of the storage contact structures arranged according to a second preset pattern;

[0009] The bottom of the storage contact structure and the top of the storage contact structure are arranged opposite to each other.

[0010] In one embodiment, the first preset pattern includes a regular hexagon, and each storage element is located at a vertex position and a center position of the regular hexagon.

[0011] In one embodiment, the bottom of the storage contact structure is arranged in a first predetermined pattern.

[0012] In one embodiment, the second predetermined pattern includes an array of multiple rows and columns.

[0013] In one embodiment, the semiconductor structure further comprises:

[0014] A plurality of bit line structures, any bit line structure contacts the top of the storage contact structure located in the same column, and the bit line structure is a straight line.

[0015] In one embodiment, the semiconductor structure further comprises:

[0016] a plurality of transistors located between the substrate and the memory element, the transistors corresponding to the memory elements one-to-one, and arranged according to a second predetermined pattern;

[0017] A plurality of transistor contact structures are located between the transistor and the memory element, and are in contact with the transistor and the memory element respectively. The tops of the transistor contact structures are arranged according to a first preset pattern.

[0018] In one embodiment, the bottom of the transistor contact structure is arranged in a second predetermined pattern;

[0019] The bottom of the transistor contact structure and the top of the transistor contact structure are arranged opposite to each other.

[0020] In one embodiment, the transistor contact structure includes:

[0021] a first lead-out structure, wherein a bottom of the first lead-out structure contacts the transistor;

[0022] a second lead-out structure, wherein a bottom of the second lead-out structure contacts a top of the first lead-out structure, and a top of the second lead-out structure is a top of the transistor contact structure;

[0023] The bottom of the first lead-out structure and the top of the first lead-out structure are arranged opposite to each other, and the bottom of the second lead-out structure and the top of the second lead-out structure are arranged opposite to each other.

[0024] In one embodiment, the area of ​​the bottom of the second lead-out structure is not less than the area of ​​the top of the first lead-out structure.

[0025] In one embodiment, the memory element includes a ferroelectric memory element, a magnetoresistive memory element, a resistive memory element, or a phase change memory element.

[0026] A method for preparing a semiconductor structure, comprising:

[0027] providing a substrate having a first surface;

[0028] forming a plurality of memory elements on the first surface of the substrate, wherein the memory elements are arranged in a first predetermined pattern;

[0029] A storage contact structure is formed on the top of each storage element, and the top of the storage contact structure is arranged according to a second preset pattern.

[0030] In one embodiment, the first preset pattern includes a regular hexagon, and each storage element is located at a vertex position and a center position of the regular hexagon.

[0031] In one embodiment, the bottom of the storage contact structure contacts the top of the storage element, and the bottom of the storage contact structure is arranged according to a first predetermined pattern;

[0032] The bottom of the storage contact structure is arranged opposite to the top of the storage contact structure.

[0033] In one embodiment, the second predetermined pattern includes an array of multiple rows and columns.

[0034] In one embodiment, the method for preparing a semiconductor structure further includes:

[0035] A plurality of bit line structures are formed on the top of the storage contact structure. Any bit line structure contacts the top of the storage contact structure in the same column. The bit line structure is a straight line.

[0036] In one embodiment, before forming a plurality of memory elements on the first surface of the substrate, the method further includes:

[0037] forming a plurality of transistors on the first surface of the substrate, the transistors corresponding to the memory elements one-to-one, and the transistors arranged according to a second predetermined pattern;

[0038] A transistor contact structure is formed on each transistor, the transistor contact structure is in contact with the transistor and the storage element, and the top of the transistor contact structure is arranged according to a first preset pattern.

[0039] In one embodiment, the bottom of the transistor contact structure is arranged in a second predetermined pattern;

[0040] The bottom of the transistor contact structure and the top of the transistor contact structure are arranged opposite to each other.

[0041] In one embodiment, the transistor contact structure includes a first lead structure and a second lead structure, and the steps of forming the transistor contact structure on each transistor include:

[0042] forming a first lead-out structure on each transistor, wherein the bottom of the first lead-out structure contacts the transistor;

[0043] forming a second lead-out structure on top of the first lead-out structure, wherein the top of the second lead-out structure contacts the bottom of the storage element;

[0044] The bottom of the first lead-out structure and the top of the first lead-out structure are arranged opposite to each other.

[0045] In one embodiment, the area of ​​the bottom of the second lead-out structure is not less than the area of ​​the top of the first lead-out structure;

[0046] The bottom of the second lead-out structure and the top of the second lead-out structure are arranged opposite to each other.

[0047] In one embodiment, the bottom of the first lead-out structure is arranged according to the second preset pattern, and the top of the second lead-out structure is arranged according to the first preset pattern.

[0048] The above-mentioned semiconductor structure includes a plurality of storage elements located on the first surface of the substrate, the storage elements are arranged according to a first preset pattern, a plurality of storage contact structures corresponding to the storage elements one by one, and the bottom of the storage contact structure contacts the top of the storage element, and the top of the storage contact structure is arranged according to a second preset pattern. Through this arrangement, a device structure arranged according to the second preset pattern can be formed on the storage elements arranged according to the first preset pattern, eliminating the influence of the arrangement shape of the storage elements on the arrangement or shape of the device structure formed on the storage elements, thereby achieving the purpose of reducing process difficulty and reducing production costs.

[0049] The method for fabricating the semiconductor structure includes providing a substrate having a first surface, forming a plurality of memory elements arranged according to a first predetermined pattern on the first surface of the substrate, and forming a memory contact structure on top of each memory element, with the tops of the memory contact structures arranged according to a second predetermined pattern. This arrangement allows device structures arranged according to the second predetermined pattern to be formed on the memory elements arranged according to the first predetermined pattern, eliminating the influence of the arrangement of the memory elements on the arrangement or shape of the device structures formed on the memory elements, thereby reducing process difficulty and production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the following briefly introduces the drawings required for use in the embodiments or the conventional technology descriptions. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0051] Figure 1 is a schematic cross-sectional view of a semiconductor structure in one embodiment;

[0052] Figure 2 is a schematic top view of a memory element in a semiconductor structure after the memory element is formed in one embodiment;

[0053] Figure 3 is a schematic top view of a semiconductor structure in one embodiment;

[0054] Figure 4 is a schematic cross-sectional view of a storage element in one embodiment;

[0055] Figure 5 is a schematic flow chart of a method for preparing a semiconductor structure in one embodiment;

[0056] Figure 6 is a schematic flow chart of a method for preparing a semiconductor structure according to another embodiment;

[0057] Figure 7 is a schematic diagram of a process for forming transistor contact structures on each transistor in one embodiment;

[0058] Figure 8 is a schematic cross-sectional view of a semiconductor structure after forming a transistor contact mask layer in one embodiment;

[0059] Figure 9 for Figure 8 A schematic cross-sectional view of a semiconductor structure after forming a transistor contact structure in a corresponding embodiment;

[0060] Figure 10 for Figure 9 A schematic cross-sectional view of a semiconductor structure after forming a memory element in a corresponding embodiment;

[0061] Figure 11 for Figure 10 A cross-sectional schematic diagram of a semiconductor structure after forming a bit line mask layer in a corresponding embodiment;

[0062] Figure 12 for Figure 11 A schematic cross-sectional view of the semiconductor structure after the bit line structure is formed in a corresponding embodiment.

[0063] Description of reference numerals:

[0064] 100, substrate; 102, storage element; 104, storage contact structure; 106, bit line structure; 108, transistor; 110, transistor contact structure; 112, word line structure; 114, global source line; 202, first lead structure; 204, second lead structure; 206, fixed layer; 208, non-magnetic isolation layer; 210, free layer; 212, bottom electrode; 214, top electrode; 216, protective layer; 302, first contact structure; 304, first conductive film; 306, transistor contact mask layer; 308, first dielectric layer; 310, second dielectric layer; 312, storage contact trench; 314, third dielectric layer; 316, storage contact layer; 318, bit line structure layer; 320, bit line mask layer; 322, fourth dielectric layer. DETAILED DESCRIPTION

[0065] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0066] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0067] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0068] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" can include both upper and lower orientations. In addition, the device can also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0069] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0070] MRAM (magnetic random access memory) is a non-volatile memory. The storage element of the memory cell in MRAM includes an upper electrode, a lower electrode, and a magnetic material located between the upper and lower electrodes. Data is written to the memory cell by passing current between the upper and lower electrodes of the target memory element. The current flowing through the memory element generates a magnetic field, which can cause erroneous writing to non-target memory elements with a specific probability. The probability of erroneous writing depends on the coercivity of the memory element (its tolerance to external magnetic fields) and the magnitude of the magnetic field. The magnitude of the magnetic field is proportional to the inverse of the distance between the target memory element and the affected non-target memory element.

[0071] To improve the integration of storage elements in MRAM while ensuring the accuracy of written data, the arrangement of storage elements in MRAM and their impact on the shape or position of the device structure above the storage elements determine the production cost and process difficulty of MRAM.

[0072] Figure 1 is a cross-sectional schematic diagram of a semiconductor structure in one embodiment, see Figure 1 In this embodiment, a semiconductor structure is provided, comprising: a substrate 100, a plurality of memory elements 102, and a plurality of memory contact structures 104. The substrate 100 has a first surface. The memory elements 102 are located on the first surface of the substrate 100 and arranged in a first predetermined pattern, i.e., each memory element 102 is arranged in the first predetermined pattern on the first surface of the substrate 100. The memory contact structures 104 are located on the memory elements 102 and correspond one-to-one with each memory element 102 on the substrate 100. The bottoms of the memory contact structures 104 contact the tops of the memory elements 102, and the tops of the memory contact structures 104 are arranged in a second predetermined pattern, i.e., the tops of the memory contact structures 104 on the memory elements 102 are arranged in a second predetermined pattern, which is different from the first predetermined pattern. The bottoms of the memory contact structures 104 and the tops of the memory contact structures 104 are arranged opposite each other, i.e., the bottoms of the memory contact structures 104 and the tops of the memory contact structures 104 are arranged in parallel.

[0073] The above-mentioned semiconductor structure includes a plurality of storage elements 102, which are located on the first surface of the substrate 100. The storage elements 102 are arranged according to a first preset pattern, and a plurality of storage contact structures 104, which correspond one-to-one to the storage elements 102, and the bottom of the storage contact structure 104 contacts the top of the storage element 102. The top of the storage contact structure 104 is arranged according to a second preset pattern. Through this arrangement, a device structure arranged according to the second preset pattern can be formed on the storage elements 102 arranged according to the first preset pattern, eliminating the influence of the arrangement shape of the storage elements 102 on the arrangement or shape of the device structure formed on the storage elements 102, thereby achieving the purpose of reducing process difficulty and reducing production costs.

[0074] Figure 2 FIG. 1 is a top view of a memory element in a semiconductor structure after forming the memory element 102 in one embodiment. Figure 2 As shown, in one embodiment, the first preset pattern includes a regular hexagon, and each storage element 102 is located at a vertex position and a center position of the regular hexagon.

[0075] In one embodiment, the bottom of the storage contact structure 104 is arranged in a first predetermined pattern.

[0076] In one embodiment, the bottom area of ​​the storage contact structure 104 is larger than the top area of ​​the storage element 102. In other embodiments, the bottom area of ​​the storage contact structure 104 is smaller than or equal to the top area of ​​the storage element 102. This configuration ensures close contact between the storage contact structure 104 and the storage element 102 while preventing damage to the storage element 102 during the formation of the storage contact structure 104.

[0077] In one embodiment, the material of the storage contact structure 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal may be tungsten (W), nickel (Ni) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0078] Figure 3 FIG. 1 is a schematic top view of a semiconductor structure in one embodiment. Figure 3 As shown, in one embodiment, the second preset pattern includes an array of multiple rows and columns.

[0079] Continue to refer Figure 1In one embodiment, the semiconductor structure further includes: a plurality of bitline structures 106, each of which contacts the top of the storage contact structure 104 located in the same column, and the bitline structures 106 are straight lines. Exemplarily, the length of the bitline structure 106 along the X direction is not less than the length of the top of the storage contact structure 104 along the X direction, and the X direction intersects the extension direction of the bitline structure 106.

[0080] Continue to refer Figure 1 In one embodiment, the semiconductor structure further includes: a plurality of transistors 108 and a plurality of transistor contact structures 110; the transistors 108 are located between the substrate 100 and the memory element 102, and the transistors 108 correspond to the memory element 102 one-to-one; the transistor contact structures 110 are located between the transistors 108 and the memory element 102, and are in contact with the transistors 108 and the memory element 102, respectively; and the tops of the transistor contact structures 110 are arranged according to a first preset pattern.

[0081] In one embodiment, transistors 108 are arranged in a third predetermined pattern. It is understood that the third predetermined pattern includes the first predetermined pattern and the second predetermined pattern. In practical applications, the arrangement of transistors 108 can be configured as needed. For example, when transistors 108 are arranged in the first predetermined pattern, the arrangement of transistors 108 is the same as that of storage elements 102. When transistors 108 are arranged in the second predetermined pattern, the arrangement of transistors 108 is the same as that of storage contact structures 104.

[0082] In one embodiment, the bottom of the transistor contact structure 110 is arranged according to a third preset pattern, and the bottom of the transistor contact structure 110 and the top of the transistor contact structure 110 are arranged relative to each other, wherein the third preset pattern includes the first preset pattern and the second preset pattern.

[0083] In one embodiment, the area of ​​the top of the transistor contact structure 110 is larger than the area of ​​the bottom of the memory element 102. In other embodiments, the area of ​​the top of the transistor contact structure 110 is smaller than or equal to the area of ​​the bottom of the memory element 102. This configuration can eliminate the impact of process variations on the contact resistance between the transistor contact structure 110 and the memory element 102.

[0084] Continue to refer Figure 1In one embodiment, the transistor contact structure 110 includes: a first lead-out structure 202 and a second lead-out structure 204; the bottom of the first lead-out structure 202 is in contact with the transistor 108 for leading out the transistor 108; illustratively, the bottom of the first lead-out structure 202 is connected to the drain of the transistor 108 for leading out the drain of the transistor 108, and typically, the area of ​​the bottom of the first lead-out structure 202 is equal to the area of ​​the drain of the transistor 108; the bottom of the second lead-out structure 204 is in contact with the top of the first lead-out structure 202, wherein the bottom of the first lead-out structure 202 and the top of the first lead-out structure 202 are arranged opposite to each other, and the bottom of the second lead-out structure 204 and the top of the second lead-out structure 204 are arranged opposite to each other, the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 110, and the top of the second lead-out structure 204 is the top of the transistor contact structure 110. At this time, the bottom of the first lead-out structure 202 is arranged according to the third preset pattern, and the top of the second lead-out structure 204 is arranged according to the first preset pattern. For example, the bottom of the first lead-out structure 202 is arranged according to the second preset pattern, and the top of the second lead-out structure 204 is arranged according to the first preset pattern; or the bottom of the first lead-out structure 202 and the top of the second lead-out structure 204 are both arranged according to the first preset pattern.

[0085] In one embodiment, the area of ​​the bottom of the second lead-out structure 204 is not less than the area of ​​the top of the first lead-out structure 202 .

[0086] In one embodiment, a portion of the first lead-out structure 202 close to the bottom of the second lead-out structure 204 is a trapezoidal structure.

[0087] In one embodiment, the material of the first lead structure 202 and the second lead structure 204 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, the material of at least one of the storage contact structure 104, the first lead structure 202, and the second lead structure 204 is different from the other. For example, the material of the first lead structure 202 is different from the materials of the storage contact structure 104 and the second lead structure 204. In practical applications, the storage contact structure 104, the first lead structure 202, and the second lead structure 204 may also be made of the same material as needed.

[0088] In one embodiment, the memory element 102 includes a ferroelectric memory element, a magnetoresistive memory element, a resistive memory element, or a phase change memory element.

[0089] Figure 4 FIG. 1 is a cross-sectional view of a memory element 102 in one embodiment. Figure 4 As shown, in this embodiment, the storage element 102 is a magnetoresistive storage element, and the storage element 102 includes: a fixed layer 206, a non-magnetic isolation layer 208, and a free layer 210. The fixed layer 206 is located at the bottom of the storage element 102, that is, the fixed layer 206 is connected to the transistor contact structure 110 and has a magnetic field in a preset direction. Compared with the free layer 210, the fixed layer 206 has a thicker film layer and a stronger magnetism, and its magnetic moment is not easily reversed. Exemplarily, the material of the fixed layer 206 includes CoFe and CoFeB. The typical fixed layer 206 is a stacked structure composed of multiple thin films, which includes, from bottom to top, a seed layer, a [Co(x) / Pt(y)] m stack, Ru or Ir metal layer, [Co(x) / Pt(y)] m The free layer 210 comprises a plurality of layers, a Ta metal layer, and a CoFeB metal layer; the non-magnetic isolation layer 208 is located between the free layer 210 and the fixed layer 206, and is used to isolate the fixed layer 206 and the free layer 210. Exemplarily, the materials of the non-magnetic isolation layer 208 include MgO and Al2O3; the free layer 210 is made of soft ferromagnetic material, which has relatively low coercive force, high magnetic permeability and high sensitivity to low magnetic fields. The magnetism of the free layer 210 is relatively weak and the magnetic moment is easily reversed. Exemplarily, the materials of the free layer 210 include CoFe, NiFe, NiFeCo, and CoFeB.

[0090] The magnetoresistive storage element is a current-controlled component that controls the magnetization direction of the free layer 210 by flowing current through the storage element 102. When the magnetization direction of the free layer 210 is consistent with the magnetization direction of the fixed layer 206, the storage element 102 is in a low-resistance state, and the storage element 102 stores data "0". When the magnetization direction of the free layer 210 is opposite to the magnetization direction of the fixed layer 206, the storage element 102 is in a high-resistance state, and the storage element 102 stores data "1".

[0091] Continue to refer Figure 4 In one embodiment, the memory element 102 further includes a bottom electrode 212 , which is located on the upper surface of the transistor contact structure 110 . It is understood that in some embodiments, the second lead-out structure 204 also serves as the bottom electrode 212 of the memory element 102 .

[0092] Continue to refer Figure 4 In one embodiment, the memory element 102 further includes a top electrode 214 , which is located on the upper surface of the free layer 210 . It is understood that in some embodiments, the memory contact structure 104 also serves as the top electrode 214 of the memory element 102 .

[0093] Continue to refer Figure 4 In other embodiments, the memory element 102 further includes a protection layer 216 covering the sidewalls of the fixed layer 206 and extending along the sidewalls of the fixed layer 206 to cover the sidewalls of the free layer 210. Exemplarily, the material of the protection layer 216 is silicon nitride.

[0094] Continue to refer Figure 1 In one embodiment, the semiconductor structure further includes: a plurality of word line structures 112 and a plurality of global source lines 114 , the word line structures 112 are connected to the gates of the transistors 108 , and the global source lines 114 are connected to the sources of the transistors 108 .

[0095] Figure 5 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in one embodiment. Figure 1 、 5 As shown, the present application also provides a method for preparing a semiconductor structure, comprising:

[0096] S102, providing a substrate, wherein the substrate has a first surface.

[0097] S104 , forming a plurality of storage elements arranged according to a first predetermined pattern on the first surface of the substrate.

[0098] like Figure 1 As shown, a plurality of storage elements 102 are formed on the first surface of the substrate 100 , and the storage elements 102 are arranged on the first surface of the substrate 100 according to a first preset pattern.

[0099] S106 , forming a storage contact structure arranged in a second predetermined pattern on the top of each storage element.

[0100] Specifically, a storage contact structure 104 is formed on each storage element 102, the bottom of the storage contact structure 104 is in contact with the top of the storage element 102, and the top of the storage contact structure 104 is arranged according to a second preset pattern, and the second preset pattern and the first preset pattern are different patterns; wherein, the bottom of the storage contact structure 104 and the top of the storage contact structure 104 are arranged relative to each other, that is, the bottom of the storage contact structure 104 and the top of the storage contact structure 104 are arranged in parallel.

[0101] The method for fabricating the semiconductor structure includes providing a substrate 100 having a first surface, forming a plurality of memory elements 102 arranged according to a first predetermined pattern on the first surface of the substrate 100, and forming a storage contact structure 104 on top of each memory element 102, with the tops of the storage contact structures 104 arranged according to a second predetermined pattern. This arrangement allows device structures arranged according to the second predetermined pattern to be formed on the memory elements 102 arranged according to the first predetermined pattern, eliminating the influence of the arrangement shape of the memory elements 102 on the arrangement or shape of the device structures formed on the memory elements 102, thereby reducing process difficulty and production costs.

[0102] like Figure 2 As shown, in one embodiment, the first preset pattern includes a regular hexagon, and each storage element 102 is located at a vertex position and a center position of the regular hexagon.

[0103] In one embodiment, the bottom of the storage contact structure 104 contacts the top of the storage element 102 , and the bottom of the storage contact structure 104 is arranged according to a first predetermined pattern.

[0104] In one embodiment, the bottom area of ​​the storage contact structure 104 is larger than the top area of ​​the storage element 102. In other embodiments, the bottom area of ​​the storage contact structure 104 is smaller than or equal to the top area of ​​the storage element 102. This configuration ensures close contact between the storage contact structure 104 and the storage element 102 while preventing damage to the storage element 102 during the formation of the storage contact structure 104.

[0105] In one embodiment, the material of the storage contact structure 104 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide and metal silicide, wherein the metal may be tungsten (W), nickel (Ni) or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi).

[0106] like Figure 3 As shown, in one embodiment, the second preset pattern includes an array of multiple rows and columns.

[0107] Continue to refer Figure 1 In one embodiment, the method for preparing the semiconductor structure further includes:

[0108] A plurality of bitline structures 106 are formed on top of the storage contact structures 104. Each bitline structure 106 contacts the top of the storage contact structures 104 in the same column. The bitline structures 106 are straight lines. Exemplarily, the length of the bitline structures 106 along the X-direction is no less than the length of the top of the storage contact structures 104 along the X-direction, and the X-direction intersects the extension direction of the bitline structures 106.

[0109] Figure 6 FIG. 1 is a flow chart of a method for preparing a semiconductor structure in another embodiment. Figure 1 、 Figure 6 As shown, in one embodiment, before step S104, the following steps are further included:

[0110] S202 , forming a plurality of transistors on the first surface of the substrate.

[0111] Specifically, a plurality of transistors 108 are formed on the first surface of the substrate 100, with each transistor 108 corresponding to each memory element 102. In one embodiment, the transistors 108 are arranged in a third predetermined pattern. It is understood that the third predetermined pattern includes the first predetermined pattern and the second predetermined pattern. In practical applications, the arrangement of the transistors 108 can be set as needed. For example, when the transistors 108 are arranged in the first predetermined pattern, the arrangement of the transistors 108 is the same as that of the memory elements 102. When the transistors 108 are arranged in the second predetermined pattern, the arrangement of the transistors 108 is the same as that of the memory contact structures 104.

[0112] S204 , forming a transistor contact structure on each transistor, with the top arranged according to a first preset pattern.

[0113] Specifically, a transistor contact structure 110 is formed on each transistor 108 . The transistor contact structure 110 is in contact with the transistor 108 and the memory element 102 , respectively. The top of the transistor contact structure 110 is arranged according to a first preset pattern.

[0114] In one embodiment, the bottom of the transistor contact structure 110 is arranged according to a third preset pattern, and the bottom of the transistor contact structure 110 and the top of the transistor contact structure 110 are arranged relative to each other, wherein the third preset pattern includes the first preset pattern and the second preset pattern.

[0115] In one embodiment, the area of ​​the top of the transistor contact structure 110 is larger than the area of ​​the bottom of the memory element 102. In other embodiments, the area of ​​the top of the transistor contact structure 110 is smaller than or equal to the area of ​​the bottom of the memory element 102. This configuration can eliminate the impact of process variations on the contact resistance between the transistor contact structure 110 and the memory element 102.

[0116] Figure 7 FIG. 1 is a schematic diagram of a process for forming transistor contact structures on each transistor in an embodiment. Figure 1 、 Figure 7 As shown, in one embodiment, the transistor contact structure 110 includes a first lead-out structure 202 and a second lead-out structure 204, and step S204 includes:

[0117] S302 , forming a first lead-out structure 202 on each transistor 108 , wherein the bottom of the first lead-out structure 202 is in contact with the transistor 108 .

[0118] Specifically, the bottom of the first lead-out structure 202 is in contact with the transistor 108 and is used to lead out the transistor 108; illustratively, the bottom of the first lead-out structure 202 is connected to the drain of the transistor 108 and is used to lead out the drain of the transistor 108. Typically, the area of ​​the bottom of the first lead-out structure 202 is equal to the area of ​​the drain of the transistor 108.

[0119] S304 , forming a second lead-out structure on top of the first lead-out structure, wherein the top of the second lead-out structure contacts the bottom of the storage element.

[0120] Specifically, the bottom of the first lead-out structure 202 is the bottom of the transistor contact structure 110, and the top of the second lead-out structure 204 is the top of the transistor contact structure 110. In this case, the bottom of the first lead-out structure 202 is arranged according to the third preset pattern, and the top of the second lead-out structure 204 is arranged according to the first preset pattern. For example, the bottom of the first lead-out structure 202 is arranged according to the second preset pattern, and the top of the second lead-out structure 204 is arranged according to the first preset pattern; or the bottom of the first lead-out structure 202 and the top of the second lead-out structure 204 are both arranged according to the first preset pattern.

[0121] Figure 8 FIG. 1 is a schematic cross-sectional view of a semiconductor structure after forming a transistor contact mask layer in one embodiment. Figure 9 for Figure 8 A schematic cross-sectional view of the semiconductor structure after forming a transistor contact structure in a corresponding embodiment.

[0122] like Figure 8 、 Figure 9As shown, in the first step, a first contact structure 302, a first conductive film 304 and a transistor contact mask layer 306 are sequentially formed on the substrate 100 on which the transistor 108 is formed, wherein the first contact structure 302 is connected to the drain of the transistor 108, and a first dielectric layer 308 whose upper surface is flush with the upper surface of the first contact structure 302 is filled between adjacent first contact structures 302, the first conductive film 304 is located on the upper surface of the first contact structure 302, and the transistor contact mask layer 306 is located on the first conductive film 304, defining the shape and position of the transistor contact structure 110. In the second step, a portion of the first conductive film 304, a portion of the first contact structure 302, and a portion of the first dielectric layer 308 are removed by etching using the transistor contact mask layer 306 as a mask, thereby obtaining a first lead-out structure 202 consisting of the remaining first contact structure 302 and a second lead-out structure 204 consisting of the remaining first conductive film 304. It will be appreciated that in some embodiments, only the first conductive film 304 and the first contact structure 302 not covered by the transistor contact mask layer 306 are removed by etching, thereby forming the second lead-out structure 204 and the first lead-out structure 202. Next, a second dielectric layer 310, whose upper surface is flush with the upper surface of the second lead-out structure 204, is filled between adjacent second lead-out structures 204.

[0123] In one embodiment, the area of ​​the bottom of the second lead-out structure 204 is not less than the area of ​​the top of the first lead-out structure 202 ; wherein the bottom of the second lead-out structure 204 and the top of the second lead-out structure 204 are arranged opposite to each other.

[0124] In one embodiment, a portion of the first lead-out structure 202 close to the bottom of the second lead-out structure 204 is a trapezoidal structure.

[0125] In one embodiment, the material of the first lead-out structure 202 and the second lead-out structure 204 includes one or more of polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide, wherein the metal may be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); and the metal silicide includes titanium silicide (TiSi). Exemplarily, the material of at least one of the storage contact structure 104, the first lead-out structure 202, and the second lead-out structure 204 is different from the other. For example, the material of the first lead-out structure 202 is different from the materials of the storage contact structure 104 and the second lead-out structure 204. In practical applications, the storage contact structure 104, the first lead-out structure 202, and the second lead-out structure 204 may also be made of the same material as needed.

[0126] In one embodiment, the memory element 102 includes a ferroelectric memory element, a magnetoresistive memory element, a resistive memory element, or a phase change memory element.

[0127] In one embodiment, the bottom of the first lead-out structure 202 is arranged according to the second preset pattern, and the top of the second lead-out structure 204 is arranged according to the first preset pattern.

[0128] Figure 10 for Figure 9 A schematic cross-sectional view of a semiconductor structure after forming a memory element in a corresponding embodiment; Figure 11 for Figure 10 A cross-sectional schematic diagram of a semiconductor structure after forming a bit line mask layer in a corresponding embodiment; Figure 12 for Figure 11 A cross-sectional view of a semiconductor structure after forming a bit line structure in one embodiment. Figure 10 、 Figure 11 、 Figure 12 As shown, in the third step, a storage element 102 is formed on each second lead-out structure 204. Assuming that the storage element 102 is a magnetoresistive storage element, the steps for forming the storage element 102 are as follows: first, a fixed layer structure is formed on the upper surface of the second lead-out structure 204 by a common deposition process, such as a physical vapor deposition process. For example, the fixed layer structure is a stacked structure composed of multiple thin films, including a seed layer (seed layer), [Co(x) / Pt(y)] formed in sequence on the upper surface of the second lead-out structure 204, m stack, Ru or Ir metal layer, [Co(x) / Pt(y)] mThe pinned layer structure is formed by stacking, forming a Ta metal layer, and forming a CoFeB metal layer. A non-magnetic isolation structure and a free layer structure are sequentially formed on the upper surface of the pinned layer structure. For example, the non-magnetic isolation structure is made of MgO and Al2O3, and the free layer structure is made of CoFe, NiFe, NiFeCo, and CoFeB. A thermal annealing process is performed, and the excess free layer structure, non-magnetic isolation structure, and pinned layer structure are removed by photolithography and etching processes, resulting in a free layer 210 consisting of the remaining free layer structure, a non-magnetic isolation layer 208 consisting of the remaining non-magnetic isolation structure, and a pinned layer 206 consisting of the remaining pinned layer structure. Typically, the bottom area of ​​the pinned layer 206 is equal to the top area of ​​the second lead-out structure 204. A protective structure, such as a silicon nitride structure, is then formed on the sidewalls of the pinned layer 206, the non-magnetic isolation layer 208, and the free layer 210. The protective structure extends along the sidewalls of the free layer 210 and covers the upper surface of the free layer 210. Next, a third dielectric structure is formed on the substrate 100. The third dielectric structure is filled between adjacent free layers 210, and the upper surface of the third dielectric structure is higher than the upper surface of the protection structure. Next, the protection structure and the third dielectric structure directly above the free layer 210 are removed through a photolithography and etching process, resulting in a storage contact trench 312 located above the free layer 210, a protection layer 216 formed by the remaining protection structure, and a third dielectric layer 314 formed by the remaining third dielectric structure. Fourth, a storage contact layer 316 is formed in the storage contact trench 312, with its upper surface flush with the upper surface of the third dielectric layer 314. Fifth, a bit line structure layer 318 is formed on the upper surface of the third dielectric layer 314. In the sixth step, a bit line mask layer 320 is formed on the bit line structure layer. The bit line mask layer 320 defines the shape and position of the bit line structure 106 and the storage contact structure 104. In other embodiments, before the fifth step, after forming a storage mask layer for defining the shape and position of the storage contact structure 104 on the upper surface of the third dielectric layer 314, a portion of the storage contact layer 316 is removed by photolithography and etching, resulting in a storage contact structure 104 consisting of the remaining storage contact layer 316. In this case, the bit line mask layer 320 is only used to define the shape and position of the bit line structure 106. In the seventh step, using the bit line mask layer 320 as a mask, an etching process is performed to remove portions of the bit line structure layer, portions of the storage contact layer 316, and portions of the third dielectric layer 314, resulting in a bit line structure 106 consisting of the remaining bit line structure layer and a storage contact structure 104 consisting of the remaining storage contact layer 316. In the eighth step, a fourth dielectric layer 322 having an upper surface flush with the bitline contact structure is formed between adjacent bitline structures 106. Exemplarily, the materials of the first dielectric layer 308, the second dielectric layer 310, the third dielectric layer 314, and the fourth dielectric layer 322 include silicon dioxide, silicon oxynitride, or silicon nitride.

[0129] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0130] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. Although these terms are used interchangeably throughout this specification, they do not necessarily refer to the same embodiment or example.

[0131] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that include: a substrate having a first surface; A plurality of storage elements are located on the first surface of the substrate, and the storage elements are arranged in a first preset pattern; a plurality of storage contact structures corresponding one to each of the storage elements, wherein the bottoms of the storage contact structures are in contact with the tops of the storage elements, and the tops of the storage contact structures are arranged according to a second preset pattern, wherein the bottoms of the storage contact structures and the tops of the storage contact structures are arranged opposite to each other; a plurality of transistors located between the substrate and the memory element, the transistors corresponding to the memory elements one-to-one, and the transistors arranged according to the second preset pattern; A plurality of transistor contact structures are located between the transistor and the memory element, and are in contact with the transistor and the memory element respectively. The tops of the transistor contact structures are arranged according to the first preset pattern.

2. The semiconductor structure according to claim 1, wherein: The first preset pattern includes a regular hexagon, and each of the storage elements is located at a vertex position and a center position of the regular hexagon.

3. The semiconductor structure according to claim 1, wherein: The bottom of the storage contact structure is arranged according to the first preset pattern.

4. The semiconductor structure according to claim 1, wherein: The second preset pattern includes an array of multiple rows and columns.

5. The semiconductor structure according to claim 4, wherein: Also includes: A plurality of bit line structures, any of which contacts the top of the storage contact structure in the same column, and the bit line structure is a straight line. The semiconductor structure according to claim 1 , wherein: The bottom of the transistor contact structure is arranged according to the second preset pattern; Wherein, the bottom of the transistor contact structure and the top of the transistor contact structure are arranged opposite to each other.

7. The semiconductor structure according to claim 1, wherein: The transistor contact structure comprises: a first lead-out structure, wherein a bottom of the first lead-out structure contacts the transistor; a second lead-out structure, wherein a bottom of the second lead-out structure contacts a top of the first lead-out structure, and a top of the second lead-out structure is a top of the transistor contact structure; The bottom of the first lead-out structure and the top of the first lead-out structure are arranged opposite to each other, and the bottom of the second lead-out structure and the top of the second lead-out structure are arranged opposite to each other.

8. The semiconductor structure according to claim 7, wherein: An area of ​​a bottom portion of the second lead-out structure is not smaller than an area of ​​a top portion of the first lead-out structure.

9. The semiconductor structure according to claim 1, wherein: The storage element includes a ferroelectric storage element, a magnetoresistive storage element, a resistive switching storage element or a phase change storage element.

10. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate having a first surface; forming a plurality of transistors on the first surface of the substrate, wherein the transistors are arranged according to a second predetermined pattern; forming a transistor contact structure on each of the transistors, wherein the top of the transistor contact structure is arranged according to a first preset pattern; forming a plurality of memory elements on the transistor contact structure, wherein the memory elements are arranged according to the first predetermined pattern, wherein the transistors correspond to the memory elements one-to-one, and the transistor contact structure contacts the transistors and the memory elements respectively; A storage contact structure is formed on the top of each of the storage elements, and the tops of the storage contact structures are arranged according to the second preset pattern.

11. The preparation method according to claim 10, characterized in that: The first preset pattern includes a regular hexagon, and each of the storage elements is located at a vertex position and a center position of the regular hexagon.

12. The preparation method according to claim 10, characterized in that The bottom of the storage contact structure contacts the top of the storage element, and the bottom of the storage contact structure is arranged according to the first preset pattern; Wherein, the bottom of the storage contact structure is arranged opposite to the top of the storage contact structure.

13. The preparation method according to claim 10, characterized in that The second preset pattern includes an array of multiple rows and columns.

14. The preparation method according to claim 13, characterized in that Also includes: A plurality of bit line structures are formed on the top of the storage contact structure. Any of the bit line structures contacts the top of the storage contact structure in the same column. The bit line structure is a straight line.

15. The preparation method according to claim 10, characterized in that The bottom of the transistor contact structure is arranged according to the second preset pattern; Wherein, the bottom of the transistor contact structure and the top of the transistor contact structure are arranged opposite to each other.

16. The preparation method according to claim 10, characterized in that The transistor contact structure includes a first lead-out structure and a second lead-out structure, and the step of forming a transistor contact structure on each of the transistors includes: forming a first lead-out structure on each of the transistors, wherein a bottom of the first lead-out structure contacts the transistor; forming a second lead-out structure on top of the first lead-out structure, wherein the top of the second lead-out structure contacts the bottom of the storage element; Wherein, the bottom of the first lead-out structure and the top of the first lead-out structure are arranged opposite to each other.

17. The preparation method according to claim 16, characterized in that The area of ​​the bottom of the second lead-out structure is not less than the area of ​​the top of the first lead-out structure; Wherein, the bottom of the second lead-out structure and the top of the second lead-out structure are arranged opposite to each other.

18. The preparation method according to claim 17, characterized in that: The bottom of the first lead-out structure is arranged according to the second preset pattern, and the top of the second lead-out structure is arranged according to the first preset pattern.

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