Differential amplifier circuit

Abstract

A differential amplifier circuit (1) of the present invention includes a differential input circuit (DI), the differential input circuit (DI) including first and second transistors (Q4, Q5), and the differential amplifier circuit (1) amplifies and outputs a differential voltage between a first input voltage (VINP) applied to a control terminal of the first transistor (Q5) and a second input voltage (VINN) applied to a control terminal of the second transistor (Q4). The differential input circuit (DI) includes a P-channel depletion-type transistor (Q10), the P-channel depletion-type transistor (Q10) having a gate connected to the control terminal of the first transistor (Q5) and a source connected to the control terminal of the second transistor (Q4), and operating as a bias current source for the differential amplifier circuit (1).

Description

Technical Field

[0001] The present invention relates to a differential amplifier circuit used in, for example, an error amplifier or a comparator which is a structural element of a DC-DC converter. Background Art

[0002] In recent years, there has been a demand for reducing the power consumption of DC-DC converters. Known technologies for reducing the power consumption of error amplifiers and comparators, components of DC-DC converters, include limiting the bias current supplied to the error amplifier or comparator when the DC-DC converter is under light load, thereby reducing current consumption. Furthermore, increasing the bias current supplied to the error amplifier or comparator when the load is heavy enables faster operation.

[0003] For example, Patent Document 1 discloses a differential amplifier device that optimizes current supply capability in response to the potential difference between input differential signals. The differential amplifier device includes: a differential amplifier having a current drive capability in response to the potential difference between the input voltages; an adjustment unit that outputs an adjustment signal having a voltage amplitude in response to the potential difference between the input voltages; and a current source that adjusts the current drive capability of the differential amplifier in response to the adjustment signal. The differential amplifier device is characterized in that the adjustment unit begins adjusting the voltage value of the adjustment signal when the potential difference between the differential signals exceeds a set value.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-035845 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] However, conventional current switching technologies require the addition of a current source for changing the bias current and a transistor functioning as a switch, resulting in a problem of increasing the circuit area in order to achieve both low current consumption and fast operation.

[0009] Furthermore, if the bias current is to be increased seamlessly in accordance with the load, as is done with LDO (low drop-out) regulators, in the case of a DC-DC converter, the inductor current must be monitored, requiring a dedicated circuit, which still presents the problem of increased circuit area.

[0010] The present invention aims to solve the above problems and achieve both low current consumption and fast operation without increasing the circuit area in a differential amplifier circuit used in an error amplifier or a comparator, which are components of a DC-DC converter.

[0011] Means for solving problems

[0012] A differential amplifier circuit according to one embodiment of the present invention includes a differential input circuit including first and second transistors. The differential amplifier circuit amplifies and outputs a differential voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor.

[0013] The differential input circuit includes a P-channel depletion transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and operates as a bias current source for the differential amplifier circuit.

[0014] Effects of the Invention

[0015] Thus, according to the differential amplifier circuit of the present invention, the differential input circuit includes a P-channel depletion-mode transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and the P-channel depletion-mode transistor operates as a bias current source for the differential amplifier circuit. Therefore, in a differential amplifier circuit used in, for example, an error amplifier or comparator, which is a component of a DC-DC converter, it is possible to achieve both low current consumption and fast operation without increasing the circuit area. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a circuit diagram showing a configuration example of the differential amplifier circuit 1 according to the first embodiment.

[0017] Figure 2 Yes Figure 1 FIG. 1 is a graph showing an example of characteristics of the drain-source current Ids of the P-channel depletion-type MOS transistor Q10 with respect to the source-gate voltage Vgs.

[0018] Figure 3 This is a circuit diagram showing a configuration example of a linear regulator 10 using the differential amplifier circuit 1 according to the second embodiment. DETAILED DESCRIPTION

[0019] Hereinafter, embodiments and modifications of the present invention will be described with reference to the accompanying drawings. The same or similar components are denoted by the same reference numerals.

[0020] (Knowledge and insight of the inventor)

[0021] Embodiments of the present invention relate to error amplifiers or comparators used in DC-DC converters requiring low current consumption and fast operation, and have the following features. This embodiment features a structure that uses a P-channel depletion-mode transistor with a threshold near 0V as a bias current source. The two input terminals of a differential input stage are connected to the gate and source of the P-channel depletion-mode transistor. This structure automatically and seamlessly supplies a current to the circuit in response to the potential difference between the two input terminals.

[0022] Hereinafter, embodiments and modifications of this embodiment will be described in detail with reference to the drawings.

[0023] (Implementation 1)

[0024] Figure 1 1 is a circuit diagram showing a configuration example of the differential amplifier circuit 1 according to the first embodiment. Figure 1 In the figure, differential amplifier circuit 1 is configured to include a differential input circuit DI and a source-grounded amplifier circuit SA. Here, differential input circuit DI includes a current mirror load circuit including P-channel MOS (metal-oxide semiconductor) field-effect transistors (hereinafter referred to as PMOS transistors or MOS transistors) Q1 and Q2, a non-inverting input terminal T1, an inverting input terminal T2, a differential pair of N-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors or MOS transistors) Q4 and Q5, a P-channel depletion-mode MOS field-effect transistor (hereinafter referred to as depletion-mode PMOS transistors or MOS transistors) Q10, and a bias current source circuit including NMOS transistors Q6 and Q8. Furthermore, source-grounded amplifier circuit SA includes a PMOS transistor Q3, an NMOS transistor Q7, and an output terminal T3. Here, three NMOS transistors Q6, Q7, and Q8 form a current mirror circuit CM, which operates as a bias current source for differential amplifier circuit 1 and source-grounded amplifier circuit SA.

[0025] exist Figure 1In the embodiment of the present invention, the power supply voltage VDD is connected to ground via the source and drain of MOS transistor Q1, the drain and source of MOS transistor Q4, and the drain and source of MOS transistor Q6. It is also connected to ground via the source and drain of MOS transistor Q2, the drain and source of MOS transistor Q5, and the drain and source of MOS transistor Q6. Furthermore, the power supply voltage VDD is connected to ground via the source and drain of MOS transistor Q3, and the drain and source of MOS transistor Q7. The gates of MOS transistors Q1 and Q2 are connected to each other and to the drain of MOS transistor Q1. The drain of MOS transistor Q2 is connected to the gate of MOS transistor Q3.

[0026] In the differential input circuit DI, a non-inverting input terminal T1, to which an input voltage VINP is applied, is connected to the gate (control terminal) of a MOS transistor Q5 and the gate (control terminal) of a MOS transistor Q10. Furthermore, an inverting input terminal T2, to which an input voltage VINN is applied, is connected to the gate of a MOS transistor Q4 and the source of a MOS transistor Q10.

[0027] In current mirror circuit CM, the drain of MOS transistor Q10 is connected to the drain of MOS transistor Q8 and to the gates of MOS transistors Q6, Q7, and Q8. The sources of MOS transistors Q6, Q7, and Q8 are grounded. Here, MOS transistors Q6, Q7, and Q8 form a current mirror circuit, and the drain-source currents of MOS transistors Q6 and Q7 flow in proportion to the bias current, which is the drain-source current flowing through MOS transistor Q8.

[0028] The differential amplifier circuit 1 configured as described above subtracts the input voltage VINN input to the inverting input terminal T2 from the input voltage VINP input to the non-inverting input terminal T1 , and amplifies the difference voltage obtained by the subtraction and outputs the voltage as the output voltage VOUT from the output terminal T3 .

[0029] The differential amplifier circuit 1 according to this embodiment is characterized by employing a depletion-type PMOS transistor Q10 as a bias current source for the differential amplifier circuit 1 within a two-stage configuration comprising a differential input circuit DI and a source-grounded amplifier circuit SA, components of a typical error amplifier. Furthermore, to achieve both low current consumption and fast operation, the threshold voltage of the depletion-type PMOS transistor Q10 is preferably close to 0V.

[0030] For example, in the case of a VFM control comparator in a DC-DC converter, the output voltage and the reference voltage are often connected to input terminals T1 and T2, respectively. When the output voltage is higher than the reference voltage, that is, when the gate voltage of depletion-mode PMOS transistor Q10 is higher than its source voltage, depletion-mode PMOS transistor Q10 is turned off, limiting the bias current supplied to differential amplifier circuit 1. When the output voltage is lower than the reference voltage, that is, when the gate voltage of depletion-mode PMOS transistor Q10 is lower than its source voltage, depletion-mode PMOS transistor Q10 is turned on, increasing the bias current supplied to differential amplifier circuit 1. When the output voltage is lower than the reference voltage and the difference is large, the gate-source voltage Vgs of depletion-mode PMOS transistor Q10 increases, further increasing the bias current supplied to differential amplifier circuit 1.

[0031] Figure 2 Yes Figure 1 FIG. 1 is a graph showing an example of the drain-source current Ids characteristic of the depletion-mode PMOS transistor Q10 with respect to the source-gate voltage Vgs (hereinafter referred to as the current-voltage characteristic).

[0032] according to Figure 2 It can be seen that when the source-gate voltage Vgs is -0.2V, according to Figure 2 The drain-source current Ids generated by the current-voltage characteristics is 1 nA. Furthermore, when the source-gate voltage Vgs is 0.2 V, the generated drain-source current Ids is 1 μA. In other words, the generated current varies by the number of bits depending on the magnitude relationship between the gate voltage and source voltage of the depletion-mode PMOS transistor Q10.

[0033] As described above, according to this embodiment, a depletion-mode PMOS transistor Q10 with a threshold near 0V is used as a bias current source for a differential amplifier circuit 1 used in a DC-DC converter requiring low current consumption and fast operation. The two input terminals T1 and T2 of a differential input circuit DI are connected to the gate and source of this depletion-mode PMOS transistor Q10. Consequently, a current corresponding to the potential difference between the two input terminals T1 and T2 is automatically and seamlessly supplied to the differential amplifier circuit 1 via the depletion-mode PMOS transistor Q10. Consequently, in the differential amplifier circuit 1, both low current consumption and fast operation can be achieved without increasing the circuit area.

[0034] (Differences from Patent Document 1)

[0035] Patent Document 1 discloses that, in order to achieve both low current consumption and fast operation, the bias current source of the differential input stage is reduced when the voltage difference of the input differential signals is small, and is increased when the voltage difference of the differential signals is large. This method is similar to the present embodiment in achieving both low current consumption and fast operation. However, as mentioned above, it does not solve the problem of increased circuit area.

[0036] In contrast, in this embodiment, a depletion-type PMOS transistor Q10 with a threshold near 0V is used as the bias current source for differential amplifier circuit 1. The two input terminals T1 and T2 of differential input circuit DI are connected to the gate and source of depletion-type PMOS transistor Q10. Consequently, a current corresponding to the potential difference between the two input terminals T1 and T2 is automatically and seamlessly supplied to differential amplifier circuit 1 via depletion-type PMOS transistor Q10. Consequently, in differential amplifier circuit 1, a component of a DC-DC converter, both low current consumption and fast operation can be achieved without increasing the circuit area.

[0037] (Implementation Method 2)

[0038] Figure 3 This is a circuit diagram of a configuration example of a three-terminal linear regulator 10 using the differential amplifier circuit 1 according to Embodiment 2. The linear regulator 10 is an example of a voltage regulator or a DC-DC converter. A voltage regulator or a DC-DC converter is an example of a power conversion device.

[0039] exist Figure 3 In FIG. 1 , the linear regulator 10 includes an input terminal T11, an output terminal T12, a ground terminal T13, a reference voltage source 11, a differential amplifier circuit 1, an output driver transistor Q20, and voltage-dividing resistors R1 and R2. The output voltage Vout at the output terminal T12 of the linear regulator 10 is divided by the voltage-dividing resistors R1 and R2, and the divided voltage is applied to the non-inverting input terminal of the differential amplifier circuit 1 as a feedback voltage Vfb. A reference voltage Vref from the reference voltage source 11 is applied to the inverting input terminal of the differential amplifier circuit 1. The differential amplifier circuit 1 amplifies the difference voltage (Vfb - Vref) between the non-inverting and inverting input terminals and applies it as a gate control voltage to the gate of the output driver transistor Q20. This amplifies the current flowing through the output driver transistor Q20 and thereby controls the output voltage Vout.

[0040] In the linear regulator 10 configured as described above, an input voltage Vin from an input voltage source 21 is applied to an input terminal T11 of the linear regulator 10 via an input capacitor C1. The linear regulator 10 controls the output voltage Vout so that it reaches a predetermined output voltage Vout. The controlled output voltage Vout is output to a load 22 via an output capacitor C2.

[0041] exist Figure 3 The linear regulator 10 uses Figure 1 The differential amplifier circuit 1 is used as an error amplifier. Therefore, as described above, in the differential amplifier circuit 1 as a component of the DCDC converter, both low current consumption and fast operation can be achieved without increasing the circuit area.

[0042] (Variation)

[0043] In the above embodiment, the P-channel depletion MOS transistor Q10 is used, but the present invention is not limited thereto, and various P-channel depletion transistors may be used.

[0044] In the above embodiment, the differential amplifier circuit 1 is configured using MOS transistors Q1 to Q8 . However, the present invention is not limited thereto, and the differential amplifier circuit may be configured using transistors such as bipolar transistors.

[0045] Industrial applicability

[0046] As described in detail above, in the differential amplifier circuit according to the present invention, the differential input circuit includes a P-channel depletion-mode transistor having a gate connected to the control terminal of the first transistor and a drain connected to the control terminal of the second transistor, and operating as a bias current source for the differential amplifier circuit. Therefore, in a differential amplifier circuit used in, for example, an error amplifier or comparator, which are components of a DC-DC converter, it is possible to achieve both low current consumption and fast operation without increasing the circuit area.

[0047] Description of labels

[0048] 1 Differential amplifier circuit

[0049] 10 Linear Regulator

[0050] 11. Voltage reference

[0051] 21 Input voltage source

[0052] 22 Load

[0053] C1 Input capacitor

[0054] C2 output capacitor

[0055] CM Current Mirror Circuit

[0056] DI differential input circuit

[0057] Q1 to Q8 MOS transistors

[0058] Q10 P-channel depletion-mode MOS transistor (depletion-mode PMOS transistor)

[0059] Q20 Output driver transistor

[0060] R1, R2 voltage divider resistors

[0061] SA source grounded amplifier circuit

[0062] T1 non-inverting input terminal

[0063] T2 reverse input terminal

[0064] T3 output terminal

[0065] T11 input terminal

[0066] T12 output terminal

[0067] T13 ground terminal

Claims

1. A differential amplifier circuit comprising a differential input circuit including first and second transistors, wherein the differential amplifier circuit amplifies and outputs a differential voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor. The differential input circuit includes a P-channel depletion transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and operates as a bias current source for the differential amplifier circuit.

2. The differential amplifier circuit according to claim 1, The first and second transistors are MOS field effect transistors, The P-channel depletion-type transistor is a P-channel depletion-type MOS field-effect transistor.

3. A power conversion device comprising a differential amplifier circuit, The differential amplifier circuit includes a differential input circuit, and the differential input circuit includes a first transistor and a second transistor. The differential amplifier circuit amplifies and outputs a difference voltage between a first input voltage applied to a control terminal of the first transistor and a second input voltage applied to a control terminal of the second transistor. The differential input circuit includes a P-channel depletion transistor having a gate connected to the control terminal of the first transistor and a source connected to the control terminal of the second transistor, and operates as a bias current source for the differential amplifier circuit.

4. The power conversion device according to claim 3, The power conversion device is a voltage stabilizer.

5. The power conversion device according to claim 3, The power conversion device is a DCDC converter.

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