Microelectromechanical microphone with diaphragm groove stiffener and method of manufacture

Abstract

Microelectromechanical (MEMS) microphones having diaphragm trench stiffeners and methods of manufacture are provided. The MEMS microphone includes a flexible plate and a rigid plate mechanically coupled to the flexible plate. The MEMS microphone includes a stop member secured to the rigid plate and extending perpendicularly relative to a surface of the rigid plate opposite a surface of the flexible plate. The stop member limits movement of the flexible plate. The rigid plate includes a reverse bend edge including a first lateral etch stop including a first corner radius and a second lateral etch stop including a second corner radius. The first corner radius is greater than 100 nanometers and the second corner radius is greater than 25 nanometers. Further, a lateral step width between the first corner radius and the second corner radius is less than about 4 microns.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit and priority of the following applications: U.S. Non-Provisional Application Serial No. 17 / 308,340, filed May 5, 2021, entitled “MICROELECTROMECHANICAL MICROPHONE WITH MEMBRANE TRENCH REINFORCEMENTS AND METHOD OF FABRICATION”; U.S. Provisional Application No. 63 / 020,216, filed May 5, 2020, entitled “PROCESS FLOW FOR MEMS MICROPHONE”; and U.S. Provisional Application No. 63 / 066,652, filed August 17, 2020, entitled “PROCESS FLOW FOR MEMS MICROPHONE”. The entire contents of the above applications are expressly incorporated herein by reference. Background Technology

[0003] Microelectromechanical systems (MEMS) are a class of structures and / or devices fabricated using semiconductor-like processes. MEMS structures and / or devices exhibit mechanical properties including the ability to move or deform. Examples of MEMS devices include, but are not limited to, gyroscopes, accelerometers, magnetometers, pressure sensors, radio frequency components, etc. Silicon wafers containing MEMS structures are called MEMS wafers. There are unique challenges in providing MEMS devices and / or structures with improved performance and reliability. Attached Figure Description

[0004] Various non-limiting embodiments are further described with reference to the accompanying drawings, in which:

[0005] Figures 1 to 36 A non-limiting example cross-sectional view of a MEMS microphone undergoing a manufacturing process according to one or more embodiments described herein is shown;

[0006] Figure 37 An example representation of a MEMS microphone according to one or more embodiments described herein is shown;

[0007] Figure 38 Another example representation of a MEMS microphone according to one or more embodiments described herein is shown; and

[0008] Figure 39 Another example representation of a MEMS microphone according to one or more embodiments described herein is shown. Detailed Implementation

[0009] One or more embodiments will now be described more fully below with reference to the accompanying drawings, which illustrate exemplary embodiments. In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of the various embodiments.

[0010] Figures 1 to 36 A non-limiting example cross-sectional view of a MEMS microphone undergoing a manufacturing process according to one or more embodiments described herein is shown.

[0011] Figure 1 A cross-sectional view is shown of a first stage of forming a MEMS microphone according to one or more embodiments described herein. In the first stage, a wafer 102 (e.g., a wafer substrate) may undergo ion implantation. The substrate may include, for example, aluminum, copper, or silicon. Depending on the implementation, the ion implantation of the wafer 102 may be phosphorus ion implantation. Alternatively, ion implantation may be process module bulk doping.

[0012] like Figure 2 As shown, a low-stress silicon nitride thin film (LSN film) can be deposited on wafer 102. More specifically, a first LSN film 2021 can be deposited on a first surface (e.g., first side 204) of wafer 102, and a second LSN film 2022 can be deposited on a second surface (e.g., second side 206) of wafer 102. As shown, the first side 204 and the second side 206 are on opposite sides of wafer 102.

[0013] like Figure 3 As shown, one or more cavities can be etched on the first side 204, the cavities passing through the first LSN film 2021 and entering the wafer 102. For example, three cavities are shown, labeled as first cavity 3021, second cavity 3022, and third cavity 3023. A cavity refers to an opening or recess in a substrate layer (e.g., wafer 102). In the example shown, there are three cavities; however, depending on various implementations, another number of cavities (e.g., one or more) can be formed in the wafer 102. One or more cavities can be etched via a deep reactive ion etching (DRIE) process. In some implementations, one or more cavities can be etched using a first mask (M1).

[0014] Depending on the implementation, the etching of the first cavity 3021 and the second cavity 3022 can be referred to as front cavity etching. Further, in these implementations, the first cavity 3021 can be referred to as the first front cavity, and the second cavity 3022 can be referred to as the second front cavity, or collectively as the front cavity.

[0015] Depending on some implementations, one or more cavities can be annular rings of approximately 4 micrometers (4 μm) capable of absorbing DRIE positioning inaccuracies. Furthermore, one or more cavities can be defined at distances to the diaphragm stop and the lateral etch stop 1 (LES1), which will be discussed in further detail below.

[0016] Figure 4 The diagram illustrates stages of a fabrication process including the deposition of a first oxide layer. According to an embodiment, depositing the first oxide layer may include filling one or more cavities by performing oxide deposition. As shown, a first oxide layer 402 is deposited on a first side 204 of wafer 102. The first oxide layer 402 is deposited over a first LSN film 2021. Furthermore, the first oxide layer 402 may be deposited within one or more cavities (e.g., first cavity 3021, second cavity 3022, and third cavity 3023). As shown, the first oxide layer 402 deposited within one or more cavities is deposited over portions of wafer 102 exposed by one or more cavities. Additionally, the first oxide layer 402 is deposited on the respective sides of one or more cavities, adjacent to wafer 102 and adjacent to the first LSN film 2021. The first oxide layer 402 may include, for example, tetraethyl orthosilicate (TEOS), also known as tetraethoxysilane.

[0017] like Figure 5 As shown, reverse etching of the filling oxide (e.g., the first oxide layer 402) can be performed in the next stage of the manufacturing process. Reverse etching can facilitate etching of one or more portions of the first oxide layer 402 that are not located in regions associated with one or more cavities (e.g., first cavity 3021, second cavity 3022, and third cavity 3023). Examples of etchable portions of the first oxide layer 402 are indicated at first portion 502, second portion 504, third portion 506, and fourth portion 508. First portion 502 represents the left edge of the device (e.g., when viewed from the left edge). Figure 5 The third portion 506 represents the portion between the left edge of the third cavity 3023 and the first cavity 3021. The fourth portion 508 represents the portion between the third cavity 3023 and the right edge of the device (e.g., when viewed from the left edge). The second portion 504 represents the portion between the first cavity 3021 and the second cavity 3022. The third portion 506 represents the portion between the second cavity 3022 and the third cavity 3023. Figure 5 The part between the right edge of the time.

[0018] like Figure 6As shown, reverse etching may include removing the filler oxide (e.g., the first oxide layer 402) via reactive ion etching (RIE) prior to performing the CMP process. During or after the CMP process, one or more portions of the first oxide layer 402 remain in regions corresponding to one or more cavities (e.g., filled cavities), as indicated by the first cavity filled with the first oxide layer 4021, the second cavity filled with the first oxide layer 4022, and the third cavity filled with the first oxide layer 4023.

[0019] The corresponding center of the front cavity is indicated by the first dashed line 602 of the first cavity 3021 and the second dashed line 604 of the second cavity 3022.

[0020] Figure 7 The deposition of base oxide 702 during the next stage of the manufacturing process is illustrated. Base oxide 702 can be deposited over a first LSN film 2021, over a first cavity filled with a first oxide layer 4021, over a second cavity filled with a first oxide layer 4022, and over a third cavity filled with a first oxide layer 4023. Base oxide 702 may include, for example, TEOS.

[0021] It is important to note that the front cavity can reduce capacitive coupling between the diaphragm and the backplate through the body. The front cavity can also reduce signal loss. It should be noted that the example shown includes a decoupling capacitor; however, other decoupling capacitors can be included at different locations.

[0022] Figure 8 The membrane protective layer (MPL) deposition is illustrated. MPL 8021 can be deposited over the base oxide 702 on the first side 204. Furthermore, MPL 8022 can be deposited over the second LSN film 2022 on the second side 206.

[0023] The MPL 8021 can be a polysilicon protective layer on the back side (e.g., the first side 204). The thickness of the MPL 8021 can be approximately 100 nm. In some implementations, the MPL 8021 can be less than approximately 500 nm. Furthermore, the MPL 8021 can help control the vent size (e.g., mitigate the reduction in vent size), thereby protecting the performance at the cutoff frequency.

[0024] MPL 8021 and / or MPL 8022 protect the separator LSN (e.g., first LSN film 2021, second LSN film 2022) from various manufacturing processes, including buffer oxide etching (BOE), and from high-frequency or very-high-frequency (vHF) exposures experienced during various use case scenarios. It should be noted that MPL 8021 and / or MPL 8022 are intermediate layers that will be removed later during the manufacturing process.

[0025] like Figure 9 As shown, structuring of MPL 8021 is performed during or after the deposition of MPL 8021. Structuring of MPL 8021 may include retaining portions of MPL 8021 located above the first cavity 3021, above the second cavity 3022, and above the region between the first cavity 3021 and the second cavity 3022 (or above the first cavity filled with the first oxide layer 4021 and the second cavity filled with the first oxide layer 4022). The retained portion of MPL 8021 is indicated at portion 902. For example, the retained portion of MPL 8021 extends from approximately a first side 904 of the first cavity filled with the first oxide layer 4021 to approximately a second side 906 of the second cavity filled with the first oxide layer 4022. Other portions of MPL 8021 (indicated at portions 908 and 910) are removed during the structuring of MPL 8021. The remainder of MPL 8021 (indicated at part 902) helps prevent the nitride on the diaphragm (which will be deposited later during manufacturing) from being over-etched.

[0026] Depending on the implementation, the center-to-center width of the two front cavities (e.g., between the first dashed line 602 and the second dashed line 604) is approximately 20 micrometers. The cavity etched from the back side is aligned with the corresponding center of the front cavity (which will be about...). Figure 33 (Discussion). Therefore, slight variations (e.g., adding or subtracting half the width of the tolerance at the cavity position during etching) can be tolerated, which can contribute to the manufacturability of the manufacturing process. Thus, some inaccuracies during the manufacturing process and alignment can be absorbed at the front cavity, as provided herein. Otherwise, proper cavity positioning may not be achievable.

[0027] Figure 10 The structuring of the diaphragm stopper according to an embodiment is shown. The structuring of the diaphragm stopper may include at the portion not covered by MPL 8021 or at portions 908 and 910 (see reference). Figure 9 The base oxide 702 is etched at the indicated portion. For example, at portion 908, the first region 1002 and the second region 1004 of the base oxide 702 can be removed. Furthermore, at portion 910, an opening can be made between the right-facing scribe line and the body contact portion (e.g., Figure 10 As shown, creating an opening may include etching or removing the base oxide 702 at the third region 1006 (shown in an enlarged view), the fourth region 1008, and the fifth region 1010. For the diaphragm stopper size, the etching may be in the range of about 0.95 micrometers. The etching should be controlled down to the nitride (e.g., the first LSN film 2021) to provide a limited amount of material upon entry into the release process (which is performed near the end of the manufacturing process), as will be discussed further below.

[0028] The diaphragm stopper can be recessed toward the body (e.g., toward wafer 102). Removing the base oxide 702 in this way to create the diaphragm stopper can reduce stress in the LES1 or suspension region.

[0029] like Figure 11 As shown, a second oxide layer can be deposited. In some cases, the second oxide layer may be referred to as a diaphragm stop spacer. For example, a portion of the second oxide layer (indicated by the second oxide layer 11021) can be deposited over and adjacent to the MPL 8021. Furthermore, the second oxide layer 11021 can be deposited over and adjacent to the base oxide 702 and over the first LSN film 2021. The second oxide layer 11021 can be deposited adjacent to the first side of the MPL 8021 near the first side 904 of the first cavity filled with the first oxide layer 4021 and near the second side of the MPL 8021 near the second side 906 of the second cavity filled with the first oxide layer 4022. The second oxide layer 11021 can be deposited in portions where the base oxide 702 has been removed (e.g., at least one wall (or side) of the first region 1002 where the base oxide is formed, the wall of the second region 1004, the wall of the third region 1006 (see...). Figure 11 (Enlarged view of the indicated area), the wall of the fourth region 1008 and a portion of at least one wall of the fifth region 1010) are adjacent to the base oxide 702 deposited with a second oxide layer 11021.

[0030] In addition, another portion of the second oxide layer (indicated by the second oxide layer 11022) may be deposited on the second side 106 and above the MPL 8021.

[0031] The second oxide layer 11021 may be an intermediate layer used to control the distance between the surface and the diaphragm stop. It should be noted that the diaphragm stop is configured to control the distance to the surface. According to some implementations, the diaphragm stop has a target distance of about 250 nm (plus or minus about 50 nm). The second oxide layer 11021 is an oxide layer that defines the distance during release etching, which will be discussed in further detail below. The second oxide layer 11021 (and the second oxide layer 11022) may include silicon oxide, which may be a TS oxide deposited in the range of about 50 nm to about 100 nm, depending on the fabrication process. In some implementations, the second oxide layer 11021 (and the second oxide layer 11022) may have a target thickness of about 100 nm.

[0032] Figure 12The diagram illustrates the structuring (e.g., opening) of a first lateral etch stop (e.g., lateral etch stop 1). Lateral etch stop structuring may include etching a second oxide layer 11021 and a base oxide 702 in one or more regions. For example, this may be done in the first region 1202 (see...). Figure 12 (Left-side magnified portion) and second region 1204 (see...) Figure 12 The right-hand magnified portion etches the second oxide layer 11021 and the base oxide 702. More specifically, as indicated by the first region 1202 and the second region 1204, the second oxide layer 11021 and the base oxide 702 can be etched down to (or the etching can stop at) the first LSN film 2021. According to some implementations, this etching can be referred to as over-etching. During or after etching, a CMP process can be performed on the exposed first LSN film 2021. According to some implementations, the first LSN film 2021 can include a thickness of approximately 50 nm.

[0033] The lateral etching stop can be structured to meet specific corner radius specifications. For example, the specification could be a corner radius greater than approximately 100 nm. The corner radius region of the first region 1202 is designated as the first corner 1206 (e.g., the first corner radius), and the corner radius region of the second region 1204 is designated as the second corner 1208 (e.g., the second corner radius). The first corner 1206 and the second corner 1208 represent two inner corner radii. The etching process can be designed to provide the desired corner radius.

[0034] Optionally, a second LSN film 2022 enhancement deposition and etching can be performed during this stage of the manufacturing process. Figure 12 (Not shown in the image).

[0035] Figure 13 Optional stages of a fabrication process, including the deposition and structuring (e.g., etching) of a nitride reinforcement layer, are illustrated. For example, a nitride reinforcement layer 13021 may be deposited over and adjacent to the second oxide layer 11021, over and adjacent to the base oxide 702, and over the first LSN film 2021 (at the first side 204). For example, the nitride reinforcement layer 13021 may be deposited adjacent to the base oxide 702 at the walls defined for the first region 1202 and the walls defined for the second region 1204. Furthermore, the nitride reinforcement layer 13021 may be deposited over the first LSN film 2021 at the bottom of the first region 1002 and the bottom of the fifth region 1010.

[0036] This stage of the manufacturing process can be referred to as diaphragm LSN1 deposition. Additionally, a nitride reinforcement layer 13022 can be deposited over the second oxide layer 11022 at the second side 206.

[0037] In addition, such as Figure 14 As shown, a first separator nitride layer can be deposited. For example, a first separator nitride layer 14021 can be deposited above and adjacent to the nitride reinforcement layer 13021. Furthermore, another first separator nitride layer 14022 can be deposited above the nitride reinforcement layer 13022 at the second side 206. The first separator nitride layer can be separator in-situ doped polysilicon (ISDP), which can be deposited and annealed.

[0038] Figure 15 The next stage of the manufacturing process, including etching the first diaphragm nitride layer 14021, is shown. A trench 1502 is formed (etched) in the first diaphragm nitride layer 14021. For example, the first diaphragm nitride layer 14021 can be etched (downward) to the top surface of the nitride reinforcement layer 13021. The trench 1502 may include bottom corners, shown as a first corner 1504 and a second corner 1506. The corners may have a corresponding radius specification greater than about 50 nm. The trench width may be 8 μm or 4 μm reinforced.

[0039] Depending on some implementations, other processes that can be performed include defining the active electrode region and the shielding. Another process may include opening the vent region in the ISDP (8μm). Additionally, annular openings can be used for the body contacts. Furthermore, scribe-lined openings can be performed, leaving edge coverage along the scribe lines. Another process may be defining the die ID.

[0040] like Figure 16 As shown, an oxide reinforcing layer 1602 can be deposited above and adjacent to the first membrane nitride layer 14021 and above the nitride reinforcing layer 13021. This step can also be referred to as top reinforcement deposition.

[0041] Figure 17 The structure of the oxide reinforcement layer 1602 is shown. As illustrated, in the enlarged portion, individual portions of the oxide reinforcement layer 1602 can be removed (e.g., etched). After etching, the portion of the oxide reinforcement layer 1602 at the trench 1502 is retained. Figure 17 (In the enlarged portion, indicated by 1702).

[0042] like Figure 18As shown, the next stage of the manufacturing process includes depositing a second separator nitride layer. According to some implementations, the second separator nitride layer can be an LSN thin film. For example, the second separator nitride layer 18021 can be deposited adjacent to and over the first separator nitride layer 14021. Furthermore, the second thin film nitride layer 18021 can be deposited adjacent to a portion of the oxide reinforcement layer 1602 above the trench 1502 and over a portion of the oxide reinforcement layer 1602 above the trench 1502. Additionally, the second separator nitride layer 18021 can be deposited over the first LSN thin film 2021. Furthermore, the second separator nitride layer 18022 can be deposited over the first separator nitride layer 14022 on the second side 206 of the wafer.

[0043] Figure 19 The creation of one or more vents is illustrated. One or more vents can be formed by etching downwards through the second diaphragm nitride layer 18021 and the first diaphragm nitride layer 14021. As shown, one or more vents can be formed, as indicated by the first vent 1902, the second vent 1904, and the third vent 1906. Although three vents are shown and described, in some implementations, an additional number of vents can be formed.

[0044] Next, as Figure 20 As shown, a third oxide layer 2002 is deposited. The third oxide layer 2002 can be deposited over and adjacent to the second membrane nitride layer 18021 and over the first LSN film 2021 (e.g., at the first region 1002 and the fifth region 1010). The third oxide layer may also be referred to as the first gap oxide (e.g., gap oxide 1).

[0045] like Figure 21 As shown, recess formation and second lateral etch stop (LES2) definition can be performed. As indicated, one or more recesses and second lateral etch stops can be formed (e.g., opened) in the third oxide layer 2002. For example, one or more recesses and second lateral etch stops can be formed (e.g., etched) in the third oxide layer 2002. Figure 22 The next stage of the fabrication process, including the deposition of the fourth oxide layer 2202, is shown. The fourth oxide layer 2202 can also be referred to as the air gap oxide 2 deposition.

[0046] Figure 23 An opening is shown in the second lateral etch stop region, which may include structuring and etching. Opening the second lateral etch stop region may include etching the third oxide layer 2002 and the fourth oxide layer 2202.

[0047] There are two corner radii on the lateral etch stop, shown as a first corner 2302 and a second corner 2304. The first corner 2302 may have a radius greater than approximately 100 nm. The second corner 2304 may have a radius greater than 25 nm. Furthermore, the step width 2306 (lateral step width) may be approximately 4 μm. Note that the radius is oriented towards the center of the microphone (indicated within the amplification section 2308).

[0048] The process of forming two radii (e.g., at the first corner 2302 and the second corner 2304) can be a dual-mask process. For example, regions on the two outer edges can be structured. Oxide can then be deposited. Regions on the two inner edges can be defined during or after oxide deposition. Thus, the wide portion is defined first, followed by the narrow trench.

[0049] Figure 24 A backplane nitride underlayer 2402 is shown, which may be an LSN underlayer. The backplane nitride underlayer 2402 may be deposited above and adjacent to the fourth oxide layer 2202 and the corresponding portions adjacent to the third oxide layer 2002.

[0050] The backplane nitride underlayer 2402 can improve robustness at LES 2 specifications (which can be greater than about 50 nm). The backplane nitride underlayer 2402 can improve the strength of the backplane. For example, the strength of nitride can be higher than that of polysilicon in the backplane (e.g., nitrite has a much higher fracture point compared to polysilicon during bending). Therefore, having a nitride underlayer (e.g., backplane nitride underlayer 2402) can improve the strength of the backplane.

[0051] Figure 25 The stages of the fabrication process for depositing the first backplane polysilicon layer are illustrated. The first backplane polysilicon layer 25021 can be deposited above and adjacent to the backplane nitride underlayer 2402. Stress annealing can also be performed. Furthermore, at the second side 206, the first backplane polysilicon layer 25021 can be deposited above the second diaphragm nitride layer 18022. The first backplane polysilicon layer can also be referred to as the top backplane and is part of the rigid plate.

[0052] Figure 26 The deposition, structuring, and etching of the fifth oxide layer are illustrated. The fifth oxide layer can be a stress distribution element, also known as a top backplane stress distribution element. The fifth oxide layer can be deposited over and etched onto the first backplane polysilicon layer 2502 to form two portions of the fifth oxide layer (indicated as fifth oxide layers 26021 and 26022). Depending on some implementations, the stress distribution may include a nitride, oxide, or another material layer.

[0053] During this stage of the manufacturing process, in the two backplate sections (e.g., as about...) Figure 26 The top back panel will be discussed below and will be discussed in more detail. Figure 27 A (small) nitride layer (e.g., fifth oxide layers 26021 and 26022) is added between the second backplate layers to increase the flexural stiffness at the backplate suspension. Stress distributors can help make the overall structure stiffer and more robust compared to structures without stress distributors.

[0054] like Figure 27 As shown, a second polysilicon layer (e.g., a second backplane polysilicon layer 2702) can be deposited to form a second portion of the backplane. The second backplane polysilicon layer 2702 can be deposited over the first backplane polysilicon layer 2502 and the fifth oxide layer (e.g., fifth oxide layers 26021 and 26022). The first backplane polysilicon layer 2502, the fifth oxide layer, and the second backplane polysilicon layer can form a rigid plate.

[0055] Figure 28 The definition (e.g., structuring) of the first backplane polysilicon layer 2502 and the second backplane polysilicon layer 2702 is shown. For example, as indicated at 2802, etching of the first backplane polysilicon layer 2502 and the second backplane polysilicon layer 2702 can be performed. Furthermore, LSN via structuring can be performed.

[0056] like Figure 29 As shown, the opening of contact 1 can be integrated during the next stage of the manufacturing process. The opening of the first contact can be facilitated via oxide etching. For example, the first contact 2902 can be opened to wafer 102 via oxide etching. Furthermore, second contacts 29041 and 29042 can be opened to the body opening of the contact to shield the contact. In this example, the first oxide can be dry etched, and then a nitride layer can be patterned to contact the separator. Figure 30 The LSN etching for the integration of the second contact portion is shown.

[0057] Figure 31The metal deposition structuring and etching are illustrated. One or more portions of metal 3102 can be deposited within one or more second contacts 29041 and 29042. Therefore, metal 3102 can be deposited over and adjacent to the second backplane polysilicon layer 2702, over the first backplane polysilicon layer 2502, and over the nitride reinforcement layer 13021 and the first LSN film 2021 (e.g., in the first contact 2902). Metal 3102 can be etched such that only portions of the metal remain at one or more second contacts. Thus, a first portion of metal 3102 can be deposited on the bottom and sides of the second contact 29041. Furthermore, a second portion of metal 3102 can be deposited on the bottom and sides of the second contact 29042.

[0058] like Figure 32 As shown, during the next stage of the manufacturing process, front-side protection and grinding can be performed. As indicated, a front-side oxide protection 3202 can be deposited over and adjacent to the first backplane polysilicon layer 2502 and metal 3102. After depositing the front-side oxide protection 3202, the wafer can be thinned to a desired thickness. For example, the wafer can be thinned to, for example, 350 micrometers.

[0059] Next, as Figure 33 As shown, back-side cavity definition and etching can be performed. As indicated, front-side resist protection 3302 can be provided. Furthermore, a cavity 3304 can be defined on the back side of the wafer (e.g., the second side 206). Defining the cavity 3304 may include structuring and etching portions of the wafer 102 and corresponding portions of the back-side layers (e.g., the second LSN film 2022, MPL 8022, the second oxide layer 11022, the nitride reinforcement layer 13022, the first diaphragm nitride layer 14022, and the second diaphragm nitride layer 18022).

[0060] Cavity 3304 may be defined between the centers of the respective centers of the front cavities (indicated by the first dashed line 602 of the first cavity 3021 and the second dashed line 604 of the second cavity 3022). Depending on the alternative implementation, photoresist for xenon difluoride (XeF2) polycrystalline silicon may be retained during the silicon removal process.

[0061] Figure 34 The defined structure is shown (e.g., regarding) Figures 1 to 33 The first release of the manufactured structure. (For example...) Figure 35As shown, the first release (or initial release) may include a buffered oxide etch (BOE) pre-release using a buffered oxide, which includes pre-resist removal. This process can be a wet pre-release process. During the BOE pre-release, a long distance within a 20-micron range is etched laterally. During the BOE pre-release, the separator is protected by a thin layer of polycrystalline silicon. The term "release" means that all sacrificial material should be removed. Figure 34 As shown, the resist is removed, and then in the next step, the sacrificial diaphragm protective layer is removed. Figure 36 The protective membrane layer is shown. This can then facilitate a second release of the structure. This may include removing the polysilicon. The polysilicon can be removed during the xenon difluoride process. Subsequently, the front resist is removed. Furthermore, a self-assembled monolayer (SAM) coating can be applied to the structure.

[0062] Figure 37 An example representation of a MEMS microphone 3700 according to one or more embodiments described herein is shown. Front cavities (e.g., a first cavity 3021 and a second cavity 3022) are shown for controlling the bending of a flexible plate toward cavity 3304. Furthermore, the flexible plate does not make contact at the edges of the cavity as it moves toward the cavity. For example, the flexible plate moves or deforms by a pressure wave. Controlling the movement of the flexible plate when it deforms by a pressure wave can improve its robustness. In some implementations, the pressure wave may include a threshold amplitude.

[0063] Additionally, diaphragm stops (shown as first diaphragm stop 3702 and second diaphragm stop 3704) can help control the flexible sheet. Since the microphone may be relatively large, the front diaphragm and diaphragm stops work together to prevent or limit downward movement of the flexible sheet. A lateral etch stop 3706 and a reverse-bent edge with a lateral etch stop 3708 are also shown.

[0064] The MEMS microphone 3700 also indicates the shielded TP contact 3710 and the diaphragm node (raised to TP) 3712. Figure 37 The LSN bottom layer 3714 and recess 3716 are also indicated. In the MEMS microphone 3700, diaphragm trenches separate the active component and shield 3718. Buried oxide stress reduction features 3720 are also provided. Parasitic reduction (MEM-boot) 3722 and body / boot node 3724 are indicated. The MEMS microphone 3700 also includes diaphragm trench oxide on the top reinforcement 3726.

[0065] Figure 38Another example representation of a MEMS microphone 3800 according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. The MEMS microphone 3800 may include one or more components and / or functions of the MEMS microphone 3700, and the MEMS microphone 3700 may include one or more components and / or functions of the MEMS microphone 3800. The MEMS microphone 3800 is similar to the MEMS microphone 3700, but does not include oxide reinforcement (e.g., diaphragm trench oxide on top reinforcement 3726). Note that perforated flexible plates can improve signal strength. Therefore, reinforcement for trenches is provided herein. The reinforcement may be oxide, nitride, or another material.

[0066] Figure 39 Another example representation of a MEMS microphone according to one or more embodiments described herein is shown. For brevity, repeated descriptions of similar elements employed in other embodiments described herein are omitted. MEMS microphone 3900 may include one or more components and / or functions of MEMS microphone 3700 and MEMS microphone 3800, and MEMS microphone 3700 and MEMS microphone 3800 may include one or more components and / or functions of MEMS microphone 3900. MEMS microphone 3900 is similar to MEMS microphone 3800. However, MEMS microphone 3900 includes a bottom LSN reinforcement 3902.

[0067] Throughout this specification, the reference to "one embodiment" or "implementation" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment. Therefore, the phrases "in one embodiment," "in one aspect," or "in an embodiment" appearing in different places throughout this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner.

[0068] Additionally, the terms “example” and “exemplary” are used herein to mean as an instance or illustration. Any implementation or design described herein as “example” or “exemplary” is not necessarily to be construed as being more preferred or advantageous than other implementations or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or clear from the context, “X adopts A or B” is intended to mean any natural inclusive arrangement. That is, if X adopts A; X adopts B; or X adopts both A and B, then “X adopts A or B” is satisfied in any of the foregoing examples. Furthermore, the articles “a” and “an” used in this application and the appended claims should generally be interpreted as meaning “one or more” unless otherwise specified or the context clearly refers to the singular form.

[0069] Furthermore, various embodiments can be implemented as articles, methods, or apparatus using standard programming and / or engineering techniques to produce software, firmware, hardware, or any combination thereof for controlling a computer to implement the disclosed subject matter. The term "article" as used herein is intended to include computer programs accessible from any computer-readable device, machine-readable device, computer-readable carrier, computer-readable medium, machine-readable medium, or computer-readable (or machine-readable) storage / communication medium. For example, computer-readable media may include, but are not limited to: magnetic storage devices, such as hard disks; floppy disks; magnetic stripes; optical discs (e.g., CDs, DVDs, Blu-ray discs). TM (BD); smart cards; flash memory devices (e.g., cards, sticks, key drives); and / or virtual devices emulating storage devices and / or any of the aforementioned computer-readable media. Of course, those skilled in the art will recognize that many modifications can be made to this configuration without departing from the scope or spirit of the various embodiments.

[0070] The above description of the embodiments shown in this disclosure (including those described in the abstract) is not intended to be exhaustive or to limit the disclosed embodiments to their exact forms. Although specific embodiments and examples have been described herein for illustrative purposes, various modifications may be considered within the scope of such embodiments and examples, as will be appreciated by those skilled in the art.

[0071] In this regard, although the subject matter has been described herein with reference to various embodiments and corresponding drawings, it should be understood where applicable that other similar embodiments may be used, or modifications and additions may be made to the described embodiments without departing from the description to perform the same, similar, alternative, or substitute functions of the disclosed subject matter. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, but should be interpreted in breadth and scope in accordance with the appended claims.

Claims

1. A method for manufacturing a microelectromechanical system (MEMS) microphone, comprising: On the front side of the wafer, a first oxide layer is deposited over and adjacent to a silicon nitride film, wherein the silicon nitride film is disposed over the wafer; A protective membrane layer is deposited over the first oxide layer between the first side of the first cavity formed in the wafer and the second side of the second cavity formed in the wafer; A second oxide layer is deposited above and adjacent to the membrane protective layer; A first membrane nitride layer is deposited over the second oxide layer; A polycrystalline silicon layer is deposited over the first membrane nitride layer; A second separator nitride layer is deposited above the polycrystalline silicon separator layer; A third oxide layer is deposited above the second membrane nitride layer; A fourth oxide layer is deposited over the third oxide layer; A backplane nitride underlayer is deposited above and adjacent to the fourth oxide layer and adjacent to the third oxide layer; A first backplane polysilicon layer is deposited above and adjacent to the backplane nitride substrate; A fifth oxide layer is deposited at the corresponding portion of the first backplane polysilicon layer; A second backplane polysilicon layer is deposited over the fifth oxide layer and the first backplane polysilicon layer; Metal is deposited above the second backplane polysilicon layer and above the first backplane polysilicon layer; A cavity is defined on the back side of the wafer to create a defined structure; Perform the first release of the defined structure; Remove the protective layer of the diaphragm; Perform the second release of the defined structure; and Deposit self-assembled single-layer coating.

2. The method according to claim 1, further comprising: Before depositing the first membrane nitride layer, a nitride reinforcement layer is deposited above and adjacent to the second oxide layer; as well as The nitride reinforcement layer is defined.

3. The method according to claim 1, further comprising: An oxide reinforcement layer is deposited before depositing the second diaphragm nitride layer; as well as The oxide reinforcement layer is defined.

4. The method according to claim 1, wherein, Depositing the membrane polysilicon layer also includes defining the membrane polysilicon layer and the region of the membrane polysilicon layer.

5. The method according to claim 4, wherein, The limitations include creating one or more vents and active electrodes.

6. The method according to claim 1, wherein, Depositing the second oxide layer also includes openings for a first lateral etch stop, wherein the corner radius of the first lateral etch stop is greater than 100 nanometers.

7. The method according to claim 1, wherein, Depositing the fourth oxide layer includes openings for lateral etch stops, and the openings for lateral etch stops include etching a first corner radius and a second corner radius.

8. The method according to claim 7, wherein, Etching the first corner radius includes etching the first corner radius to a radius greater than 100 nanometers.

9. The method according to claim 7, wherein, Etching the second corner radius includes etching the second corner radius to a radius greater than 25 nanometers.

10. The method according to claim 7, wherein, The step width between the first corner radius and the second corner radius is less than 4 micrometers.

11. A microelectromechanical microphone device, comprising: A flexible sheet, which is deformed by a pressure wave, includes a reverse bending edge, and the reverse bending edge includes a first lateral etching stop and a second lateral etching stop. The first lateral etching stop includes a first corner radius, and the second lateral etching stop includes a second corner radius different from the first corner radius. A rigid plate, mechanically connected to the flexible plate, the rigid plate including an opening that allows the pressure wave to pass through; as well as A blocking member, which is fixed only to the flexible plate and extends perpendicularly to the surface of the flexible plate opposite to the surface of the rigid plate, wherein the blocking member restricts the movement of the flexible plate in response to the pressure wave.

12. The microelectromechanical microphone device according to claim 11, wherein, The first corner radius is greater than 100 nanometers, and the second corner radius is greater than 25 nanometers.

13. The microelectromechanical microphone device according to claim 12, wherein, The width of the transverse step between the first corner radius and the second corner radius is less than 4 micrometers.

14. The microelectromechanical microphone device according to claim 11, wherein, The rigid plate includes: Stress distribution components are located between polysilicon layers.

15. The microelectromechanical microphone device according to claim 14, wherein, The stress distribution element includes a nitride layer.

16. A microelectromechanical microphone device, comprising: A flexible sheet, wherein the flexible sheet is deformed by pressure waves, the flexible sheet includes a reverse bending edge, the reverse bending edge includes a first lateral etching stop and a second lateral etching stop, the first lateral etching stop includes a first corner radius, and the second lateral etching stop includes a second corner radius different from the first corner radius; A rigid plate mechanically coupled to the flexible plate, wherein the rigid plate includes an opening allowing the pressure wave to pass through, and the rigid plate includes a stress distribution element; and A blocking member, which is fixed only to the flexible plate and extends perpendicularly relative to the surface of the flexible plate opposite to the surface of the rigid plate, wherein the blocking member restricts the movement of the flexible plate in response to pressure waves including a threshold amplitude.

17. The microelectromechanical microphone device according to claim 16, wherein, The stress distribution element includes a nitride, oxide, or another material layer.

18. The microelectromechanical microphone device according to claim 16, wherein, The first corner radius is greater than 100 nanometers, and the second corner radius is greater than 25 nanometers.

19. The microelectromechanical microphone device according to claim 16, wherein, The width of the transverse step between the first corner radius and the second corner radius is less than 4 micrometers.

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