A fast-starting bandgap voltage reference

Abstract

The invention discloses a fast-starting bandgap reference voltage source, including a latch-type fast non-overshoot starting circuit, which is used to receive the reference voltage fed back by the reference output circuit when the circuit is powered on, so that the bandgap reference voltage source can enter a normal working state without overshoot; a PTAT current generating circuit, which is used to provide a first-order positive temperature coefficient current for the reference output circuit and a positive temperature coefficient bias current for the segmented curvature compensation circuit; a CTAT current generating circuit, which is used to provide a first-order negative temperature coefficient current for the reference output circuit and a negative temperature coefficient bias current for the segmented curvature compensation circuit; a segmented curvature compensation circuit, which is used to perform segmented curvature temperature compensation on the bandgap reference voltage source; and a reference output circuit, which is used to generate a reference voltage that is segmented curvature compensated by the segmented curvature compensation circuit. The invention can improve the starting speed of the starting circuit and solve the starting voltage overshoot phenomenon that is common in traditional starting circuits.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a fast-starting bandgap reference voltage source. Background Art

[0002] For the existing bandgap reference voltage source, the circuit has two stable states: one is the zero current state and the other is the normal working state. In order to get rid of the degenerate state of zero current, a startup circuit needs to be designed. The existing startup circuit technology makes the bandgap reference voltage reach output stability slowly and has overshoot phenomenon.

[0003] The traditional bandgap reference voltage source performs first-order temperature compensation on the emitter junction voltage VBE of the transistor to reduce the temperature coefficient, thereby reducing the impact of temperature changes on the reference voltage. However, due to the existence of high-order temperature terms, it cannot meet the requirements of high-precision integrated circuit systems. In order to improve the performance of the bandgap reference voltage source, people have tried a variety of technologies to compensate for high-order temperature terms to reduce the temperature coefficient of the reference source.

[0004] For a bandgap reference voltage source, there are usually two stable states: one is the zero current state, and the other is the normal working state. The function of the startup circuit is to enable the bandgap reference to enter the normal working state when the circuit is powered on. The traditional startup circuit makes the bandgap reference voltage reach output stability slowly and has overshoot. Therefore, it is necessary to design a startup circuit with faster startup time and less overshoot.

[0005] The traditional bandgap reference voltage source performs first-order temperature compensation on the emitter junction voltage VBE of the transistor to reduce the temperature coefficient, thereby reducing the impact of temperature changes on the reference voltage. However, due to the existence of high-order temperature terms, it cannot meet the requirements of high-precision integrated circuit systems. In order to improve the performance of the bandgap reference voltage source, people have tried a variety of technologies to compensate for high-order temperature terms to reduce the temperature coefficient of the reference source, such as adding feedback structures and designing temperature compensation circuits.

[0006] The traditional startup circuit makes the bandgap reference voltage take a long time to reach output stability and has voltage overshoot. In order to make the bandgap reference provide a more stable reference voltage, the present invention designs a startup circuit with faster startup time and less overshoot.

[0007] The traditional bandgap reference voltage source performs first-order temperature compensation on the emitter junction voltage VBE of the transistor to reduce the temperature coefficient, thereby reducing the impact of temperature changes on the reference voltage. Due to the existence of high-order temperature terms, it cannot meet the requirements of high-precision integrated circuit systems. The present invention improves the temperature coefficient. Summary of the invention

[0008] In order to solve the above problems existing in the prior art, the present invention provides a fast-starting bandgap reference voltage source. The technical problem to be solved by the present invention is achieved by the following technical solution:

[0009] The present invention provides a fast-starting bandgap reference voltage source, comprising a latch-type fast overshoot-free starting circuit, a PTAT current generating circuit, a CTAT current generating circuit, a reference output circuit and a segmented curvature compensation circuit, wherein:

[0010] The latch-type fast overshoot-free startup circuit is used to receive the reference voltage fed back by the reference output circuit when the circuit is powered on, and to turn on the MOS tubes on the current paths of the PTAT current generating circuit, the CTAT current generating circuit and the segmented curvature compensation circuit through the action of the positive feedback latch structure latch, so that the bandgap reference voltage source can enter a normal working state without overshoot;

[0011] The PTAT current generating circuit is used to provide a first-order positive temperature coefficient current for the reference output circuit and to provide a positive temperature coefficient bias current for the segmented curvature compensation circuit;

[0012] The CTAT current generating circuit is used to provide a first-order negative temperature coefficient current for the reference output circuit and to provide a negative temperature coefficient bias current for the segmented curvature compensation circuit;

[0013] The segmented curvature compensation circuit is used to perform segmented curvature temperature compensation on the bandgap reference voltage source to reduce the temperature coefficient of the reference voltage;

[0014] The reference output circuit is used to generate a reference voltage which is segmented curvature compensated by the segmented curvature compensation circuit.

[0015] In one embodiment of the present invention, the latch-type fast overshoot-free startup circuit includes a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor NM8, an NMOS transistor NM9 and an MOS transistor NM10, wherein:

[0016] The source of the PMOS tube PM1, the source of the PMOS tube PM2 and the source of the PMOS tube PM3 are all connected to the power supply terminal VDD; the source of the NMOS tube NM1, the source of the NMOS tube NM4, the source of the NMOS tube NM5, the source of the NMOS tube NM8, the source of the NMOS tube NM9 and the source of the NMOS tube NM10 are all connected to the ground terminal GND;

[0017] The gate of the PMOS tube PM1 and the gate of the NMOS tube NM1 are both connected to the output end of the reference output circuit; the drain of the PMOS tube PM1 and the drain of the NMOS tube NM1 are both connected to the gate of the NMOS tube NM8;

[0018] The gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM2, the drain of the PMOS tube PM3, the drain of the NMOS tube NM3, the drain of the NMOS tube NM5, the gate of the NMOS tube NM9 and the gate of the NMOS tube NM10; the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM4, the gate of the PMOS tube PM3 and the gate of the NMOS tube NM3; the gate of the NMOS tube NM4 is connected to the gate of the NMOS tube NM1;

[0019] The source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 is connected to the PTAT current generating circuit 102, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM7, the gate of the NMOS tube NM7 and the gate of the NMOS tube NM5 are both connected to the gate of the PMOS tube PM1, the source of the NMOS tube NM6 and the source of the NMOS tube NM7 are both connected to the drain of the NMOS tube NM8, the drain of the NMOS tube NM10 is connected to the CTAT current generating circuit, and the drain of the NMOS tube NM9 is connected to the PTAT current generating circuit.

[0020] In one embodiment of the present invention, the PTAT current generating circuit includes a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, an operational amplifier OP1, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1 and a PNP transistor Q2, wherein:

[0021] The source of the PMOS tube PM4 and the source of the PMOS tube PM5 are both connected to the power supply terminal VDD, the gate of the PMOS tube PM4 is connected to the gate of the PMOS tube PM5, the drain of the NMOS tube NM9, the segmented curvature compensation circuit and the output end of the operational amplifier OP1; the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM6, the drain of the PMOS tube PM5 is connected to the source of the PMOS tube PM7, and the gate of the PMOS tube PM6 is connected to the gate of the PMOS tube PM7, the drain of the PMOS tube PM7 and the segmented curvature compensation circuit;

[0022] The resistor R1 is connected between the drain of the PMOS tube PM6 and the emitter of the PNP type transistor Q1, the resistor R2 and the resistor R3 are connected in series between the drain of the PMOS tube PM7 and the emitter of the PNP type transistor Q2, the negative input end of the operational amplifier OP1 is connected to the emitter of the PNP type transistor Q1, the positive input end of the operational amplifier OP1 is connected between the resistor R2 and the resistor R3, and the base and collector of the PNP type transistor Q1 and the base and collector of the PNP type transistor Q2 are all connected to the ground terminal GND.

[0023] In one embodiment of the present invention, the operational amplifier OP1 includes a PMOS transistor OP1-PM1, a PMOS transistor OP1-PM2, a PMOS transistor OP1-PM3, a PMOS transistor OP1-PM4, a PMOS transistor OP1-PM5, a PMOS transistor OP1-PM6, an NMOS transistor OP1-NM1, an NMOS transistor OP1-NM2, an NMOS transistor OP1-NM3, an NMOS transistor OP1-NM4, an NMOS transistor OP1-NM5, a resistor OP1-R1, a resistor OP1-R2 and a capacitor OP1-C1, wherein:

[0024] The source of the PMOS tube OP1-PM1, the source of the PMOS tube OP1-PM2, the source of the PMOS tube OP1-PM3 and the source of the PMOS tube OP1-PM6 are all connected to the power supply end, and the gate of the PMOS tube OP1-PM1 is connected to the drain of the PMOS tube OP1-PM1, the gate of the PMOS tube OP1-PM2, the gate of the PMOS tube OP1-PM3, the gate of the PMOS tube OP1-PM6 and the drain of the NMOS tube OP1-NM1;

[0025] The drain of the PMOS tube OP1-PM2 is connected to the gate of the NMOS tube OP1-NM1, the gate of the NMOS tube OP1-NM2 and the drain of the NMOS tube OP1-NM2;

[0026] The drain of the PMOS tube OP1-PM3 is connected to the source of the PMOS tube OP1-PM4 and the source of the PMOS tube OP1-PM5, and the drain of the PMOS tube OP1-PM6 is connected to the drain of the NMOS tube OP1-NM5;

[0027] The resistor OP1-R1 is connected between the source of the NMOS transistor OP1-NM1 and the ground terminal GND, and the source of the NMOS transistor OP1-NM1, the source of the NMOS transistor OP1-NM3, the source of the NMOS transistor OP1-NM4 and the source of the NMOS transistor OP1-NM5 are all connected to the ground terminal GND;

[0028] The drain of the PMOS tube OP1-PM4 is simultaneously connected to the drain of the NMOS tube OP1-NM3, the gate of the NMOS tube OP1-NM3 and the gate of the NMOS tube OP1-NM4, the drain of the PMOS tube OP1-PM5 is connected to the drain of the NMOS tube OP1-NM4 and the gate of the NMOS tube OP1-NM5, and the resistor OP1-R2 and the capacitor OP1-C1 are connected in series between the drain of the NMOS tube OP1-NM4 and the drain of the NMOS tube OP1-NM5;

[0029] The gate of the PMOS tube OP1-PM4 serves as the negative input terminal of the operational amplifier OP1, the gate of the PMOS tube OP1-PM5 serves as the positive input terminal of the operational amplifier OP1, and the drain of the PMOS tube OP1-PM6 serves as the output terminal of the operational amplifier OP1.

[0030] In one embodiment of the present invention, the CTAT current generating circuit includes a PMOS transistor PM8, a PMOS transistor PM9, a PMOS transistor PM10, a PMOS transistor PM11, a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM11, a resistor R4, an NPN transistor Q3 and an NPN transistor Q4, wherein:

[0031] The source of the PMOS tube PM8, the source of the PMOS tube PM9 and the source of the PMOS tube PM10 are all connected to the power supply terminal VDD, the gate of the PMOS tube PM8 is connected to the drain of the PMOS tube PM8, the source of the PMOS tube PM11, the reference output circuit and the segmented curvature compensation circuit; the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12, the gate of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10, the gate of the PMOS tube PM5, the drain of the MOS tube NM10, the reference output circuit and the segmented curvature compensation circuit; the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12; the drain of the PMOS tube PM10 is connected to the source of the PMOS tube PM13;

[0032] The gate of the PMOS transistor PM11 is connected to the drain of the PMOS transistor PM11, the drain of the NMOS transistor NM11, the reference output circuit and the segmented curvature compensation circuit;

[0033] The gate of the PMOS tube PM12 is connected to the gate of the PMOS tube PM13, the gate of the PMOS tube PM7, the reference output circuit and the segmented curvature compensation circuit; the drain of the PMOS tube PM12 is connected to the emitter of the NPN transistor Q3, the drain of the PMOS tube PM13 is connected to the gate of the MOS tube NM11 and the emitter of the NPN transistor Q4, the resistor R4 is connected between the source of the MOS tube NM11 and the ground terminal GND, the base of the NPN transistor Q3 and the base of the NPN transistor Q4 are both connected to the source of the MOS tube NM11, and the collector of the NPN transistor Q3 and the collector of the NPN transistor Q4 are both connected to the ground terminal GND.

[0034] In one embodiment of the present invention, the reference output circuit includes a PMOS transistor PM14, a PMOS transistor PM15, a PMOS transistor PM16, a PMOS transistor PM17 and a digital trimming resistor trim1, wherein:

[0035] The source of the PMOS tube PM14 and the source of the PMOS tube PM15 are both connected to the power supply terminal VDD, the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM8, the drain of the PMOS tube PM14 is connected to the source of the PMOS tube PM16, the gate of the PMOS tube PM15 is connected to the gate of the PMOS tube PM9 and the segmented curvature compensation circuit, the drain of the PMOS tube PM15 is connected to the source of the PMOS tube PM17, the gate of the PMOS tube PM17 is connected to the gate of the PMOS tube PM12 and the segmented curvature compensation circuit, one end of the digital trimming resistor trim1 is simultaneously connected to the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17, and the other end is connected to the ground terminal GND; the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17 are also connected to the gate of the NMOS tube NM5.

[0036] In one embodiment of the present invention, the segmented curvature compensation circuit includes a PMOS transistor PM18, a PMOS transistor PM19, a PMOS transistor PM20, a PMOS transistor PM21, an NMOS transistor NM12, an NMOS transistor NM13, a digital trimming resistor trim2, and a digital trimming resistor trim3, wherein:

[0037] The source of the PMOS tube PM18 and the source of the PMOS tube PM19 are both connected to the power supply terminal VDD, the gate of the PMOS tube PM18 is connected to the gate of the PMOS tube PM14, the gate of the PMOS tube PM19 is connected to the gate of the PMOS tube PM15, the drain of the PMOS tube PM18 is connected to the source of the PMOS tube PM20, and the drain of the PMOS tube PM19 is connected to the source of the PMOS tube PM21;

[0038] The gate of the PMOS tube PM20 is connected to the gate of the PMOS tube PM16, the gate of the PMOS tube PM21 is connected to the gate of the PMOS tube PM17, the drain of the PMOS tube PM20 is connected to the gate of the NMOS tube NM12, the gate of the PMOS tube PM21 is connected to the gate of the NMOS tube NM13, and the drain of the NMOS tube NM12 and the drain of the NMOS tube NM13 are both connected to the drain of the PMOS tube PM16;

[0039] The digital trimming resistor trim2 is connected between the gate of the NMOS tube NM12 and the ground terminal GND, the digital trimming resistor trim3 is connected between the gate of the NMOS tube NM13 and the ground terminal GND, and the source of the NMOS tube NM12 is connected to the ground terminal GND.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] 1. The traditional startup circuit makes it take a long time for the bandgap reference voltage to reach output stability and there is a voltage overshoot phenomenon. The present invention uses two back-to-back inverters, namely PM2 and NM2 and PM3 and NM3, to form a positive feedback latch, so that when the gate potentials of NM6 and NM7 are different, the gate potentials of NM9 and NM10 change rapidly, thereby improving the startup speed of the startup circuit and solving the startup voltage overshoot phenomenon commonly existing in the traditional startup circuit.

[0042] 2. The traditional bandgap reference voltage source performs first-order temperature compensation on the emitter junction voltage of the transistor to reduce the temperature coefficient, thereby reducing the impact of temperature changes on the reference voltage. Due to the existence of high-order temperature terms, it cannot meet the requirements of high-precision integrated circuit systems. The present invention introduces resistance adjustment technology into segmented curvature compensation and uses two MOS tubes working in the subthreshold region to perform segmented curvature compensation to obtain a lower temperature coefficient.

[0043] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1It is a module diagram of a fast-start bandgap reference voltage source provided by an embodiment of the present invention;

[0045] Figure 2 It is a specific circuit diagram of a fast-start bandgap reference voltage source provided by an embodiment of the present invention;

[0046] Figure 3 is a circuit diagram of an operational amplifier and a bias circuit thereof provided by an embodiment of the present invention;

[0047] Figure 4 is a circuit diagram of a digital trimming resistor trim1 provided by an embodiment of the present invention;

[0048] Figure 5 is a circuit diagram of digital trimming resistors trim2 and trim3 provided by an embodiment of the present invention;

[0049] Figure 6 1. It is a test result diagram of different process angles of the reference voltage output according to the embodiment of the present invention as the temperature changes;

[0050] Figure 7 This is a startup time simulation test diagram of an embodiment of the present invention;

[0051] Figure 8 1 is a test result diagram of the power supply rejection ratio of an embodiment of the present invention varying with frequency. DETAILED DESCRIPTION

[0052] In order to further explain the technical means and effects adopted by the present invention to achieve the predetermined invention purpose, a fast-start bandgap reference voltage source proposed according to the present invention is described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0053] The above and other technical contents, features and effects of the present invention are clearly presented in the following detailed description of the specific implementation modes in conjunction with the accompanying drawings. Through the description of the specific implementation modes, the technical means and effects adopted by the present invention to achieve the predetermined purpose can be more deeply and specifically understood. However, the attached drawings are only for reference and explanation purposes and are not used to limit the technical solutions of the present invention.

[0054] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants are intended to cover non-exclusive inclusion, so that an article or device including a series of elements includes not only those elements, but also other elements that are not explicitly listed. In the absence of more restrictions, the elements defined by the statement "including one..." do not exclude the existence of other identical elements in the article or device including the elements.

[0055] See also Figure 1 , a module diagram of a fast-starting bandgap reference voltage source provided by an embodiment of the present invention. The bandgap reference voltage source comprises a latch-type fast overshoot-free startup circuit 101, a PTAT current generating circuit 102, a CTAT current generating circuit 103, a reference output circuit 104 and a segmented curvature compensation circuit 105, wherein the latch-type fast overshoot-free startup circuit 101 is used to receive the reference voltage fed back by the reference output circuit 104 when the circuit is powered on, and through the action of the positive feedback latch structure latch, the MOS tubes on the current paths of the PTAT current generating circuit 102, the CTAT current generating circuit 103 and the segmented curvature compensation circuit 105 are turned on, so that the bandgap reference voltage source can enter a normal working state without overshoot; the PTAT current generating circuit 102 is used to provide the reference voltage for the reference output circuit 104. The quasi-output circuit 104 provides a first-order positive temperature coefficient current and provides a positive temperature coefficient bias current for the segmented curvature compensation circuit 105; the CTAT current generating circuit 103 is used to provide a first-order negative temperature coefficient current for the reference output circuit 104 and provides a negative temperature coefficient bias current for the segmented curvature compensation circuit 105; the reference output circuit 104 is used to generate a reference voltage that has been segmented curvature compensated by the segmented curvature compensation circuit 105; the segmented curvature compensation circuit 105 is used to perform temperature compensation for the segmented curvature of the bandgap reference voltage source, introduce resistance trimming technology into the segmented curvature compensation, and use two MOS tubes working in the subthreshold region to perform segmented curvature compensation, thereby effectively improving the temperature coefficient of the reference voltage.

[0056] Further, the latch-type fast overshoot-free startup circuit 101 includes PMOS transistor PM1, PMOS transistor PM2, PMOS transistor PM3, NMOS transistor NM1, NMOS transistor NM2, NMOS transistor NM3, NMOS transistor NM4, NMOS transistor NM5, NMOS transistor NM6, NMOS transistor NM7, NMOS transistor NM8, NMOS transistor NM9 and MOS transistor NM10. The source of the PMOS tube PM1, the source of the PMOS tube PM2 and the source of the PMOS tube PM3 are all connected to the power supply terminal VDD; the source of the NMOS tube NM1, the source of the NMOS tube NM4, the source of the NMOS tube NM5, the source of the NMOS tube NM8, the source of the NMOS tube NM9 and the source of the NMOS tube NM10 are all connected to the ground terminal GND; the gate of the PMOS tube PM1 and the gate of the NMOS tube NM1 are both connected to the output end of the reference output circuit 104; the drain of the PMOS tube PM1 and the drain of the NMOS tube NM1 are both connected to the gate of the NMOS tube NM8.

[0057] The gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM2, the drain of the PMOS tube PM3, the drain of the NMOS tube NM3, the drain of the NMOS tube NM5, the gate of the NMOS tube NM9 and the gate of the NMOS tube NM10; the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM4, the gate of the PMOS tube PM3 and the gate of the NMOS tube NM3; the gate of the NMOS tube NM4 is connected to the gate of the NMOS tube NM1; the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM4, the gate of the PMOS tube PM3 and the gate of the NMOS tube NM3; the gate of the NMOS tube NM4 is connected to the gate of the NMOS tube NM1; the source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM2. The drain of NMOS tube NM6 and the gate of NMOS tube NM6 are connected to the PTAT current generating circuit 102, the source of NMOS tube NM3 is connected to the drain of NMOS tube NM7, the gate of NMOS tube NM7 and the gate of NMOS tube NM5 are both connected to the gate of PMOS tube PM1, the source of NMOS tube NM6 and the source of NMOS tube NM7 are both connected to the drain of NMOS tube NM8, the drain of NMOS tube NM10 is connected to the CTAT current generating circuit 103, and the drain of NMOS tube NM9 is connected to the PTAT current generating circuit 102.

[0058] Further, the PTAT current generating circuit 102 includes a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, an operational amplifier OP1, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2. The source of the PMOS transistor PM4 and the source of the PMOS transistor PM5 are both connected to the power supply terminal VDD, the gate of the PMOS transistor PM4 is connected to the gate of the PMOS transistor PM5, the drain of the NMOS transistor NM9, the segmented curvature compensation circuit 105, and the output end of the operational amplifier OP1; the drain of the PMOS transistor PM4 is connected to the source of the PMOS transistor PM6, the drain of the PMOS transistor PM5 is connected to the source of the PMOS transistor PM7, and the gate of the PMOS transistor PM6 is connected to the gate of the PMOS transistor PM7, the drain of the PMOS transistor PM7, and the segmented curvature compensation circuit 105.

[0059] The resistor R1 is connected between the drain of the PMOS transistor PM6 and the emitter of the PNP transistor Q1, the resistor R2 and the resistor R3 are connected in series between the drain of the PMOS transistor PM7 and the emitter of the PNP transistor Q2, the negative input terminal of the operational amplifier OP1 is connected to the emitter of the PNP transistor Q1, the positive input terminal of the operational amplifier OP1 is connected between the resistor R2 and the resistor R3, and the base and collector of the PNP transistor Q1 and the base and collector of the PNP transistor Q2 are all connected to the ground terminal GND.

[0060] For further information, see Figure 3 The operational amplifier OP1 of the present embodiment includes a PMOS transistor OP1-PM1, a PMOS transistor OP1-PM2, a PMOS transistor OP1-PM3, a PMOS transistor OP1-PM4, a PMOS transistor OP1-PM5, a PMOS transistor OP1-PM6, an NMOS transistor OP1-NM1, an NMOS transistor OP1-NM2, an NMOS transistor OP1-NM3, an NMOS transistor OP1-NM4, an NMOS transistor OP1-NM5, a resistor OP1-R1, a resistor OP1-R2 and a capacitor OP1-C1. The source of the PMOS tube OP1-PM1, the source of the PMOS tube OP1-PM2, the source of the PMOS tube OP1-PM3 and the source of the PMOS tube OP1-PM6 are all connected to the power supply end, and the gate of the PMOS tube OP1-PM1 is connected to the drain of the PMOS tube OP1-PM1, the gate of the PMOS tube OP1-PM2, the gate of the PMOS tube OP1-PM3, the gate of the PMOS tube OP1-PM6 and the drain of the NMOS tube OP1-NM1.

[0061] The drain of the PMOS tube OP1-PM2 is connected to the gate of the NMOS tube OP1-NM1, the gate of the NMOS tube OP1-NM2 and the drain of the NMOS tube OP1-NM2; the drain of the PMOS tube OP1-PM3 is connected to the source of the PMOS tube OP1-PM4 and the source of the PMOS tube OP1-PM5, and the drain of the PMOS tube OP1-PM6 is connected to the drain of the NMOS tube OP1-NM5; the resistor OP1-R1 is connected between the source of the NMOS tube OP1-NM1 and the ground terminal GND, and the source of the NMOS tube OP1-NM1, the source of the NMOS tube OP1-NM3, the source of the NMOS tube OP1-NM4 and the source of the NMOS tube OP1-NM5 are all connected to the ground terminal GND.

[0062] The drain of the PMOS tube OP1-PM4 is connected to the drain of the NMOS tube OP1-NM3, the gate of the NMOS tube OP1-NM3 and the gate of the NMOS tube OP1-NM4 at the same time, the drain of the PMOS tube OP1-PM5 is connected to the drain of the NMOS tube OP1-NM4 and the gate of the NMOS tube OP1-NM5, the resistor OP1-R2 and the capacitor OP1-C1 are connected in series between the drain of the NMOS tube OP1-NM4 and the drain of the NMOS tube OP1-NM5; the gate of the PMOS tube OP1-PM4 serves as the negative input terminal of the operational amplifier OP1, the gate of the PMOS tube OP1-PM5 serves as the positive input terminal of the operational amplifier OP1, and the drain of the PMOS tube OP1-PM6 serves as the output terminal of the operational amplifier OP1.

[0063] Continue to see Figure 2 The CTAT current generating circuit 103 of the present embodiment includes a PMOS transistor PM8, a PMOS transistor PM9, a PMOS transistor PM10, a PMOS transistor PM11, a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM11, a resistor R4, an NPN transistor Q3 and an NPN transistor Q4. The source of the PMOS tube PM8, the source of the PMOS tube PM9 and the source of the PMOS tube PM10 are all connected to the power supply terminal VDD, the gate of the PMOS tube PM8 is connected to the drain of the PMOS tube PM8, the source of the PMOS tube PM11, the reference output circuit 104 and the segmented curvature compensation circuit 105; the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12, the gate of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10, the gate of the PMOS tube PM5, the drain of the MOS tube NM10, the reference output circuit 104 and the segmented curvature compensation circuit 105; the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12; the drain of the PMOS tube PM10 is connected to the source of the PMOS tube PM13.

[0064] The gate of the PMOS transistor PM11 is connected to the drain of the PMOS transistor PM11, the drain of the NMOS transistor NM11, the reference output circuit 104 and the segmented curvature compensation circuit 105; the gate of the PMOS transistor PM12 is connected to the gate of the PMOS transistor PM13, the gate of the PMOS transistor PM7, the reference output circuit 104 and the segmented curvature compensation circuit 105; the drain of the PMOS transistor PM12 is connected to the emitter of the NPN transistor Q3, the drain of the PMOS transistor PM13 is connected to the gate of the MOS transistor NM11 and the emitter of the NPN transistor Q4, the resistor R4 is connected between the source of the MOS transistor NM11 and the ground terminal GND, the base of the NPN transistor Q3 and the base of the NPN transistor Q4 are both connected to the source of the MOS transistor NM11, and the collector of the NPN transistor Q3 and the collector of the NPN transistor Q4 are both connected to the ground terminal GND.

[0065] Furthermore, the reference output circuit 104 includes a PMOS transistor PM14, a PMOS transistor PM15, a PMOS transistor PM16, a PMOS transistor PM17 and a digital trimming resistor trim1, wherein the source of the PMOS transistor PM14 and the source of the PMOS transistor PM15 are both connected to the power supply terminal VDD, the gate of the PMOS transistor PM14 is connected to the gate of the PMOS transistor PM8, the drain of the PMOS transistor PM14 is connected to the source of the PMOS transistor PM16, and the gate of the PMOS transistor PM15 is connected to the gate of the PMOS transistor PM 9 and the segmented curvature compensation circuit 105, the drain of the PMOS tube PM15 is connected to the source of the PMOS tube PM17, the gate of the PMOS tube PM17 is connected to the gate of the PMOS tube PM12 and the segmented curvature compensation circuit 105, one end of the digital trimming resistor trim1 is connected to the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17 at the same time, and the other end is connected to the ground terminal GND, the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17 are also connected to the gate of the NMOS tube NM5.

[0066] The segmented curvature compensation circuit 105 of the present embodiment includes a PMOS transistor PM18, a PMOS transistor PM19, a PMOS transistor PM20, a PMOS transistor PM21, an NMOS transistor NM12, an NMOS transistor NM13, a digital trimming resistor trim2, and a digital trimming resistor trim3. The source of the PMOS transistor PM18 and the source of the PMOS transistor PM19 are both connected to the power supply terminal VDD, the gate of the PMOS transistor PM18 is connected to the gate of the PMOS transistor PM14, the gate of the PMOS transistor PM19 is connected to the gate of the PMOS transistor PM15, the drain of the PMOS transistor PM18 is connected to the source of the PMOS transistor PM20, and the drain of the PMOS transistor PM19 is connected to the source of the PMOS transistor PM21; the gate of the PMOS transistor PM20 is connected to the gate of the PMOS transistor PM16, and the gate of the PMOS transistor PM21 is connected to the gate of the PMOS transistor PM17. The gate of the PMOS tube PM20 is connected to the gate of the NMOS tube NM12, the gate of the PMOS tube PM21 is connected to the gate of the NMOS tube NM13, the drain of the NMOS tube NM12 and the drain of the NMOS tube NM13 are both connected to the drain of the PMOS tube PM16; the digital trimming resistor trim2 is connected between the gate of the NMOS tube NM12 and the ground terminal GND, the digital trimming resistor trim3 is connected between the gate of the NMOS tube NM13 and the ground terminal GND, and the source of the NMOS tube NM12 is connected to the ground terminal GND.

[0067] Specifically, the working principle of the latch-type fast non-overshoot startup circuit of the present embodiment is as follows: when the circuit is powered on, there is a degeneracy point in the circuit (the degeneracy point is two possible states, one is a normal working state, and the other is an abnormal zero current state), the gate voltages of the PMOS transistors PM4, PM5, PM8, PM9, and PM10 are at a high level, close to the power supply terminal VDD, so that the PMOS transistors PM4, PM5, PM8, PM9, and PM10 are turned off, and the gate Vref potential of the NMOS transistor NM8 is at a low level, so that the NMOS transistors NM6 and NMOS transistors NM8 are turned on, and the NMOS transistor NM7 is turned off, and the positive feedback latch structure latch is operated. The gate terminals of the NMOS tubes NM9 and NM10 are high level and turned on, and the gate voltages of the PMOS tubes PM4, PM5, PM8, PM9 and PM10 are pulled down, so that the PMOS tubes PM4, PM5, PM8, PM9 and PM10 are turned on. At this time, the bandgap reference voltage source is separated from the degenerate working point and starts to work normally. When the output of the reference circuit is stable, the gate Vrefb of the NMOS tube NM8 is low level, the NMOS tube NM8 is turned off, the NMOS tubes NM4 and NMOS tubes NM5 are turned on, so that the NMOS tubes NM9 and NMOS tubes NM10 are turned off, the startup circuit is turned off, and the operation of the main circuit is no longer affected, and the startup is completed.

[0068] The PTAT current generating circuit 102 of the present embodiment adopts the operational amplifier clamping method, and its working principle is: the operational amplifier OP1 and the PMOS tubes PM4-PM7 form a deep negative feedback network, which not only improves the power supply suppression capability of the circuit, but also clamps the potential of point A (the negative input terminal of the operational amplifier OP1) and point B (the positive input terminal of the operational amplifier OP1), so that V A =V B , so: V BE1 =V BE2 +R3I PTAT1 , thus obtaining the positive temperature coefficient current I PTAT1 : Among them, V BE1 、V BE2 are the emitter junction voltages of PNP transistors Q1 and Q2 respectively; N is the ratio of the emitter junction area of ​​Q2 to Q1, V T Represents thermal voltage.

[0069] Furthermore, the CTAT current generating circuit 103 adopts a negative feedback structure, and its working principle is: through the negative feedback effect, the voltage drop across the resistor R4 (the voltage at point C) is equal to the voltage V between the base and the emitter of the PNP transistor Q4. BE4 , V BE4 It is a voltage that is negatively correlated with temperature. Dividing it by the resistance value of resistor R4 gives a current that is negatively correlated with temperature, and the negative temperature coefficient current I CTAT1 : Among them, V BE4 is the base voltage of NPN transistor Q4.

[0070] See also Figure 4 and Figure 5 , Figure 4 is a circuit diagram of a digital trimming resistor trim1 provided by an embodiment of the present invention; Figure 5 1 is a circuit diagram of a digital trimming resistor trim2 and trim3 provided by an embodiment of the present invention. The segmented curvature compensation circuit 105 of this embodiment adopts a subthreshold region MOS tube current compensation method. The CTAT current flows through the digital trimming resistor trim2 to generate a CTAT voltage. The voltage acts on the gate voltage of the NMOS tube NM12. The NMOS tube NM12 is always in a subthreshold state, generating a subthreshold current I CTAT2 PTAT current flows through the digital trimming resistor trim3, generating PTAT voltage, which acts on the gate voltage of NMOS tube NM13. NMOS tube NM13 is always in the subthreshold state, generating subthreshold current I PTAT2 I CTAT2 and I PTAT2 The compensation current acts on the digital trimming resistor trim1 to generate a compensation voltage to compensate the reference voltage Vref at low temperature and high temperature respectively.

[0071] In the subthreshold region, the MOS tube leakage current is:

[0072]

[0073] Where ξ is the subthreshold slope correction factor; V TH is the subthreshold voltage of the MOS tube, μ is the mobility, C ox is the gate capacitance per unit area, V T is the thermal voltage constant, V GS is the gate-source voltage of the MOS tube.

[0074] The PMOS tube PM18 and PMOS tube PM20 mirror the CTAT current, which acts on the digital trimming resistor trim2 to generate a CTAT voltage. This voltage makes the NMOS tube NM12 work in a subthreshold state. The lower the temperature, the greater the compensation current. It can be obtained:

[0075]

[0076] The PMOS tube PM19 and PMOS tube PM21 mirror the PTAT current, which acts on the digital trimming resistor trim3 to generate a PTAT voltage. This voltage makes the NMOS tube NM13 work in a subthreshold state. The higher the temperature, the greater the compensation current. It can be obtained:

[0077]

[0078] After the segmented curvature compensation, the reference voltage output by the reference output circuit can be expressed as:

[0079] Vref=(I CTAT1 +I PTAT1 +I CTAT2 +I PTAT2 )trim1.

[0080] For further information, see Figure 6 , Figure 6 This is a test result diagram of different process angles of the output reference voltage of the embodiment of the present invention changing with temperature, in which the horizontal axis is temperature and the vertical axis is the reference voltage Vref. It can be seen that under the three process angles tt, ss, and ff, when the temperature changes from -40°C to 140°C, the reference voltage Vref maintains a very small variation range, and a stable reference output voltage of 2.5V can be achieved under different process angles.

[0081] See also Figure 7 , Figure 7 It is a startup time simulation test diagram of an embodiment of the present invention. In the figure, the horizontal axis represents transient time, the vertical axis represents voltage value, and the three lines are respectively the power supply voltage VDD and the voltage value range of the latch type startup circuit of the embodiment of the present invention and the traditional startup circuit as the power supply voltage VDD is powered on. When the power supply voltage is powered on, the stabilization time of the traditional startup circuit is to reach 119.877ns, and there is an overshoot voltage fluctuation, while the stabilization time of the invented latch type startup circuit is only 60.8939ns, and there is no voltage overshoot during the startup process, so the bandgap reference voltage source can be quickly and stably put into a normal working state.

[0082] See also Figure 8 , Figure 8 1 is a test result diagram of the power supply rejection ratio of an embodiment of the present invention changing with frequency, in which the horizontal axis is the frequency change and the vertical axis is the power supply rejection ratio of the bandgap reference voltage source. Figure 8It can be seen that the power supply rejection ratio is -77.8614dB at 10Hz and -70.0888dB at 1KHz. The bandgap reference voltage source of the embodiment of the present invention can have a good suppression effect on the fluctuation of the power supply voltage.

[0083] The embodiment of the present invention uses two back-to-back inverters to form a positive feedback latch, which improves the startup speed of the startup circuit and can solve the startup voltage overshoot phenomenon that is common in traditional startup circuits. The embodiment of the present invention introduces the resistance adjustment technology into the segmented curvature compensation, uses two MOS tubes working in the subthreshold region to perform segmented curvature compensation, and obtains a lower temperature coefficient.

[0084] In the several embodiments provided by the present invention, it should be understood that the apparatus and method disclosed by the present invention can be implemented in other ways. For example, the apparatus embodiments described above are only illustrative, for example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation, for example, multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed.

[0085] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of hardware plus software functional modules.

[0086] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A fast-start bandgap reference voltage source, characterized in that: The invention comprises a latch-type fast non-overshoot starting circuit (101), a PTAT current generating circuit (102), a CTAT current generating circuit (103), a reference output circuit (104) and a segmented curvature compensation circuit (105), wherein: The latch-type fast non-overshoot startup circuit (101) is used to receive the reference voltage fed back by the reference output circuit (104) when the circuit is powered on, and to turn on the MOS tubes on the current paths of the PTAT current generating circuit (102), the CTAT current generating circuit (103) and the segmented curvature compensation circuit (105) through the action of the positive feedback latch structure latch, so that the bandgap reference voltage source can enter a normal working state without overshoot; The PTAT current generating circuit (102) is used to provide a first-order positive temperature coefficient current for the reference output circuit (104), and to provide a positive temperature coefficient bias current for the segmented curvature compensation circuit (105); The CTAT current generating circuit (103) is used to provide a first-order negative temperature coefficient current for the reference output circuit (104), and to provide a negative temperature coefficient bias current for the segmented curvature compensation circuit (105); The segmented curvature compensation circuit (105) is used to perform segmented curvature temperature compensation on the bandgap reference voltage source to reduce the temperature coefficient of the reference voltage; The reference output circuit (104) is used to generate a reference voltage that has been segmented curvature compensated by the segmented curvature compensation circuit (105); The latch-type fast overshoot-free starting circuit (101) comprises a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, an NMOS transistor NM1, an NMOS transistor NM2, an NMOS transistor NM3, an NMOS transistor NM4, an NMOS transistor NM5, an NMOS transistor NM6, an NMOS transistor NM7, an NMOS transistor NM8, an NMOS transistor NM9 and a MOS transistor NM10, wherein: The source of the PMOS tube PM1, the source of the PMOS tube PM2 and the source of the PMOS tube PM3 are all connected to the power supply terminal VDD; the source of the NMOS tube NM1, the source of the NMOS tube NM4, the source of the NMOS tube NM5, the source of the NMOS tube NM8, the source of the NMOS tube NM9 and the source of the NMOS tube NM10 are all connected to the ground terminal GND; The gate of the PMOS transistor PM1 and the gate of the NMOS transistor NM1 are both connected to the output end of the reference output circuit (104); the drain of the PMOS transistor PM1 and the drain of the NMOS transistor NM1 are both connected to the gate of the NMOS transistor NM8; The gate of the PMOS tube PM2 is connected to the gate of the NMOS tube NM2, the drain of the PMOS tube PM3, the drain of the NMOS tube NM3, the drain of the NMOS tube NM5, the gate of the NMOS tube NM9 and the gate of the NMOS tube NM10; the drain of the PMOS tube PM2 is connected to the drain of the NMOS tube NM2, the drain of the NMOS tube NM4, the gate of the PMOS tube PM3 and the gate of the NMOS tube NM3; the gate of the NMOS tube NM4 is connected to the gate of the NMOS tube NM1; The source of the NMOS tube NM2 is connected to the drain of the NMOS tube NM6, the gate of the NMOS tube NM6 is connected to the PTAT current generating circuit 102, the source of the NMOS tube NM3 is connected to the drain of the NMOS tube NM7, the gate of the NMOS tube NM7 and the gate of the NMOS tube NM5 are both connected to the gate of the PMOS tube PM1, the source of the NMOS tube NM6 and the source of the NMOS tube NM7 are both connected to the drain of the NMOS tube NM8, the drain of the NMOS tube NM10 is connected to the CTAT current generating circuit (103), and the drain of the NMOS tube NM9 is connected to the PTAT current generating circuit (102); The PTAT current generating circuit (102) comprises a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, an operational amplifier OP1, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1 and a PNP transistor Q2, wherein: The source of the PMOS tube PM4 and the source of the PMOS tube PM5 are both connected to the power supply terminal VDD; the gate of the PMOS tube PM4 is connected to the gate of the PMOS tube PM5, the drain of the NMOS tube NM9, the segmented curvature compensation circuit (105) and the output end of the operational amplifier OP1; the drain of the PMOS tube PM4 is connected to the source of the PMOS tube PM6, the drain of the PMOS tube PM5 is connected to the source of the PMOS tube PM7, and the gate of the PMOS tube PM6 is connected to the gate of the PMOS tube PM7, the drain of the PMOS tube PM7 and the segmented curvature compensation circuit (105); The resistor R1 is connected between the drain of the PMOS transistor PM6 and the emitter of the PNP transistor Q1, the resistor R2 and the resistor R3 are connected in series between the drain of the PMOS transistor PM7 and the emitter of the PNP transistor Q2, the negative input terminal of the operational amplifier OP1 is connected to the emitter of the PNP transistor Q1, the positive input terminal of the operational amplifier OP1 is connected between the resistor R2 and the resistor R3, and the base and collector of the PNP transistor Q1 and the base and collector of the PNP transistor Q2 are all connected to the ground terminal GND; The operational amplifier OP1 includes a PMOS tube OP1-PM1, a PMOS tube OP1-PM2, a PMOS tube OP1-PM3, a PMOS tube OP1-PM4, a PMOS tube OP1-PM5, a PMOS tube OP1-PM6, an NMOS tube OP1-NM1, an NMOS tube OP1-NM2, an NMOS tube OP1-NM3, an NMOS tube OP1-NM4, an NMOS tube OP1-NM5, a resistor OP1-R1, a resistor OP1-R2 and a capacitor OP1-C1, wherein: The source of the PMOS tube OP1-PM1, the source of the PMOS tube OP1-PM2, the source of the PMOS tube OP1-PM3 and the source of the PMOS tube OP1-PM6 are all connected to the power supply end, and the gate of the PMOS tube OP1-PM1 is connected to the drain of the PMOS tube OP1-PM1, the gate of the PMOS tube OP1-PM2, the gate of the PMOS tube OP1-PM3, the gate of the PMOS tube OP1-PM6 and the drain of the NMOS tube OP1-NM1; The drain of the PMOS tube OP1-PM2 is connected to the gate of the NMOS tube OP1-NM1, the gate of the NMOS tube OP1-NM2 and the drain of the NMOS tube OP1-NM2; The drain of the PMOS tube OP1-PM3 is connected to the source of the PMOS tube OP1-PM4 and the source of the PMOS tube OP1-PM5, and the drain of the PMOS tube OP1-PM6 is connected to the drain of the NMOS tube OP1-NM5; The resistor OP1-R1 is connected between the source of the NMOS transistor OP1-NM1 and the ground terminal GND, and the source of the NMOS transistor OP1-NM1, the source of the NMOS transistor OP1-NM3, the source of the NMOS transistor OP1-NM4 and the source of the NMOS transistor OP1-NM5 are all connected to the ground terminal GND; The drain of the PMOS tube OP1-PM4 is simultaneously connected to the drain of the NMOS tube OP1-NM3, the gate of the NMOS tube OP1-NM3 and the gate of the NMOS tube OP1-NM4, the drain of the PMOS tube OP1-PM5 is connected to the drain of the NMOS tube OP1-NM4 and the gate of the NMOS tube OP1-NM5, and the resistor OP1-R2 and the capacitor OP1-C1 are connected in series between the drain of the NMOS tube OP1-NM4 and the drain of the NMOS tube OP1-NM5; The gates of the PMOS transistors OP1-PM4 serve as the negative input terminals of the operational amplifier OP1, the gates of the PMOS transistors OP1-PM5 serve as the positive input terminals of the operational amplifier OP1, and the drains of the PMOS transistors OP1-PM6 serve as the output terminals of the operational amplifier OP1; The CTAT current generating circuit (103) comprises a PMOS transistor PM8, a PMOS transistor PM9, a PMOS transistor PM10, a PMOS transistor PM11, a PMOS transistor PM12, a PMOS transistor PM13, an NMOS transistor NM11, a resistor R4, an NPN transistor Q3 and an NPN transistor Q4, wherein: The source of the PMOS tube PM8, the source of the PMOS tube PM9 and the source of the PMOS tube PM10 are all connected to the power supply terminal VDD; the gate of the PMOS tube PM8 is connected to the drain of the PMOS tube PM8, the source of the PMOS tube PM11, the reference output circuit (104) and the segmented curvature compensation circuit (105); the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12; the gate of the PMOS tube PM9 is connected to the gate of the PMOS tube PM10, the gate of the PMOS tube PM5, the drain of the MOS tube NM10, the reference output circuit (104) and the segmented curvature compensation circuit (105); the drain of the PMOS tube PM9 is connected to the source of the PMOS tube PM12; the drain of the PMOS tube PM10 is connected to the source of the PMOS tube PM13; The gate of the PMOS tube PM11 is connected to the drain of the PMOS tube PM11, the drain of the NMOS tube NM11, the reference output circuit (104) and the segmented curvature compensation circuit (105); The gate of the PMOS transistor PM12 is connected to the gate of the PMOS transistor PM13, the gate of the PMOS transistor PM7, the reference output circuit (104) and the segmented curvature compensation circuit (105); the drain of the PMOS transistor PM12 is connected to the emitter of the NPN transistor Q3, the drain of the PMOS transistor PM13 is connected to the gate of the MOS transistor NM11 and the emitter of the NPN transistor Q4, the resistor R4 is connected between the source of the MOS transistor NM11 and the ground terminal GND, the base of the NPN transistor Q3 and the base of the NPN transistor Q4 are both connected to the source of the MOS transistor NM11, and the collector of the NPN transistor Q3 and the collector of the NPN transistor Q4 are both connected to the ground terminal GND; The reference output circuit (104) comprises a PMOS transistor PM14, a PMOS transistor PM15, a PMOS transistor PM16, a PMOS transistor PM17 and a digital trimming resistor trim1, wherein: The source of the PMOS tube PM14 and the source of the PMOS tube PM15 are both connected to the power supply terminal VDD, the gate of the PMOS tube PM14 is connected to the gate of the PMOS tube PM8, the drain of the PMOS tube PM14 is connected to the source of the PMOS tube PM16, the gate of the PMOS tube PM15 is connected to the gate of the PMOS tube PM9 and the segmented curvature compensation circuit (105), the drain of the PMOS tube PM15 is connected to the source of the PMOS tube PM17, the gate of the PMOS tube PM17 is connected to the gate of the PMOS tube PM12 and the segmented curvature compensation circuit (105), one end of the digital trimming resistor trim1 is simultaneously connected to the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17, and the other end is connected to the ground terminal GND; the drain of the PMOS tube PM16 and the drain of the PMOS tube PM17 are also connected to the gate of the NMOS tube NM5; The segmented curvature compensation circuit (105) comprises a PMOS transistor PM18, a PMOS transistor PM19, a PMOS transistor PM20, a PMOS transistor PM21, an NMOS transistor NM12, an NMOS transistor NM13, a digital trimming resistor trim2 and a digital trimming resistor trim3, wherein: The source of the PMOS tube PM18 and the source of the PMOS tube PM19 are both connected to the power supply terminal VDD, the gate of the PMOS tube PM18 is connected to the gate of the PMOS tube PM14, the gate of the PMOS tube PM19 is connected to the gate of the PMOS tube PM15, the drain of the PMOS tube PM18 is connected to the source of the PMOS tube PM20, and the drain of the PMOS tube PM19 is connected to the source of the PMOS tube PM21; The gate of the PMOS tube PM20 is connected to the gate of the PMOS tube PM16, the gate of the PMOS tube PM21 is connected to the gate of the PMOS tube PM17, the drain of the PMOS tube PM20 is connected to the gate of the NMOS tube NM12, the gate of the PMOS tube PM21 is connected to the gate of the NMOS tube NM13, and the drain of the NMOS tube NM12 and the drain of the NMOS tube NM13 are both connected to the drain of the PMOS tube PM16; The digital trimming resistor trim2 is connected between the gate of the NMOS tube NM12 and the ground terminal GND, the digital trimming resistor trim3 is connected between the gate of the NMOS tube NM13 and the ground terminal GND, and the source of the NMOS tube NM12 is connected to the ground terminal GND.

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