High-frequency equivalent circuit, method for modeling high-frequency equivalent circuit, and modeling device

Abstract

An embodiment of the present invention discloses a high-frequency equivalent circuit, a modeling method and a modeling device for the high-frequency equivalent circuit. The circuit includes: an equivalent resistor, an equivalent capacitor and a drain parasitic inductor connected in series, and is connected in parallel with an absorption circuit formed by connecting a parasitic inductor, an absorption resistor and an absorption capacitor in series, and then connected in series with an upper transistor conduction equivalent resistor, a power loop parasitic inductor, a DC link equivalent series resistor, a power supply, a power loop resistor and a shunt resistor. Through the present invention, the problem in the related art that the Cascode-type GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system, is solved, and the technical effects of quantitatively suppressing switching oscillations and matching the parameters for suppressing oscillations, ensuring the safe and reliable operation of the GaN device and fully exerting the high-frequency switching characteristics of the GaN power device are achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of device power conversion, and particularly to a high-frequency equivalent circuit, a modeling method thereof, and a modeling device. Background Art

[0002] In recent years, power devices made of the third-generation wide-bandgap semiconductor material gallium nitride (GaN) have gradually emerged in high-speed and high-power-density power electronics applications. Compared with Si and SiC, GaN power devices have higher switching frequencies, smaller on-resistances, and smaller gate charges, which means that GaN devices have obvious advantages in high-power-density and high-efficiency converters.

[0003] Since depletion-mode GaN devices are normally-on devices, it is not easy to perform driving and fault protection, and they are not suitable for bridge converter applications. To solve this problem, common-source common-gate cascaded gallium nitride (referred to as Cascode-type GaN for short) and enhancement-mode GaN are introduced to endow GaN switches with the characteristics of normally-off devices. Cascode-type GaN is formed by connecting a low-voltage silicon MOSFET in series with a high-voltage depletion-mode GaN, as Figure 1 shown, Figure 1 where all junction capacitances and parasitic inductances are marked. This structure can not only make the device normally off, but also mitigate the Miller effect, improve the switching speed, and reduce the turn-off loss under high-current conditions. Therefore, Cascode-type GaN devices are strong candidates for high-power and high-frequency switching applications. However, the connection between the silicon component Si MOSFET and the GaN device leads to an increase in parasitic inductance, resulting in an excessive oscillation effect at high switching frequencies, thereby limiting high-frequency operation. In addition, during the large-current turn-off process, the inherent capacitance and parasitic inductance between the Si and GaN devices may cause large oscillations during the turn-off process. Multiple parasitic elements in Cascode-type GaN devices and parasitic inductances in external circuits may cause large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference (EMI) noise, and even device breakdown, reducing the reliability of the system. The complex structure of Cascode-type GaN devices and the coupling between multiple parasitic parameters make it very difficult to model the switching oscillation.

[0004] At present, the research on the oscillation modeling of GaN power devices mainly focuses on the switching oscillation modeling of depletion-mode GaN and enhancement-mode GaN. These switching oscillation modeling methods are not fully applicable to Cascode-type GaN power devices. For example, a double-pulse test experiment is used to quantify the influence of circuit parameters on the switching characteristics, and a circuit model based on enhancement-mode GaN devices is established. This model only reflects the influence of various parameters in the switching process on the switching process and losses. In addition, the switching oscillation of Cascode-type GaN devices is closely related to the interaction between low-voltage MOSFETs and high-voltage depletion-mode GaN. Enhancement-mode GaN does not have a Cascode structure, and the modeling method is not applicable to Cascode-type GaN power devices. Another example is the research on the oscillation problem and stability of GaN-based circuits, which gives a method of adding an RC buffer circuit to provide a current path for high-frequency signals to suppress oscillation. Two different sets of RC values are taken to simulate the oscillation suppression effect. For another example, in the research on the characteristics and applications of cascode-type gallium nitride power devices, the parasitic inductance and capacitance of Cascode-type GaN circuits are estimated by actual measurement methods, and a simulation circuit is built to explore the switching oscillation problem of Cascode-type GaN devices. Therefore, there is little research on the oscillation modeling method for Cascode-type GaN bridge converters.

[0005] In the related art, the Cascode-type GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system. No effective solution has been proposed for this problem. Summary of the Invention

[0006] Embodiments of the present invention provide a high-frequency equivalent circuit, a modeling method for the high-frequency equivalent circuit, and a modeling device, so as to at least solve the technical problem that in the related art, the Cascode-type GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system.

[0007] According to an aspect of an embodiment of the present invention, a high-frequency equivalent circuit is provided, including: an equivalent resistance, an equivalent capacitance, a drain parasitic inductance, a parasitic inductance, an absorption resistance, an absorption capacitance, an upper transistor conduction equivalent resistance, a power loop parasitic inductance, a DC link equivalent series resistance, a power supply, a power loop resistance, and a shunt resistance. Among them, the equivalent resistance, the equivalent capacitance, and the drain parasitic inductance are connected in series and are connected in parallel with an absorption circuit formed by connecting the parasitic inductance, the absorption resistance, and the absorption capacitance in series, and then the upper transistor conduction equivalent resistance, the power loop parasitic inductance, the DC link equivalent series resistance, the power supply, the power loop resistance, and the shunt resistance are connected in series.

[0008] Optionally, the first end of the equivalent resistor is connected to the second end of the drain parasitic inductor, the second end of the equivalent resistor is connected to the first end of the equivalent capacitor, the first end of the drain parasitic inductor is connected to the second end of the on-resistance of the upper transistor, and the second end of the equivalent capacitor is connected to the second end of the shunt resistor.

[0009] Optionally, the first end of the parasitic inductor is connected to the line between the drain parasitic inductor and the on-resistance of the upper transistor, the second end of the parasitic inductor is connected to the first end of the snubber resistor, the second end of the snubber resistor is connected to the first end of the snubber capacitor, and the second end of the snubber capacitor is connected to the line between the equivalent capacitor and the shunt resistor.

[0010] Optionally, the first end of the on-resistance of the upper transistor is connected to the second end of the power loop parasitic inductor, the first end of the power loop parasitic inductor is connected to the second end of the DC link equivalent series resistor, the first end of the DC link equivalent series resistor is connected to the first end of the power supply, the second end of the power supply is connected to the first end of the power loop resistor, and the second end of the power loop resistor is connected to the first end of the shunt resistor.

[0011] An embodiment of the present invention provides a method for modeling a high-frequency equivalent circuit, which is applied to the circuit described in any one of the above, and includes: establishing a high-order switching oscillation circuit model with parasitic parameters, where the parasitic parameters at least include: internal cascade parasitic parameters of a cascode gallium nitride device, half-bridge circuit distribution parameters and snubber circuit parameters in a bridge converter including the cascode gallium nitride device; extracting key parasitic parameters of the high-order switching oscillation circuit model by using switching characteristics, and determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, where the key parasitic parameters are parasitic parameters that affect the switching oscillation of the cascode gallium nitride device.

[0012] Optionally, determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation includes: determining an initial high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model; performing a star-delta transformation on the initial high-frequency equivalent circuit model to obtain a transformed initial high-frequency equivalent circuit model, where the star-delta transformation is used to convert a triangular connection network corresponding to the junction capacitance of a silicon element and a high-voltage depletion-mode gallium nitride in the initial high-frequency equivalent circuit model into a star network; performing a network real and imaginary part separation process on the transformed initial high-frequency equivalent circuit to obtain a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

[0013] Optionally, the internal cascaded parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distributed parameters at least include the parasitic inductance of the gate drive loop; the snubber circuit parameters at least include the DC link equivalent series resistance, power loop resistance, shunt resistance, power loop parasitic inductance, and snubber circuit parasitic inductance.

[0014] An embodiment of the present invention provides a modeling device for a high-frequency equivalent circuit, which is applied to the circuit described in any one of the above, and includes: a building module, configured to build a high-order switching oscillation circuit model with parasitic parameters, where the parasitic parameters at least include: the internal cascaded parasitic parameters of a cascode gallium nitride device, the half-bridge circuit distributed parameters and the snubber circuit parameters in a bridge converter including the cascode gallium nitride device; a processing module, configured to extract the key parasitic parameters of the high-order switching oscillation circuit model by using the switching characteristics, and determine the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, where the key parasitic parameters are the parasitic parameters that affect the switching oscillation of the cascode gallium nitride device.

[0015] An embodiment of the present invention provides an electronic device, including: a processor; a memory for storing processor-executable instructions; wherein, the processor is configured to execute the steps of the method described in any one of the above.

[0016] An embodiment of the present invention provides a computer-readable storage medium, on which instructions are stored, and when the instructions are executed by a processor, the steps of the method described in any one of the above are implemented.

[0017] In the embodiments of the present invention, the high-frequency equivalent circuit includes: equivalent resistance, equivalent capacitance, drain parasitic inductance, parasitic inductance, absorption resistance, absorption capacitance, equivalent on-resistance of the upper transistor, parasitic inductance of the power loop, equivalent series resistance of the DC link, power supply, power loop resistance, and shunt resistance. Among them, the equivalent resistance, equivalent capacitance, and drain parasitic inductance are connected in series and are connected in parallel with the absorption circuit formed by connecting the parasitic inductance, absorption resistance, and absorption capacitance in series, and then are connected in series with the equivalent on-resistance of the upper transistor, parasitic inductance of the power loop, equivalent series resistance of the DC link, power supply, power loop resistance, and shunt resistance. Therefore, the high-frequency equivalent circuit in the embodiments of the present invention can accurately reflect the voltage oscillation during the Cascode-type GaN switch in the bridge converter under high-frequency conditions, and can be used for the voltage oscillation analysis of the Cascode-type GaN in the bridge converter at the moment of large-current turn-off. Furthermore, it solves the problem in the related art that the Cascode-type GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system, and achieves the technical effects of quantitatively suppressing switching oscillations, matching and suppressing oscillation parameters, ensuring the safe and reliable operation of the GaN device, and fully exerting the high-frequency switching characteristics of the GaN power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of this application. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0019] Figure 1 is a schematic diagram of a Cascode-type GaN device circuit with parasitic elements provided by the present invention;

[0020] Figure 2 is a schematic diagram of a high-frequency equivalent circuit provided by an embodiment of the present invention;

[0021] Figure 3 is a flowchart of a method for modeling a high-frequency equivalent circuit provided by an embodiment of the present invention;

[0022] Figure 4 is a double-pulse test circuit diagram including parasitic parameters provided by an alternative embodiment of the present invention;

[0023] Figure 5 is a schematic diagram of the derivation process of the Cascode-type GaN high-frequency equivalent circuit provided by an alternative embodiment of the present invention;

[0024] Figure 6 is a comparison diagram of experimental and simulation results provided by an alternative embodiment of the present invention;

[0025] Figure 7It is a schematic diagram of a modeling device for a high-frequency equivalent circuit according to an embodiment of the present invention. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present invention more clear and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0027] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0028] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the accompanying drawings are used to distinguish different objects, rather than to limit a specific order.

[0029] According to one aspect of an embodiment of the present invention, a high-frequency equivalent circuit is provided. Figure 2 It is a schematic diagram of a high-frequency equivalent circuit provided by an embodiment of the present invention. As Figure 2 shown, the high-frequency equivalent circuit includes: an equivalent resistance Req, an equivalent capacitance Ceq, a drain parasitic inductance LD, a parasitic inductance Lsn, an absorption resistance Rsn, an absorption capacitance Csn, an upper transistor on-resistance RDS(ON), a power loop parasitic inductance Lloop, a DC link equivalent series resistance RESR, a power supply v(t), a power loop resistance Rloop, and a shunt resistance Rsens. Among them, the equivalent resistance Req, the equivalent capacitance Ceq, and the drain parasitic inductance LD are connected in series, and are connected in parallel with an absorption circuit formed by connecting the parasitic inductance Lsn, the absorption resistance Rsn, and the absorption capacitance Csn in series, and then connected in series with the upper transistor on-resistance RDS(ON), the power loop parasitic inductance Lloop, the DC link equivalent series resistance RESR, the power supply v(t), the power loop resistance Rloop, and the shunt resistance.

[0030] The above high-frequency equivalent circuit is equivalent to the circuit generated by a bridge converter based on a Cascode-type GaN device.

[0031] It should be noted that the high-frequency equivalent circuit in the embodiments of the present invention can accurately reflect the voltage oscillation of the Cascode GaN switch in the bridge converter under high-frequency conditions, and can be used for the voltage oscillation analysis of the Cascode GaN in the bridge converter at the moment of large-current turn-off. Furthermore, it solves the problem in the related art that the Cascode GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system, and achieves the technical effects of quantitatively suppressing switching oscillations, matching and suppressing oscillation parameters, ensuring the safe and reliable operation of GaN devices, and giving full play to the high-frequency switching characteristics of GaN power devices.

[0032] In an alternative embodiment, the equivalent resistance R eq has its first end connected to the second end of the drain parasitic inductance L D ; the second end of the equivalent resistance R eq is connected to the first end of the equivalent capacitance C eq ; the first end of the drain parasitic inductance L D is connected to the second end of the equivalent on-resistance R DS of the upper transistor; the second end of the equivalent capacitance C eq is connected to the second end of the shunt resistance R sens .

[0033] In an alternative embodiment, the first end of the parasitic inductance L sn is connected to the line between the drain parasitic inductance L D and the equivalent on-resistance R DS of the upper transistor; the second end of the parasitic inductance L sn is connected to the first end of the snubber resistance R sn ; the second end of the snubber resistance R sn is connected to the first end of the snubber capacitance C sn ; the second end of the snubber capacitance C sn is connected to the line between the equivalent capacitance C eq and the shunt resistance R sens .

[0034] In an alternative embodiment, the first end of the equivalent on-resistance R DS(ON) of the upper transistor is connected to the second end of the power loop parasitic inductance L loop ; the first end of the power loop parasitic inductance L loop is connected to the second end of the DC link equivalent series resistance R ESR ; the first end of the DC link equivalent series resistance R ESR is connected to the first end of the power supply v(t); the second end of the power supply v(t) is connected to the first end of the power loop resistance R loop ; the power loop resistance Rloop The second end of is connected to the shunt resistor R of the shunt resistor sens at its first end.

[0035] An embodiment of the present invention provides a method for modeling a high-frequency equivalent circuit, which is applied to the high-frequency equivalent circuit in the above embodiment. Figure 3 As shown in the flowchart of a method for modeling a high-frequency equivalent circuit provided by an embodiment of the present invention, Figure 3 as shown, the method for modeling a high-frequency equivalent circuit provided by an embodiment of the present application includes the following steps:

[0036] S302. Establish a high-order switching oscillation circuit model with parasitic parameters, where the parasitic parameters at least include: internal cascade parasitic parameters of a cascode-type gallium nitride device, half-bridge circuit distribution parameters and absorption circuit parameters in a bridge converter including a cascode-type gallium nitride device;

[0037] Optionally, a high-order switching oscillation circuit model with parasitic parameters can be established for the internal cascade parasitic parameters formed by cascading a low-voltage Si MOSFET and a high-voltage depletion-type GaN in a Cascode-type GaN device, the coupling of multiple distribution parameters of the half-bridge circuit in a bridge converter composed of this device, and the RC absorption circuit parameters.

[0038] S304. Extract the key parasitic parameters of the high-order switching oscillation circuit model by using the switching characteristics, and determine the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, where the key parasitic parameters are the parasitic parameters that affect the switching oscillation of the cascode-type gallium nitride device.

[0039] Optionally, in the bridge circuit, when the lower transistor Q b is completely turned off, the drain-source voltage V ds oscillates most severely. Analyze the high-frequency characteristics of the circuit when the lower transistor Q b is turned off; regard the conducting upper transistor Q a as an equivalent resistor R DS(ON) , and the turned-off lower transistor is equivalent to the junction capacitance of a low-voltage SiMOSFET and a high-voltage depletion-type GaN; in the high-frequency circuit, the impedance of the DC bus support capacitor is much smaller than its equivalent series resistance R ESR , and only consider the equivalent series resistance R ESR .

[0040] Optionally, for a high-order switching oscillation circuit model including parasitic parameters inside and outside the device, by analyzing the switching characteristics, the key parasitic parameters that affect the device switching oscillation are extracted, and then by using the circuit equivalent transformation method, the equivalent of a difficult-to-solve high-order circuit model with a quantitatively solvable low-order model is realized.

[0041] The above key parasitic parameters can be any one or more of the internal cascaded parasitic parameters of the cascode GaN device, the half-bridge circuit distribution parameters and the absorption circuit parameters in the bridge converter including the cascode GaN device.

[0042] In the embodiments of the present invention, it is necessary to establish a high-order switching oscillation circuit model with parasitic parameters, then extract the key parasitic parameters of the high-order switching oscillation circuit model by using the switching characteristics, and through the way of circuit equivalent transformation, so as to determine the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model. The high-frequency equivalent circuit designed according to this high-frequency equivalent circuit model can accurately reflect the voltage oscillation when the Cascode GaN switch in the bridge converter is under high-frequency conditions, and can be used for the voltage oscillation analysis of the Cascode GaN in the bridge converter at the moment of large-current turn-off. Furthermore, it solves the problem in the related technology that the Cascode GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system, and achieves the technical effects of quantitatively suppressing the switching oscillation and matching the oscillation-suppressing parameters, ensuring the safe and reliable operation of the GaN device and giving full play to the high-frequency switching characteristics of the GaN power device.

[0043] It should be noted that due to the complex structure of the Cascode GaN device, it is necessary to establish its high-frequency equivalent circuit model, and then apply the high-frequency equivalent circuit model to the high-frequency equivalent circuit. In addition, the above high-frequency equivalent circuit model couples the internal parasitic parameters of the device and the external circuit parasitic parameters, and is applicable to the high-frequency oscillation analysis of the Cascode GaN device bridge converter, and can be used to determine the optimal RC buffer parameters of the Cascode GaN bridge converter.

[0044] In an optional implementation manner, determining the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through the way of circuit equivalent transformation includes: determining the initial high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model; performing a star-delta transformation on the initial high-frequency equivalent circuit model to obtain the transformed initial high-frequency equivalent circuit model, where the star-delta transformation is used to convert the triangular connection network corresponding to the junction capacitance of the silicon element and the high-voltage depletion-mode GaN in the initial high-frequency equivalent circuit model into a star network; performing a real and imaginary part separation process on the transformed initial high-frequency equivalent circuit to obtain the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

[0045] The above silicon elements include but are not limited to low-voltage Si MOSFETs, etc., and will not be elaborated here one by one.

[0046] Optionally, the delta-connected network of the junction capacitances of the Si MOSFET and the high-voltage depletion-mode GaN can be transformed into a star network through two-star delta transformations; and by the method of separating the real and imaginary parts of the network, the complex impedance network can be equivalent to a low-order circuit containing parasitic inductance L D , resistance R eq and capacitance C eq , so as to equivalent the high-order switching oscillation circuit model with parasitic parameters to a low-order high-frequency equivalent circuit model that can be quantitatively solved.

[0047] In an optional implementation manner, the internal cascaded parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distributed parameters at least include the parasitic inductance of the gate drive loop; the absorption circuit parameters at least include the equivalent series resistance of the DC link, the power loop resistance, the shunt resistance, the power loop parasitic inductance, and the absorption circuit parasitic inductance.

[0048] Optionally, the above internal cascaded parasitic parameters include, but are not limited to, device junction capacitances C GD-Si , C GS-Si , C DS-Si , C GD-GaN , C GSGaN , C DS-GaN , device parasitic inductances L G , L D , L S , bond wire parasitic inductances L int1 , L int2 , L int3 , bond wire resistances R int2 , R int3 ; the above half-bridge circuit distributed parameters include, but are not limited to, the parasitic inductance L of the gate drive loop Ge ; the above absorption circuit parameters, also known as external circuit parasitic parameters, include, but are not limited to, the equivalent series resistance R of the DC link ESR , the power loop resistance R loop , the shunt resistance R sens , the power loop parasitic inductances L P , L n and the coupling of the absorption circuit parasitic inductance L sn .

[0049] Next, an optional implementation manner of the present invention will be illustrated by examples.

[0050] To solve the above technical problems, an optional embodiment of the present invention proposes a high-frequency equivalent circuit model and its modeling method for a bridge converter based on a Cascode-type GaN device. Aiming at the complex structure of the Cascode-type GaN device and the complexity of multiple parasitic parameter couplings, the main parameters are extracted through switch characteristic analysis, and the equivalent circuit transformation is carried out to simplify it into a high-frequency equivalent circuit model with low order that can be quantitatively solved.

[0051] Since the oscillation mechanism of the Cascode-type GaN bridge converter is the same as that found in the double-pulse test, the oscillation of the Cascode-type GaN device is studied through the double-pulse test. Figure 4 The double-pulse test circuit diagram with parasitic parameters provided for an optional embodiment of the present invention is as Figure 4 shown. A high-frequency equivalent circuit model is established through this circuit, and the focus is on studying the oscillation of the drain-source voltage V b in Q b when Q is turned off, and the oscillation is the most serious at this time. DS

[0052] First, set the lower transistor Q b of the bridge circuit as an ideal switch that is completely turned off, and all parasitic elements are regarded as external elements. Then analyze the high-frequency characteristics of the circuit when Q b is turned off: 1) Once Q b is turned off, current commutation occurs. As the current of the inductor L charges the output capacitance of Q a , V GD increases. After exceeding the threshold voltage, Q a starts to conduct. At this time, Q a operating in the active region can be regarded as a on-resistance R DS(ON) in the high-frequency equivalent circuit; 2) The turned-off lower transistor Q b is equivalent to the junction capacitance of Si MOSFET and high-voltage depletion-type GaN; 3) The high-frequency impedance of the DC bus support capacitance is much smaller than its equivalent series resistance R ESR , and only R ESR is considered in the high-frequency circuit.

[0053] Figure 5 The schematic diagram of the derivation process of the Cascode-type GaN high-frequency equivalent circuit provided for an optional embodiment of the present invention is as Figure 5 shown. The high-frequency equivalent circuit obtained based on the above high-frequency characteristic analysis is as Figure 5 shown in (a) of

[0054] Then, through the formula C GD-Si , C GS-Si and C DS-Si ​The delta connection is changed to a star connection, and through the formula L G′ = L G + L Ge 、L loop = L p + L n + L D + L S The simplified circuit is as shown in (b) of Figure 5 .

[0055] The delta connection of C GD-GaN , C GS-GaN and C DS-GaN around the central node B is changed to a star connection, obtaining the circuit shown in (c) of Figure 5 .

[0056]

[0057]

[0058]

[0059] In the above equations, ω OFF In the formula, s = jω OFF is the resonance frequency of the turn-off transient loop.

[0060] Z AB , Z AC and Z BC are the impedances between nodes A and B, A and C, and B and C respectively. Similarly, the equivalent impedances are obtained through the delta-star transformation. Z AB , Z AC and Z BC can be obtained through the following formulas respectively.

[0061] Z AB = sL int1 + Z CD_Si + Z CS_GaN

[0062] Z BC = sL int2 + Z CG_GaN + R int2

[0063] Z AC = sL int3 + Z CS_Si + R int3

[0064] Figure 5 The Z A , Z B and Z shown in (c) ofC It can be obtained through the following formula.

[0065]

[0066]

[0067]

[0068] Z G = R G + s(L G + L Ge ) + Z CG_Si + Z A

[0069]

[0070] In Figure 5 (d) of, the lower transistor Q of the bridge circuit b is converted into three impedances Z O , Z B , Z CD_GaN in series with L S . By extracting the real and imaginary parts of the impedance, Q b b is equivalent to a resistor and a capacitor, and its equivalent resistance and capacitance are:

[0071] R eq = Re(Z B + Z O + Z CD_GaN )

[0072]

[0073] Figure 5 (d) in is the high-frequency oscillation equivalent circuit of the final Cascode-type GaN bridge converter.

[0074] To verify the above embodiments of the present invention, a double-pulse test experiment was carried out on the bridge circuit based on Cascode-type GaN. The device under test was TP65H035WS (650V Cascode-type GaN device) produced by Transphorm, the gate driver was Si8273AB-IS1 produced by Silicon Lab, the current shunt was 0.1Ω SSDN-414 with a bandwidth of 2GHz, and the voltage probe was TPP1000 with a bandwidth of 1GHz.

[0075] The present invention verifies the accuracy of the proposed high-frequency equivalent circuit model. Without adding an RC absorption circuit, the V ds and I ds oscillations predicted by the model were compared with the experimental results.Figure 6 This is a comparison chart of experimental and simulation results provided by an alternative embodiment of the present invention. As Figure 6 shown, (a) is the oscillation waveform of the experimental and simulation results corresponding to V ds , and (b) is the oscillation waveform of the experimental and simulation results corresponding to I ds . It can be seen that the measured oscillation waveforms of V ds and I ds are basically consistent with the predicted oscillation waveforms. Therefore, this model has high accuracy.

[0076] An embodiment of the present invention provides a modeling device for a high-frequency equivalent circuit, which is applied to the high-frequency equivalent circuit in the above embodiment. Figure 7 This is a schematic diagram of the modeling device for a high-frequency equivalent circuit according to an embodiment of the present invention. As Figure 7 shown, the modeling device for this high-frequency equivalent circuit includes: a building module 72 and a processing module 74. The following provides a detailed description of the modeling device for this high-frequency equivalent circuit.

[0077] The building module 72 is used to build a high-order switching oscillation circuit model with parasitic parameters. Among them, the parasitic parameters at least include: the internal cascaded parasitic parameters of the cascode-type gallium nitride device, the half-bridge circuit distribution parameters and the absorption circuit parameters in the bridge converter including the cascode-type gallium nitride device; the processing module 74 is connected to the above building module 72 and is used to extract the key parasitic parameters of the high-order switching oscillation circuit model by using the switching characteristics, and determine the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through the method of circuit equivalent transformation, where the key parasitic parameters are the parasitic parameters that affect the switching oscillation of the cascode-type gallium nitride device.

[0078] In the above embodiment, the modeling device for this high-frequency equivalent circuit can build a high-order switching oscillation circuit model with parasitic parameters, then extract the key parasitic parameters of the high-order switching oscillation circuit model by using the switching characteristics, and through the method of circuit equivalent transformation, thereby determine the high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model. The high-frequency equivalent circuit designed based on this high-frequency equivalent circuit model can accurately reflect the voltage oscillation during the switching of the Cascode-type GaN in the bridge converter under high-frequency conditions, and can be used for the voltage oscillation analysis of the Cascode-type GaN in the bridge converter at the moment of large-current turn-off. Furthermore, it solves the problem in the related technology that the Cascode-type GaN device causes large oscillations at high switching frequencies, resulting in serious voltage overshoot, additional power loss, electromagnetic interference noise, and even device breakdown, reducing the reliability of the system, and achieves the technical effects of quantitatively suppressing switching oscillations and matching the oscillation-suppressing parameters, ensuring the safe and reliable operation of GaN devices and fully exerting the high-frequency switching characteristics of GaN power devices.

[0079] It should be noted here that the above-mentioned establishing module 72 and processing module 74 correspond to steps S302 to S304 in the method embodiment. The examples and application scenarios implemented by the above-mentioned modules and the corresponding steps are the same, but are not limited to the content disclosed in the above-mentioned method embodiment.

[0080] Optionally, the above-mentioned processing module 74 includes: a determining unit, configured to determine an initial high-frequency equivalent circuit model corresponding to a high-order switching oscillation circuit model; a transforming unit, configured to perform a star-delta transformation on the initial high-frequency equivalent circuit model to obtain a transformed initial high-frequency equivalent circuit model, wherein the star-delta transformation is used to convert a triangular connection network corresponding to the junction capacitance of a silicon element and a high-voltage depletion-mode gallium nitride in the initial high-frequency equivalent circuit model into a star network; a processing unit, configured to perform network real and imaginary part separation processing on the transformed initial high-frequency equivalent circuit to obtain a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

[0081] Optionally, the above-mentioned internal cascade parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distribution parameters at least include gate drive loop parasitic inductance; the snubber circuit parameters at least include DC link equivalent series resistance, power loop resistance, shunt resistance, power loop parasitic inductance, and snubber circuit parasitic inductance.

[0082] An embodiment of the present invention provides an electronic device, including: a processor; a memory for storing instructions executable by the processor; wherein the processor is configured to execute the steps of any one of the above-mentioned methods.

[0083] An embodiment of the present invention provides an electronic device, which includes a processor, a memory, and a program stored on the memory and executable on the processor. When the processor executes the program, the following steps are implemented: establishing a high-order switching oscillation circuit model with parasitic parameters, wherein the parasitic parameters at least include: internal cascade parasitic parameters of a cascode gallium nitride device, half-bridge circuit distribution parameters and snubber circuit parameters in a bridge converter including a cascode gallium nitride device; extracting key parasitic parameters of the high-order switching oscillation circuit model by using switching characteristics, and determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model by means of circuit equivalent transformation, wherein the key parasitic parameters are parasitic parameters that affect the switching oscillation of the cascode gallium nitride device.

[0084] Optionally, a high-frequency equivalent circuit model corresponding to a high-order switching oscillation circuit model is determined by means of circuit equivalent transformation, including: determining an initial high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model; performing a star-delta transformation on the initial high-frequency equivalent circuit model to obtain a transformed initial high-frequency equivalent circuit model, where the star-delta transformation is used to transform a triangular connection network corresponding to the junction capacitance of a silicon element and a high-voltage depletion-mode gallium nitride in the initial high-frequency equivalent circuit model into a star network; and performing a network real and imaginary part separation process on the transformed initial high-frequency equivalent circuit to obtain a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

[0085] Optionally, the above internal cascade parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distribution parameters at least include gate drive loop parasitic inductance; the snubber circuit parameters at least include DC link equivalent series resistance, power loop resistance, shunt resistance, power loop parasitic inductance, and snubber circuit parasitic inductance.

[0086] An embodiment of the present invention provides a computer-readable storage medium, on which instructions are stored, and when the instructions are executed by a processor, the steps of the method in any one of the above are implemented.

[0087] Optionally, in this embodiment, the above computer-readable storage medium may be located in any one of the computer terminals in a computer terminal group in a computer network, and / or in any one of the mobile terminals in a mobile terminal group. The above computer-readable storage medium includes a stored program.

[0088] Optionally, when the program runs, it controls the device where the computer-readable storage medium is located to perform the following functions: establishing a high-order switching oscillation circuit model with parasitic parameters, where the parasitic parameters at least include: internal cascade parasitic parameters of a cascode gallium nitride device, half-bridge circuit distribution parameters and snubber circuit parameters in a bridge converter including a cascode gallium nitride device; extracting key parasitic parameters of the high-order switching oscillation circuit model by using switching characteristics, and determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model by means of circuit equivalent transformation, where the key parasitic parameters are parasitic parameters that affect the switching oscillation of the cascode gallium nitride device.

[0089] Optionally, a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model is determined by means of circuit equivalent transformation, including: determining an initial high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model; performing a star-delta transformation on the initial high-frequency equivalent circuit model to obtain a transformed initial high-frequency equivalent circuit model, wherein the star-delta transformation is used to transform the triangular connection network corresponding to the junction capacitance of the silicon element and the high-voltage depletion-mode gallium nitride in the initial high-frequency equivalent circuit model into a star network; and performing network real and imaginary part separation processing on the transformed initial high-frequency equivalent circuit to obtain a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

[0090] Optionally, the above internal cascaded parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distribution parameters at least include the parasitic inductance of the gate drive loop; and the snubber circuit parameters at least include the DC link equivalent series resistance, power loop resistance, shunt resistance, power loop parasitic inductance, and snubber circuit parasitic inductance.

[0091] As described above, only the preferred embodiments of the present invention are given, and they are not intended to limit the protection scope of the present invention.

Claims

1. A high-frequency equivalent circuit, characterized in that, Including: An equivalent resistance, an equivalent capacitance, a drain parasitic inductance, a parasitic inductance, a snubber resistance, a snubber capacitance, an equivalent on-resistance of the upper transistor, a parasitic inductance of the power loop, an equivalent series resistance of the DC link, a power supply, a power loop resistance, and a shunt resistance. Among them, the equivalent resistance, the equivalent capacitance, and the drain parasitic inductance are connected in series, and are connected in parallel with a snubber circuit formed by connecting the parasitic inductance, the snubber resistance, and the snubber capacitance in series, and then the equivalent on-resistance of the upper transistor, the parasitic inductance of the power loop, the equivalent series resistance of the DC link, the power supply, the power loop resistance, and the shunt resistance are connected in series; The first end of the equivalent resistance is connected to the second end of the drain parasitic inductance, the second end of the equivalent resistance is connected to the first end of the equivalent capacitance, the first end of the drain parasitic inductance is connected to the second end of the equivalent on-resistance of the upper transistor, and the second end of the equivalent capacitance is connected to the second end of the shunt resistance; The first end of the parasitic inductance is connected to the line between the drain parasitic inductance and the equivalent on-resistance of the upper transistor, the second end of the parasitic inductance is connected to the first end of the snubber resistance, the second end of the snubber resistance is connected to the first end of the snubber capacitance, and the second end of the snubber capacitance is connected to the line between the equivalent capacitance and the shunt resistance; The first end of the equivalent on-resistance of the upper transistor is connected to the second end of the parasitic inductance of the power loop, the first end of the parasitic inductance of the power loop is connected to the second end of the equivalent series resistance of the DC link, the first end of the equivalent series resistance of the DC link is connected to the first end of the power supply, the second end of the power supply is connected to the first end of the power loop resistance, and the second end of the power loop resistance is connected to the first end of the shunt resistance.

2. A modeling method for a high-frequency equivalent circuit, applied to the circuit described in claim 1, characterized in that, Including: Establishing a high-order switching oscillation circuit model with parasitic parameters, where the parasitic parameters at least include: internal cascade parasitic parameters of a cascode gallium nitride device, half-bridge circuit distribution parameters and snubber circuit parameters in a bridge converter including the cascode gallium nitride device; Extracting key parasitic parameters of the high-order switching oscillation circuit model by using switching characteristics, and determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, where the key parasitic parameters are parasitic parameters that affect the switching oscillation of the cascode gallium nitride device.

3. The method according to claim 2, wherein Determining a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, including: Determining an initial high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model; Performing a star-delta transformation on the initial high-frequency equivalent circuit model to obtain a transformed initial high-frequency equivalent circuit model, where the star-delta transformation is used to convert a triangular connection network corresponding to the junction capacitance of a silicon element and a high-voltage depletion-mode gallium nitride in the initial high-frequency equivalent circuit model into a star network; Performing network real and imaginary part separation processing on the transformed initial high-frequency equivalent circuit to obtain a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model.

4. The method according to claim 2, wherein the internal cascaded parasitic parameters at least include device junction capacitance, device parasitic inductance, bond wire parasitic inductance, and bond wire resistance; the half-bridge circuit distributed parameters at least include the parasitic inductance of the gate drive loop; the snubber circuit parameters at least include the DC link equivalent series resistance, the power loop resistance, the shunt resistance, the power loop parasitic inductance, and the snubber circuit parasitic inductance.

5. A modeling device for a high-frequency equivalent circuit, applied to the circuit described in claim 1, characterized in that, It includes: a building module, configured to build a high-order switching oscillation circuit model with parasitic parameters, wherein the parasitic parameters at least include: the internal cascaded parasitic parameters of the cascode gallium nitride device, the half-bridge circuit distributed parameters and the snubber circuit parameters in a bridge converter including the cascode gallium nitride device; a processing module, configured to extract key parasitic parameters of the high-order switching oscillation circuit model by using switching characteristics, and determine a high-frequency equivalent circuit model corresponding to the high-order switching oscillation circuit model through circuit equivalent transformation, wherein the key parasitic parameters are the parasitic parameters affecting the switching oscillation of the cascode gallium nitride device.

6. An electronic device, characterized in that, It includes: a processor; a memory for storing instructions executable by the processor; wherein, the processor is configured to execute the steps of the method according to any one of claims 2 to 4.

7. A computer-readable storage medium having instructions stored thereon, characterized in that, When the instructions are executed by the processor, the steps of the method according to any one of claims 2 to 4 are implemented.

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