Hardware-based CPU clock adjustment circuit, system, and adjustment method

Abstract

This invention discloses a hardware-based CPU clock adjustment circuit, system, and adjustment method. The CPU clock adjustment circuit includes a phase-locked loop (PLL) counting module, a PLL parameter comparison module, and a clock gating module. The PLL counting module counts the clock signals transmitted by the PLL circuit and outputs a clock gating enable signal to the clock gating module to control its operation. The PLL parameter comparison module determines whether the PLL circuit is in the clock frequency adjustment phase and outputs a reset signal to the PLL counting module when it is. The clock gating module controls the clock gating module to transmit the CPU clock signal to the CPU based on the received clock gating enable signal. This invention achieves CPU clock frequency adjustment only after the PLL circuit has stabilized, ensuring a stable and glitchy CPU clock and guaranteeing normal CPU operation during the PLL circuit's frequency switching phase.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a CPU clock adjustment circuit based on hardware implementation, a system and an adjustment method thereof. BACKGROUND

[0002] At present, in the SoC system, the clock frequency of the CPU needs to be adjusted according to the different requirements of the application program. Due to the high complexity of the actual application program, the CPU needs to be continuously adjusted in frequency. If clock glitch occurs during the adjustment process of the CPU clock frequency, it will affect the normal work of the CPU, which may cause the safety of the CPU to be reduced or the CPU to be dead, etc., affecting the working efficiency and effect of the CPU. The CPU clock frequency adjustment is mainly through the frequency adjustment software to wait until the phase-locked loop is stable, and then switch the clock source of the CPU to the phase-locked loop. The current frequency adjustment software has the problems of complicated operation and low efficiency, which affects the user experience. SUMMARY

[0003] In order to solve the above problems, the present application provides a CPU clock adjustment circuit based on hardware implementation, a system and an adjustment method thereof. The CPU clock adjustment is realized by hardware circuit, which simplifies the operation steps of the frequency adjustment software, improves the efficiency of the CPU clock adjustment, and ensures the normal work of the CPU during the adjustment stage. The specific technical scheme of the present application is as follows:

[0004] The CPU clock adjustment circuit based on hardware implementation comprises a phase-locked loop counting module, a phase-locked loop parameter comparison module and a clock gating module. The phase-locked loop counting module is used to count the clock signal transmitted by the phase-locked loop circuit and output a clock gating enable signal to the clock gating module to control the running of the clock gating module. The phase-locked loop parameter comparison module is used to determine whether the phase-locked loop circuit is in the clock frequency adjustment stage. When the phase-locked loop circuit is in the clock frequency adjustment stage, a reset signal is output to the phase-locked loop counting module to clear the count value of the phase-locked loop counting module. The clock gating module is used to control the transmission of the CPU clock signal from the clock gating module to the CPU according to the received clock gating enable signal.

[0005] Compared with the prior art, the CPU clock adjustment circuit based on hardware implementation in the present application can realize the adjustment of the CPU clock frequency without frequent adjustment when the phase-locked loop circuit is in the clock frequency adjustment stage, and can ensure the stability of the CPU clock without glitch after the phase-locked loop circuit is adjusted and stabilized. The frequency switching efficiency of the phase-locked loop circuit is effectively improved, and the normal work of the CPU during the frequency switching stage of the phase-locked loop circuit is ensured.

[0006] Further, the phase-locked loop counting module comprises a counter and a first comparator; the counter comprises a first input end, a second input end and an output end, the first input end of the counter is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit; the second input end of the counter is used for receiving the reset signal transmitted by the phase-locked loop parameter comparison module; the counter is used for counting the clock signal transmitted by the phase-locked loop circuit, obtaining a count value, and determining whether to reset and clear the count value according to the reset signal transmitted by the phase-locked loop parameter comparison module; the first comparator comprises a first input end, a second input end and a clock gate enable signal output end, the first input end of the first comparator is used for receiving the clock signal transmitted by the phase-locked loop circuit; the second input end of the first comparator is connected with the output end of the counter, for receiving the count value transmitted by the counter; the clock gate enable signal output end of the first comparator is connected with the clock gating module, so as to transmit the clock gate enable signal generated by the first comparator to the clock gating module; the first comparator is used for comparing the received count value with a preset count threshold value, when the count value is greater than or equal to the preset count threshold value, the first comparator outputs a high-level clock gate enable signal; when the count value is less than the preset count threshold value, the first comparator outputs a low-level clock gate enable signal. The phase-locked loop technology module counts the phase-locked loop clock based on the counter, so as to identify whether the frequency modulation stage of the phase-locked loop circuit ends according to whether the count value reaches the preset count threshold value, if the count value reaches the preset technology threshold value, it is determined that the clock frequency of the phase-locked loop circuit has stabilized, the phase-locked loop counting module outputs a high-level clock gate enable signal, so that the CPU clock signal of the clock gating module is valid, by controlling the counting and resetting of the counter, the accuracy of the clock gate enable signal output by the second comparator is ensured, and the CPU clock is stable without glitches.

[0007] Further, the first comparator further comprises a third input end, for receiving an externally set preset count threshold value. By receiving the externally set preset count threshold value through the third input end of the first comparator, the preset count threshold value can be changed, improving the flexibility and adaptability of the CPU clock adjustment circuit realized based on hardware.

[0008] Further, the first comparator is internally configured with a preset count threshold value. By configuring the preset count threshold value in the first comparator, the problem of inaccurate preset count threshold value adjustment affecting the high-low level accuracy of the clock gate enable signal output by the phase-locked loop counting module is avoided.

[0009] Further, the phase-locked loop parameter comparison module comprises a synchronizer and a second comparator; the synchronizer comprises a first input end, a second input end and an output end, the first input end of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit; the second input end of the synchronizer is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the external register; the synchronizer is used for synchronizing the current received phase-locked loop parameter, and transmitting the synchronized phase-locked loop parameter to the second comparator; the second comparator comprises a first input end, a second input end, a third input end and a reset signal output end, the first input end of the second comparator is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit; the second input end of the second comparator is connected with the output end of the synchronizer, for receiving the synchronized phase-locked loop parameter; the third input end of the second comparator is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the phase-locked loop circuit; the second comparator is used for comparing the phase-locked loop parameter received by the second input end of the second comparator with the phase-locked loop parameter received by the third input end of the second comparator, when the phase-locked loop parameter received by the second input end of the second comparator is equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a low-level reset signal; when the phase-locked loop parameter received by the second input end of the second comparator is not equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a high-level reset signal. The technical scheme is based on the phase-locked loop parameter comparison module, compares the phase-locked loop parameters before and after synchronization, to determine whether the phase-locked loop circuit is in the frequency adjustment stage, thereby controlling the output effectiveness of the reset signal, the combination of the phase-locked loop parameter comparison module and the phase-locked loop counting module doubly ensures the accuracy of the confirmation result of whether the CPU clock adjustment circuit based on hardware realizes that the phase-locked loop circuit is in the clock frequency adjustment stage.

[0010] Further, the second input end of the counter is connected with the reset signal output end of the second comparator, for enabling the counter to receive the reset signal transmitted by the second comparator; when the counter receives the high-level reset signal transmitted by the second comparator, the counting value of the counter is cleared; when the counter receives the low-level reset signal transmitted by the second comparator, the counter continues counting. The clearing of the counter is controlled by the reset control signal, thereby indirectly controlling the effectiveness of the clock gate enable signal output by the first comparator.

[0011] Further, the synchronizer is an N-stage synchronizer, the first input end of each stage of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit respectively to receive the clock signal of the phase-locked loop circuit; the second input end of the first stage of the synchronizer is connected with the phase-locked loop parameter output end of the external register as the second input end of the N-stage synchronizer to receive the phase-locked loop parameter transmitted by the external register; the second input end of each stage of the synchronizer except the first stage is connected with the output end of the previous stage of the synchronizer to receive the phase-locked loop parameter output by the previous stage of the synchronizer; the output end of the Nth stage of the synchronizer is connected with the second input end of the second comparator as the output end of the N-stage synchronizer to output the synchronized phase-locked loop parameter; wherein N is an integer greater than or equal to 2. The N-stage synchronizer is adopted to meet the requirement that the clock frequency of the phase-locked loop circuit does not change suddenly, and the N-stage synchronizer can meet the requirement of effectiveness of the reset signal generated by the second comparator.

[0012] Further, the output end of the synchronizer is also connected with the phase-locked loop parameter input end of the phase-locked loop circuit to realize that the synchronized phase-locked loop parameter is transmitted to the phase-locked loop circuit by the synchronizer. The synchronized phase-locked loop parameter is transmitted to the phase-locked loop circuit by the synchronizer to realize the phase-locked loop parameter adjustment of the phase-locked loop circuit, so that the phase-locked loop outputs the corresponding clock signal.

[0013] Further, the clock gating module comprises a clock gating circuit, the clock gating circuit comprises a first input end, a second input end and an output end, the first input end of the clock gating circuit is connected with the clock signal output end of the phase-locked loop circuit to realize that the clock signal transmitted by the phase-locked loop circuit is received by the clock gating circuit; the second input end of the clock gating circuit is connected with the output end of the first comparator of the phase-locked loop counting module to make the clock gating enable signal transmitted by the first comparator of the phase-locked loop counting module be received by the clock gating circuit to realize the control of the work of the clock gating circuit; wherein when the clock gating enable signal of high level is received by the clock gating circuit, the clock signal of the phase-locked loop circuit is output as the CPU clock signal by the clock gating circuit; when the clock gating enable signal of low level is received by the clock gating circuit, the CPU clock signal is not output by the clock gating circuit. The effectiveness of the CPU clock signal output by the clock gating circuit is controlled based on the clock gating enable signal received by the clock gating circuit, the CPU clock signal is not output when the phase-locked loop circuit is in the clock frequency adjustment stage, the frequent clock frequency adjustment of the CPU is avoided, the CPU clock signal is output when the clock frequency of the phase-locked loop circuit is stable, the corresponding clock frequency adjustment of the CPU is realized, the effectiveness of the CPU clock frequency adjustment is greatly improved, and the stable and burr-free CPU clock signal is ensured.

[0014] The application further discloses a hardware-based CPU clock adjusting system, which comprises the hardware-based CPU clock adjusting circuit as described above, an external register for storing all parameters of a phase-locked loop circuit and transmitting the parameters to the phase-locked loop circuit for parameter adjustment of the phase-locked loop circuit, and a CPU for receiving a CPU clock signal output by the CPU clock adjusting circuit.

[0015] The application further discloses a CPU clock adjusting method, which comprises the following steps: the phase-locked loop circuit transmits a phase-locked loop clock signal to each component in the CPU clock adjusting circuit; a counter counts according to the phase-locked loop clock signal and transmits a count value to a first comparator; the first comparator compares the count value with a preset count threshold; when the count value is greater than or equal to the preset count threshold, the first comparator outputs a high-level clock enable signal to a clock gating circuit, the clock gating circuit transmits the current phase-locked loop clock signal to the CPU as a CPU clock signal, and the adjustment of the CPU clock is realized; and when the count value is less than the preset count threshold, the first comparator outputs a low-level clock enable signal to the clock gating circuit, and the clock gating circuit does not output the CPU clock signal. Compared with the prior art, the application determines whether the phase-locked loop circuit has reached the preset count threshold by counting the clock signal of the phase-locked loop circuit, the preset count threshold is determined by repeatedly testing the count value of the time signal required for the phase-locked loop to stabilize, and whether the phase-locked loop circuit has stabilized is determined by judging whether the count value reaches the preset count threshold, so that the frequent adjustment of the CPU clock frequency is reduced.

[0016] Further, the method further comprises: the external register transmitting the phase-locked loop parameter to the synchronizer and the second comparator, the synchronizer synchronizing the received phase-locked loop parameter and transmitting the synchronized phase-locked loop parameter to the second comparator, and the second comparator comparing the synchronized phase-locked loop parameter with the phase-locked loop parameter before synchronization; when the synchronized phase-locked loop parameter is the same as the phase-locked loop parameter before synchronization, the second comparator transmits a low-level reset signal to the counter, and the counter keeps normal counting; when the synchronized phase-locked loop parameter is not the same as the phase-locked loop parameter before synchronization, the second comparator transmits a high-level reset signal to the counter, the counter resets and clears the counting value, and the counter restarts counting. In the technical solution, whether the phase-locked loop circuit is in the parameter adjustment stage is determined by comparing whether the phase-locked loop parameters before and after synchronization are equal, which is equivalent to determining whether the phase-locked loop circuit is in the frequency adjustment stage, and simultaneously acts with the counter, further ensures the level accuracy of the clock gate enable signal output by the first comparator, and ensures the stability of the CPU clock without burr. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 A module schematic diagram of the CPU clock adjustment circuit according to an embodiment of the present application.

[0018] Figure 2 A circuit schematic diagram of the CPU clock adjustment circuit according to an embodiment of the present application.

[0019] Figure 3 A module schematic diagram of the CPU clock adjustment system according to an embodiment of the present application.

[0020] Figure 4 A circuit schematic diagram of the CPU clock adjustment system according to an embodiment of the present application.

[0021] Figure 5 A flowchart of the adjustment method of the CPU clock adjustment system according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described and explained below in combination with the drawings and embodiments. It should be understood that the specific embodiments described below are only used to explain the present application and should not be used to limit the present application. In addition, it can be understood by those skilled in the art that some design, manufacture or production changes on the technical content disclosed in the present application are only conventional technical means and should not be understood as the insufficiency of the disclosed content of the present application.

[0023] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the ordinary meanings as understood by one of ordinary skill in the art to which this application pertains. The terms "a", "an", "one", "this", and "the" used in this application are not limited to the singular form, and can mean one or more. The terms "include", "comprise", "have", and any variations thereof, are intended to cover non-exclusive inclusion, such that processes, methods, product, or devices that include a list of steps or modules are not limited to those listed steps or modules, but can also include other steps or modules not listed, or can also include other steps or modules inherent to the processes, methods, product, or devices. The terms "first", "second", "third", and the like are only used to distinguish similar corresponding, and do not represent a specific order for the objects.

[0024] In an embodiment of the present application, a hardware-based CPU clock adjustment circuit is provided, as shown in Figure 1 The hardware-based CPU clock adjustment circuit includes a phase-locked loop counting module, a phase-locked loop parameter comparison module, and a clock gating module.

[0025] The phase-locked loop counting module is configured to count the clock signal transmitted by the phase-locked loop circuit, and output a clock gating enable signal to the clock gating module to control the operation of the clock gating module.

[0026] Specifically, as shown in Figure 2 The phase-locked loop counting module includes a counter and a first comparator. The counter includes a first input end, a second input end, and an output end. The first input end of the counter is connected to the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit. The second input end of the counter is configured to receive a reset signal transmitted by the phase-locked loop parameter comparison module. The counter is configured to count the clock signal transmitted by the phase-locked loop circuit, and obtain a count value. The counter is also configured to determine whether to reset and clear the count value according to the reset signal transmitted by the comparison module. The first comparator includes a first input end, a second input end, and a clock gating enable signal output end. The first input end of the first comparator is configured to receive the clock signal transmitted by the phase-locked loop circuit. The second input end of the first comparator is connected to the output end of the counter, for receiving the count value transmitted by the counter. The clock gating enable signal output end of the first comparator is connected to the clock gating module, for transmitting the clock gating enable signal generated by the first comparator to the clock gating module. The first comparator is configured to compare the received count value with a preset count threshold value. When the count value is greater than or equal to the preset count threshold value, the first comparator outputs a high-level clock gating enable signal. When the count value is less than the preset count threshold value, the first comparator outputs a low-level clock gating enable signal.

[0027] Preferably, the pre-set count threshold is configured in the first comparator, or the first comparator further comprises a third input end for receiving an externally set pre-set count threshold. It should be noted that the pre-set count threshold is a count threshold set by a user according to a count value required for a phase-locked loop circuit to perform a clock frequency adjustment regularly until a clock frequency of the phase-locked loop circuit is stable, and the pre-set count threshold can be transmitted to the first comparator by the user through the third input end in the form of being pre-configured in the first comparator or being configured in the first comparator through the third input end. It should be noted that the input arrow of the pre-set count threshold in Figure 1 、 Figure 2 、 Figure 3 and Figure 4 is a dashed line, when the pre-set count threshold is transmitted to the first comparator through the third input end of the first comparator, the input arrow is an actually existing data transmission arrow, when the pre-set count threshold is configured in the first comparator, the input arrow in Figure 1 、 Figure 2 、 Figure 3 and Figure 4 does not exist, and the third input end of the first comparator in Figure 2 and Figure 4 does not exist.

[0028] The phase-locked loop parameter comparison module is configured to determine whether the phase-locked loop circuit is in a frequency adjustment stage, and output a reset signal to the phase-locked loop counting module to control the count value of the phase-locked loop counting module to be cleared when the phase-locked loop circuit is in the frequency adjustment stage.

[0029] Specifically, refer to Figure 2The phase-locked loop parameter comparison module comprises a synchronizer and a second comparator. The synchronizer comprises a first input end, a second input end and an output end. The first input end of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit. The second input end of the synchronizer is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the external register. The synchronizer is used for synchronizing the current received phase-locked loop parameter, and transmitting the synchronized phase-locked loop parameter to the second comparator. The second comparator comprises a first input end, a second input end, a third input end and a reset signal output end. The first input end of the second comparator is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit. The second input end of the second comparator is connected with the output end of the synchronizer, for receiving the synchronized phase-locked loop parameter. The third input end of the second comparator is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the phase-locked loop circuit. The second comparator is used for comparing the phase-locked loop parameter received by the second input end of the second comparator with the phase-locked loop parameter received by the third input end of the second comparator. When the phase-locked loop parameter received by the second input end of the second comparator is equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a low-level reset signal. When the phase-locked loop parameter received by the second input end of the second comparator is not equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a high-level reset signal. The second input end of the counter is connected with the reset signal output end of the second comparator, for enabling the counter to receive the reset signal transmitted by the second comparator. When the counter receives the high-level reset signal transmitted by the second comparator, the count value of the counter is cleared. When the counter receives the low-level reset signal transmitted by the second comparator, the counter continues counting.

[0030] The clock gating module is used for transmitting the CPU clock signal to the CPU according to the received clock gating enable signal. Specifically, refer to Figure 2The clock gating module comprises a clock gating circuit, the clock gating circuit comprises a first input end, a second input end and an output end, the first input end of the clock gating circuit is connected with the clock signal output end of the phase-locked loop circuit, so that the clock gating circuit receives the clock signal transmitted by the phase-locked loop circuit; the second input end of the clock gating circuit is connected with the output end of the first comparator of the phase-locked loop counting module, so that the clock gating circuit receives the clock gating enable signal transmitted by the first comparator of the phase-locked loop counting module, to realize the control of the work of the clock gating circuit; when the clock gating circuit receives the clock gating enable signal of high level, the clock gating circuit outputs the clock signal of the phase-locked loop circuit as the CPU clock signal; when the clock gating circuit receives the clock gating enable signal of low level, the clock gating circuit does not output the CPU clock signal. The clock gating enable signal is output in view of whether the phase-locked loop circuit is in the clock frequency adjustment stage, so that the adjustment of the CPU clock frequency is realized indirectly after the clock frequency of the phase-locked loop circuit is adjusted and stabilized through the CPU clock adjustment circuit.

[0031] In another embodiment of the application, the synchronizer of the phase-locked loop parameter comparison module is an N-stage synchronizer, the first input end of each stage of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit, to receive the clock signal of the phase-locked loop circuit; the second input end of the first stage of the synchronizer is connected with the phase-locked loop parameter output end of the external register as the second input end of the N-stage synchronizer, to receive the phase-locked loop parameter transmitted by the external register; the second input end of each stage of the synchronizer except the first stage is connected with the output end of the last stage of the synchronizer, to receive the phase-locked loop parameter output by the last stage of the synchronizer; the output end of the Nth stage of the synchronizer is connected with the second input end of the second comparator as the output end of the N-stage synchronizer, to output the synchronized phase-locked loop parameter; wherein N is an integer greater than or equal to 2. By using the N-stage synchronizer, it is ensured that the clock frequency of the phase-locked loop circuit does not change suddenly, and the N-stage synchronizer can meet the requirement of the effectiveness of the reset signal generated by the second comparator.

[0032] Preferably, as shown in Figure 2 the output end of the N-stage synchronizer (the output end of the Nth stage of the synchronizer) is also connected with the phase-locked loop parameter input end of the phase-locked loop circuit, so that the synchronized phase-locked loop parameter is sent to the phase-locked loop circuit by the synchronizer, and the phase-locked loop adjusts the parameters according to the received phase-locked loop parameter; when the phase-locked loop circuit adjusts the parameters, the phase-locked loop circuit is in the clock frequency adjustment stage.

[0033] In another embodiment of the application, a hardware-based CPU clock adjustment system is provided, as shown in Figure 3As shown, the CPU clock adjustment system comprises the hardware-based CPU clock adjustment circuit, the CPU, the external register and the phase-locked loop circuit; the CPU clock adjustment circuit is used for reading all parameters of the phase-locked loop circuit stored in the external register and transmitting the parameters to the phase-locked loop circuit for parameter adjustment of the phase-locked loop circuit, waiting for the phase-locked loop parameter adjustment to be stable, and outputting the CPU clock signal according to the clock signal of the phase-locked loop circuit to adjust the CPU clock; the CPU is used for receiving the CPU clock signal output by the CPU clock adjustment circuit; the phase-locked loop circuit is used for receiving the parameter adjustment of the CPU clock adjustment circuit and outputting the clock signal of the phase-locked loop circuit; and the external register is used for storing all parameters of the phase-locked loop circuit. Specifically, the transmission relationship of data / signal between the specific components in the CPU clock adjustment circuit, the CPU, the external register and the phase-locked loop circuit in the CPU clock adjustment system can be referred to Figure 4 .

[0034] Based on the CPU clock adjustment system and the hardware-based CPU clock adjustment circuit provided in the above embodiments, another embodiment of the present application provides a CPU clock adjustment method of the CPU clock adjustment circuit, as shown in the method, which comprises the following steps: Figure 5

[0035] The phase-locked loop circuit inputs the phase-locked loop clock signal to each component in the CPU clock adjustment circuit, the counter counts according to the phase-locked loop clock signal and transmits the count value to the first comparator, the first comparator compares whether the count value is greater than or equal to the preset count threshold value, and the first comparator transmits the clock gate enable signal of the corresponding high level or low level to the clock gate circuit according to the first comparison result. When the first comparison result is that the count value is not equal to the preset count threshold value, it is confirmed that the phase-locked loop circuit is in the frequency adjustment stage and the phase-locked loop circuit parameter is unstable, and the first comparator transmits the clock gate enable signal of the low level to the clock gate circuit; when the first comparison result is that the count value is greater than or equal to the preset count threshold value, it is confirmed that the phase-locked loop circuit parameter is stable and the phase-locked loop circuit is not in the frequency adjustment stage, and the first comparator transmits the clock gate enable signal of the high level to the clock gate circuit.

[0036] When the clock gate circuit receives the clock gate enable signal of the high level transmitted by the first comparator, the clock gate circuit transmits the valid CPU clock signal to the CPU, so that the CPU adjusts the corresponding frequency according to the CPU clock signal; when the clock gate circuit receives the clock gate enable signal of the low level transmitted by the first comparator, the clock gate circuit does not transmit the CPU clock signal to the CPU.

[0037] ​Meanwhile, the external register transmits the phase-locked loop parameter to the synchronizer and the second comparator, the synchronizer synchronizes the received phase-locked loop parameter, and then the synchronizer transmits the synchronized phase-locked loop parameter to the second comparator and to the phase-locked loop circuit, the second comparator compares whether the synchronized phase-locked loop parameter is the same as the phase-locked loop parameter without synchronization processing, and the second comparator transmits the reset signal of the corresponding high level or low level to the counter according to the second comparison result. When the second comparison result is that the synchronized phase-locked loop parameter is the same as the phase-locked loop parameter without synchronization processing, it is confirmed that the phase-locked loop parameter is stable, the phase-locked loop circuit is not in the frequency adjustment stage, and the second comparator outputs the reset signal of the low level. When the second comparison result is that the synchronized phase-locked loop parameter is not the same as the phase-locked loop parameter without synchronization processing, it is confirmed that the phase-locked loop parameter is unstable, the phase-locked loop circuit is in the frequency adjustment stage, and the second comparator outputs the reset signal of the high level.

[0038] When the counter receives the reset signal of the high level transmitted by the second comparator, the counter resets and clears the count value, and the counter starts counting again. When the counter receives the reset signal of the low level transmitted by the second comparator, the counter keeps normal counting.

[0039] Specifically, the phase-locked loop circuit adjusts the parameter according to the received synchronized phase-locked loop parameter, and correspondingly outputs the adjusted clock signal to each component in the CPU clock adjustment circuit.

[0040] Obviously, the above-mentioned embodiments are only a part of the embodiments of the present application, and the technical solutions of each embodiment can be combined with each other. In addition, if the terms such as "first", "second", "third" and the like appear in the embodiments, they are used only for the convenience of distinguishing the related features, and cannot be understood as indicating or implying the relative importance, the order of precedence or the number of technical features.

[0041] In several embodiments provided by the present application, it should be understood that the disclosed technology can be implemented by other ways. Of course, the embodiment described above is only a schematic and exemplary, for example, the division of the modules can be a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another module or system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units or modules shown or discussed can be indirect coupling or communication connection through some interfaces, units or modules, and can be electrical or other forms.

[0042] Although the embodiments of the present application have been shown and described, it is to be understood that various modifications, substitutions, changes and alterations can be made to these embodiments without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents. The foregoing description is only exemplary of the preferred embodiments of the application and is not intended to be limiting of the present application. Various changes and modifications can be made to the application by those skilled in the art without departing from the spirit and scope of the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present application should be included in the scope of the present application.

Claims

1. A hardware-implemented CPU clock adjustment circuit, characterized by, The hardware-based CPU clock adjusting circuit comprises a phase-locked loop counting module, a phase-locked loop parameter comparison module and a clock gating module. The phase-locked loop counting module is configured to count the clock signal transmitted by the phase-locked loop circuit and output a clock gating enable signal to the clock gating module to control the operation of the clock gating module. The phase-locked loop parameter comparison module is configured to determine whether the phase-locked loop circuit is in a clock frequency adjusting stage and output a reset signal to the phase-locked loop counting module to clear the counting value of the phase-locked loop counting module when the phase-locked loop circuit is in the clock frequency adjusting stage. The clock gating module is configured to transmit the CPU clock signal to the CPU according to the received clock gating enable signal.

2. The hardware-implemented CPU clock adjustment circuit of claim 1, wherein, The phase-locked loop counting module comprises a counter and a first comparator. The counter comprises a first input end, a second input end and an output end, the first input end of the counter is connected with the clock signal output end of the phase-locked loop circuit to receive the clock signal transmitted by the phase-locked loop circuit, and the second input end of the counter is configured to receive the reset signal transmitted by the phase-locked loop parameter comparison module. The counter is configured to count the clock signal transmitted by the phase-locked loop circuit, obtain a counting value and determine whether to reset and clear the counting value according to the reset signal transmitted by the phase-locked loop parameter comparison module. The first comparator comprises a first input end, a second input end and a clock gating enable signal output end, the first input end of the first comparator is configured to receive the clock signal transmitted by the phase-locked loop circuit, the second input end of the first comparator is connected with the output end of the counter to receive the counting value transmitted by the counter, and the clock gating enable signal output end of the first comparator is connected with the clock gating module to transmit the clock gating enable signal generated by the first comparator to the clock gating module. The first comparator is configured to compare the received counting value with a preset counting threshold value, output a high-level clock gating enable signal when the counting value is greater than or equal to the preset counting threshold value, and output a low-level clock gating enable signal when the counting value is less than the preset counting threshold value.

3. The hardware-implemented CPU clock adjustment circuit of claim 2, wherein, The first comparator further comprises a third input end configured to receive an externally set preset counting threshold value.

4. The hardware-implemented CPU clock adjustment circuit of claim 2, wherein, The first comparator is internally configured with a preset counting threshold value.

5. The hardware-implemented CPU clock adjustment circuit of claim 2, wherein, The phase-locked loop parameter comparison module comprises a synchronizer and a second comparator. The synchronizer comprises a first input end, a second input end and an output end, the first input end of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit to receive the clock signal transmitted by the phase-locked loop circuit, and the second input end of the synchronizer is connected with the phase-locked loop parameter output end of an external register to receive the phase-locked loop parameter transmitted by the external register. The synchronizer is configured to synchronize the currently received phase-locked loop parameter and transmit the synchronized phase-locked loop parameter to the second comparator. The second comparator comprises a first input end, a second input end and a clock gating enable signal output end, the first input end of the second comparator is connected with the clock signal output end of the phase-locked loop circuit to receive the clock signal transmitted by the phase-locked loop circuit, the second input end of the second comparator is connected with the output end of the synchronizer to receive the synchronized phase-locked loop parameter transmitted by the synchronizer, and the clock gating enable signal output end of the second comparator is connected with the clock gating module to transmit the clock gating enable signal generated by the second comparator to the clock gating module. The second comparator is configured to compare the received synchronized phase-locked loop parameter with a preset phase-locked loop parameter threshold value, output a high-level clock gating enable signal when the synchronized phase-locked loop parameter is greater than or equal to the preset phase-locked loop parameter threshold value, and output a low-level clock gating enable signal when the synchronized phase-locked loop parameter is less than the preset phase-locked loop parameter threshold value. The second comparator comprises a first input end, a second input end, a third input end and a reset signal output end, the first input end of the second comparator is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal transmitted by the phase-locked loop circuit; the second input end of the second comparator is connected with the output end of the synchronizer, for receiving the synchronized phase-locked loop parameter; the third input end of the second comparator is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the phase-locked loop circuit; The second comparator is used for comparing the phase-locked loop parameter received by the second input end of the second comparator with the phase-locked loop parameter received by the third input end of the second comparator, when the phase-locked loop parameter received by the second input end of the second comparator is equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a low-level reset signal; when the phase-locked loop parameter received by the second input end of the second comparator is not equal to the phase-locked loop parameter received by the third input end of the second comparator, the second comparator outputs a high-level reset signal.

6. The hardware-implemented CPU clock adjustment circuit of claim 5, wherein, The second input end of the counter is connected with the reset signal output end of the second comparator, for enabling the counter to receive the reset signal transmitted by the second comparator; when the counter receives the high-level reset signal transmitted by the second comparator, the count value of the counter is cleared; when the counter receives the low-level reset signal transmitted by the second comparator, the counter continues to count.

7. The hardware-implemented CPU clock adjustment circuit of claim 5, wherein, The synchronizer is an N-stage synchronizer, the first input end of each stage of the synchronizer is connected with the clock signal output end of the phase-locked loop circuit, for receiving the clock signal of the phase-locked loop circuit; the second input end of the first stage of the synchronizer is connected with the phase-locked loop parameter output end of the external register, for receiving the phase-locked loop parameter transmitted by the external register, the second input end of each stage of the synchronizer except the first stage is connected with the output end of the previous stage of the synchronizer, for receiving the phase-locked loop parameter output by the previous stage of the synchronizer; the output end of the Nth stage of the synchronizer is connected with the second input end of the second comparator, for outputting the synchronized phase-locked loop parameter; wherein, N is an integer greater than or equal to 2.

8. The hardware-implemented CPU clock adjustment circuit according to any one of claim 5 or claim 7, wherein, The output end of the synchronizer is also connected with the phase-locked loop parameter input end of the phase-locked loop circuit, for enabling the synchronizer to send the synchronized phase-locked loop parameter to the phase-locked loop circuit.

9. The hardware-implemented CPU clock adjustment circuit of claim 2, wherein, The clock gating module comprises a clock gating circuit, the clock gating circuit comprises a first input end, a second input end and an output end, the first input end of the clock gating circuit is connected with the clock signal output end of the phase-locked loop circuit, so that the clock gating circuit receives the clock signal transmitted by the phase-locked loop circuit; the second input end of the clock gating circuit is connected with the output end of the first comparator of the phase-locked loop counting module, so that the clock gating circuit receives the clock gating enable signal transmitted by the first comparator of the phase-locked loop counting module, to realize the control of the working of the clock gating circuit; wherein, when the clock gating circuit receives the clock gating enable signal of high level, the clock gating circuit outputs the clock signal of the phase-locked loop circuit as the CPU clock signal; when the clock gating circuit receives the clock gating enable signal of low level, the clock gating circuit does not output the CPU clock signal.

10. A hardware-implemented CPU clock adjustment system, characterized by The CPU clock adjustment system comprises: The hardware-based CPU clock adjustment circuit according to any one of claims 1 to 9 is used for reading all parameters of the phase-locked loop circuit stored in the external register, transmitting the parameters to the phase-locked loop circuit for parameter adjustment of the phase-locked loop circuit, and outputting the CPU clock signal according to the clock signal of the phase-locked loop circuit after the phase-locked loop parameter adjustment is stable to adjust the CPU clock; The CPU is used for receiving the CPU clock signal output by the CPU clock adjustment circuit; The phase-locked loop circuit is used for receiving the parameter adjustment of the CPU clock adjustment circuit and outputting the clock signal of the phase-locked loop circuit; The external register is used for storing all parameters of the phase-locked loop circuit.

11. A method of regulating a CPU clock regulation system, characterized by, The method is based on the hardware-based CPU clock adjustment system according to claim 10, and the method specifically comprises: The phase-locked loop circuit transmits the phase-locked loop clock signal to each component in the CPU clock adjustment circuit, the counter performs counting according to the phase-locked loop clock signal and transmits the counting value to the first comparator, and the first comparator compares the counting value with the preset counting threshold value; When the counting value is greater than or equal to the preset counting threshold value, the first comparator outputs the clock enable signal of high level to the clock gating circuit, and the clock gating circuit transmits the current phase-locked loop clock signal as the CPU clock signal to the CPU, to realize the adjustment of the CPU clock; When the counting value is less than the preset counting threshold value, the first comparator outputs the clock enable signal of low level to the clock gating circuit, and the clock gating circuit does not output the CPU clock signal.

12. The method of adjusting the CPU clock adjustment system according to claim 11, wherein, The method further comprises: The external register transmits the phase-locked loop parameters to the synchronizer and the second comparator, the synchronizer synchronizes the received phase-locked loop parameters, transmits the synchronized phase-locked loop parameters to the second comparator, and the second comparator compares the synchronized phase-locked loop parameters with the phase-locked loop parameters before synchronization; When the synchronized phase-locked loop parameters are the same as the phase-locked loop parameters before synchronization, the second comparator transmits the reset signal of low level to the counter, and the counter keeps normal counting; When the phase-locked loop parameter after the synchronization processing is different from the phase-locked loop parameter before the synchronization processing, the second comparator transmits a high-level reset signal to the counter, the counter resets and clears the count value, and the counter restarts counting.

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