Integrated circuit design layout circuit area acquisition method and device and computer equipment

Abstract

The present application relates to the field of integrated circuit computer-aided design, in particular to an integrated circuit design layout circuit area acquisition method, device and computer equipment. The integrated circuit design layout circuit area acquisition method comprises the following steps: obtaining the image area of the design layout; defining a preset area on the design layout and uniformly distributing a preset number of sampling points in the preset area; calculating the falling number and falling probability of the sampling points in the circuit diagram of the preset area; and calculating based on the falling probability and the image area of the design layout to obtain the final circuit diagram area in the design layout. The technical problem of long acquisition time and low efficiency of the existing integrated circuit design layout area is solved.

Description

Technical Field

[0001] This invention relates to the field of computer-aided design of integrated circuits, and in particular to a method, apparatus and computer device for obtaining the circuit area of ​​an integrated circuit design layout. Background Technology

[0002] In modern very large-scale integrated circuit (VLSI) manufacturing processes, layout design maps the designed circuit diagram to a physical description level, thereby enabling the production of the designed circuit onto a wafer. The layout contains a graphical representation of the physical information of the integrated circuit, including device types, device dimensions, relative positions of devices, and interconnections. To achieve VLSI manufacturing, it is also essential to minimize the layout area.

[0003] Existing methods for calculating network layout area mostly focus on extracting and calculating key areas of the layout. This requires classifying each period in the circuit netlist and calculating its corresponding ideal area before piecing them together to calculate the total layout area. However, the graphics in a network layout can reach the order of billions (1G). Using a fragmented approach would require verifying all the data in the layout one by one, which is far from meeting the user's needs in terms of time and space efficiency. Summary of the Invention

[0004] To address the problems of long processing time and low efficiency in obtaining the layout area of ​​integrated circuit designs, this invention provides a method, apparatus, and computer device for obtaining the circuit area of ​​integrated circuit design layouts.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a method for obtaining the circuit area of ​​an integrated circuit design layout, characterized by comprising the following steps:

[0006] Obtain the image area of ​​the design layout;

[0007] Define a preset area on the design map and evenly distribute a preset number of sampling points within the preset area;

[0008] Calculate the number of sampling points and the probability of sampling points falling into the circuit diagram of the preset area;

[0009] The final circuit diagram area in the design layout is calculated based on the fall probability and the image area of ​​the design layout.

[0010] Preferably, the image area of ​​each layer in the design layout with a preset number of layers is obtained; the final circuit diagram area in the design layout of each layer is calculated; and the final circuit diagram areas of each layer are summed up; the preset number of layers is 8-40 layers.

[0011] Preferably, defining the preset area on the design layout includes the following steps: identifying the center point of the design layout, establishing two reference axes based on the center point, and setting a strip-shaped preset area based on the two reference axes.

[0012] Preferably, the reference axis is at least one of the axis of symmetry or the diagonal of the design layout.

[0013] Preferably, the step of uniformly distributing a preset number of sampling points within a preset area includes the following steps: uniformly distributing a preset number of sampling points in an array within the preset area.

[0014] Preferably, the calculation of the number of sampling points and the probability of sampling points falling into the circuit diagram of the preset region includes the following steps:

[0015] The cross-point counting method is used to determine whether each sampling point is within the circuit diagram;

[0016] The total number of sampling points that fall within the circuit diagram is the number of points that fall within the circuit diagram.

[0017] The probability of falling in is obtained based on the number of falls and the preset number.

[0018] Preferably, after obtaining the image area of ​​each layer in the design layout with a preset number of layers, the method further includes the following steps:

[0019] On each layer of the design plan, define multiple preset areas of different sizes, and calculate the probability of sampling points falling into each of the multiple preset areas.

[0020] Alternatively, define a preset area on each layer of the design layout, generate multiple types of sampling points within the preset area, and calculate the probability of each type of sampling point falling into the preset area.

[0021] The areas of multiple circuit diagrams in the design layout of this layer are calculated based on the fall-in probability and the image area of ​​the design layout.

[0022] The average area of ​​multiple circuit diagrams is taken as the final circuit diagram area of ​​the design layout for this layer;

[0023] Sum the final circuit diagram area of ​​each layer.

[0024] Preferably, obtaining the final circuit diagram area in the design layout includes the following steps: calculating the preprocessed circuit diagram area based on the fall probability and the image area of ​​the design layout, and performing confidence analysis on the preprocessed circuit diagram area to obtain the final circuit diagram area.

[0025] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: an apparatus applied to the above-mentioned method for obtaining the circuit area of ​​integrated circuit design layout, the apparatus comprising:

[0026] Extraction module: Used to obtain the image area of ​​the design layout;

[0027] Identification module: Used to identify sampling points in the circuit diagram of a preset area;

[0028] Calculation module: used to calculate the number and probability of sampling points falling in the circuit diagram of the preset area and / or to calculate and obtain the final circuit diagram area in the design layout based on the falling probability and the image area of ​​the design layout;

[0029] Output module: Used to output the area value of the final circuit diagram.

[0030] To solve the above-mentioned technical problems, the present invention provides another technical solution as follows: a computer device applied to the above-mentioned method for obtaining the circuit area of ​​integrated circuit design layout, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the above-mentioned computer program to implement the method for obtaining the circuit area of ​​integrated circuit design layout.

[0031] Compared with the prior art, the integrated circuit design layout circuit area acquisition method, apparatus, and computer equipment provided by the present invention have the following beneficial effects:

[0032] 1. This invention provides a method for obtaining the circuit area of ​​an integrated circuit design layout, comprising the following steps: obtaining the image area of ​​the design layout; defining a preset region on the design layout and uniformly distributing a preset number of sampling points within the preset region; calculating the number of sampling points falling into the circuit diagram of the preset region and the probability of falling into the circuit diagram; and calculating the final circuit diagram area in the design layout based on the falling into the circuit diagram and the image area of ​​the design layout. The circuit diagram can be a curve or a polygon. In existing designs, the circuit diagram is usually a polygon, that is, the geometric shape formed by the closed circuit diagram is a polygon. By defining a preset region on the design layout and uniformly distributing sampling points within the preset region, identifying the number of sampling points falling into the polygon diagram of the preset region, and then calculating the probability of the sampling points falling into the polygon, the final circuit diagram area in the design layout can be obtained by calculating based on the falling into the circuit diagram and the image area of ​​the design layout. This method is simple and convenient, and can quickly improve the efficiency of circuit diagram area calculation in the layout, filling the gap in the field of full layout area calculation.

[0033] 2. The method for obtaining the image area of ​​a design layout according to this embodiment of the invention includes the following steps: obtaining the image area of ​​each layer in a design layout with a preset number of layers; calculating the final circuit diagram area in each layer of the design layout; and summing the final circuit diagram areas of each layer; wherein the preset number of layers is 8-40 layers. Design layouts are often very complex; by first identifying the area of ​​the circuit diagram in a single layer and then calculating the area of ​​the final circuit diagram, the computational load is small and the efficiency is high.

[0034] 3. The method of defining a preset area on the design layout in this embodiment includes the following steps: identifying the center point of the design layout; establishing two reference axes based on the center point, and setting a strip-shaped preset area based on the two reference axes; calculating the area of ​​the circuit diagram in the design layout by calculating the probability that a sampling point within the cross-shaped area falls into the circuit diagram. This method is efficient and convenient. Furthermore, establishing a cross-shaped area makes the calculated area result more accurate.

[0035] 4. The reference axis in this embodiment of the invention is at least one of the axis of symmetry or the diagonal of the design layout. The variety of reference axes allows users to select different types of reference axes to set preset areas according to their needs.

[0036] 5. The method of uniformly distributing a preset number of sampling points within a preset area according to an embodiment of the present invention includes the following steps: uniformly distributing a preset number of sampling points in an array within the preset area. The sampling points are evenly distributed within the preset area through an array distribution, ensuring that the distance between adjacent sampling points within the preset area is equal, thereby improving the accuracy of the subsequent calculation of the probability of falling into the target area.

[0037] 6. The method for calculating the number of sampling points and the probability of sampling points falling within a preset area in the circuit diagram of this invention includes the following steps: using the cross-point counting method to determine whether each sampling point is within the circuit diagram; counting the total number of sampling points falling within the circuit diagram as the number of sampling points; and obtaining the probability of sampling points based on the number of sampling points and the preset number. The cross-point counting method can easily determine whether a sampling point falls within the circuit diagram, and then count the number of sampling points falling within the circuit diagram in the preset area, which is simple and convenient.

[0038] 7. After obtaining the image area of ​​each layer in the design layout with a preset number of layers, the embodiment of the present invention further includes the following steps: defining multiple preset regions of different sizes on each layer of the design layout, and calculating the probability of sampling points falling into each of the multiple preset regions; or, defining a preset region on each layer of the design layout, generating multiple types of sampling points within the preset region, and calculating the probability of each type of sampling point falling into the preset region; calculating multiple circuit diagram areas in the design layout of that layer based on the falling probability and the image area of ​​the design layout; taking the average of the multiple circuit diagram areas as the final circuit diagram area of ​​the design layout of that layer; and summing the final circuit diagram areas of each layer. By obtaining the falling probability in multiple ways, and then calculating the average area of ​​the circuit diagram, the accuracy of the calculated structure is effectively improved.

[0039] 8. Obtaining the final circuit diagram area in the design layout according to embodiments of the present invention includes the following steps: calculating the preprocessed circuit diagram area based on the fall-in probability and the image area of ​​the design layout; and performing confidence analysis on the preprocessed circuit diagram area to obtain the final circuit diagram area. Verifying the circuit diagram area through confidence analysis improves accuracy.

[0040] 9. The present invention also provides an apparatus that has the same beneficial effects as the above-described method for obtaining the circuit area of ​​an integrated circuit design layout, and will not be described in detail here.

[0041] 10. This invention also provides a computer device that has the same beneficial effects as the above-described method for obtaining the circuit area of ​​an integrated circuit design layout, and will not be described in detail here. Attached Figure Description

[0042] Figure 1 This is a schematic flowchart of a method for obtaining the circuit area of ​​an integrated circuit design layout provided by an embodiment of the present invention.

[0043] Figure 2 This is a schematic diagram illustrating the process of defining a preset area on the design layout in an integrated circuit design layout circuit area acquisition method provided by an embodiment of the present invention.

[0044] Figure 3 This is a schematic diagram illustrating the process of identifying the number of sampling points falling in the circuit diagram of a preset area in an integrated circuit design layout circuit area acquisition method provided by an embodiment of the present invention.

[0045] Figure 4 This is a schematic diagram illustrating the calculation process for obtaining the final circuit diagram area, as provided in an embodiment of the present invention, of a method for obtaining the circuit area of ​​an integrated circuit design layout.

[0046] Figure 5 This is a schematic flowchart of a method for determining the number of cross intersections in an integrated circuit design layout circuit area acquisition method provided by an embodiment of the present invention.

[0047] Figure 6 This is a schematic diagram of a predefined area defined on a single-layer design layout provided in an embodiment of the present invention. Figure 1 .

[0048] Figure 7 This is a schematic diagram of a predefined area defined on a single-layer design layout provided in an embodiment of the present invention. Figure 2 .

[0049] Figure 8 This is a schematic diagram of a device structure provided in an embodiment of the present invention.

[0050] Figure 9 This is a schematic diagram of a computer device structure provided in an embodiment of the present invention.

[0051] Explanation of reference numerals in the attached diagram:

[0052] 1. Device; 2. Computer equipment;

[0053] 11. Extraction module; 12. Recognition module; 13. Calculation module; 14. Output module; 21. Memory; 22. Processor; 23. Computer program. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0055] In the embodiments provided by this invention, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined based on A. However, it should also be understood that determining B based on A does not mean determining B solely based on A; B can also be determined based on A and / or other information.

[0056] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the invention. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Those skilled in the art should also recognize that the embodiments described in the specification are optional embodiments, and the actions and modules involved are not necessarily essential to the invention.

[0057] In various embodiments of the present invention, it should be understood that the sequence number of each process does not necessarily imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0058] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It is particularly important to note that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0059] For ease of understanding, this embodiment will first explain layout design. Layout design refers to the series of geometric figures that an integrated circuit designer transforms into a series of geometric figures after designing and optimizing the circuit. It includes physical information data related to the device, such as the integrated circuit dimensions and the topology definitions of each layer. The figures on the mask determine the dimensions of the devices or physical layers on the chip. Therefore, the dimensions of the geometric figures on the layout are directly related to the dimensions of the physical layers on the chip. In very large-scale integrated circuit manufacturing processes, layout design can map the designed circuit diagram to the physical description layer, thereby mapping the designed circuit onto the wafer for production. The design layout contains graphical representations of the integrated circuit's device type, device size, relative positions between devices, and connection relationships between devices.

[0060] When designing a layout, basic design rules include minimum size limits, spacing, enclosure, overlap, and line width rules.

[0061] The minimum size limit refers to the minimum line width that can be achieved by photolithography in integrated circuit manufacturing processes, such as 28nm chips or 14nm chips.

[0062] Spacing refers to the distance between the outer boundaries of various geometric shapes in a layout. In layout design, designers need to distinguish between the design pattern and the blank areas. Therefore, the spacing is usually smaller than the minimum size to avoid the spacing and the design layout overlapping.

[0063] Enclosing refers to the process of forming an enclosure around the chip after the entire chip layout design is completed, in order to protect the internal circuitry. The enclosure is usually smaller than the minimum size to avoid the enclosure and the design layout overlapping.

[0064] Overlap refers to the length from the inner boundary of one geometric shape to the inner boundary of another shape. When designing, it is necessary to avoid the phenomenon of short circuits caused by overlapping lines.

[0065] Linewidth refers to the minimum size that can be photolithographically etched, which is determined by a specific process. It is generally equal to the minimum width of the channel.

[0066] To meet the above basic design rules and achieve VLSI manufacturing, the circuit diagrams in the layout are extremely complex, often containing multiple layers. The overlapping of these layers further complicates the circuit diagram. Furthermore, as the area of ​​the design layout decreases, the calculation of the graphic area within the layout becomes increasingly complex. Current techniques classify the various sections of the circuit diagram, calculate their respective ideal areas, and then piece together the data to calculate the total layout area. This process is extremely time-consuming and falls far short of user requirements in terms of time efficiency.

[0067] Please see Figure 1 This invention provides a method for obtaining the circuit area of ​​an integrated circuit design layout, comprising the following steps:

[0068] S1, obtain the image area of ​​the design layout;

[0069] S2, define a preset area on the design map and evenly distribute a preset number of sampling points within the preset area;

[0070] S3, calculate the number of sampling points and the probability of falling into the circuit diagram of the preset area;

[0071] S4 calculates the final circuit area in the design layout based on the falling probability and the image area of ​​the design layout.

[0072] Understandably, circuit diagrams can be curves or polygons. In existing designs, circuit diagrams are typically polygons, meaning the closed geometric shape formed by the circuit diagram is a polygon. By defining a preset area on the design layout and uniformly distributing sampling points within that area, the number of sampling points falling into the polygonal shape of the preset area is identified. Then, the probability of each sampling point falling into a polygon is calculated. Based on the probability of falling into a polygon and the area of ​​the design layout, the final circuit diagram area in the design layout can be calculated. This method is simple and convenient, and can quickly improve the efficiency of circuit diagram area calculation in the layout, filling the gap in the field of full layout area calculation.

[0073] In step S1 above, obtaining the image area of ​​the design layout specifically includes the following steps: obtaining the image area of ​​each layer in the design layout with a preset number of layers; calculating the final circuit diagram area in each layer of the design layout; and summing the final circuit diagram areas of each layer; the preset number of layers is 8-40 layers. It should be understood that the design layout is very complex. By first obtaining the design layout area of ​​each layer, then identifying the area of ​​the circuit diagram in a single layer to calculate the area of ​​the circuit diagram in each layer of the design layout, and finally summing the areas of the circuit diagrams in each layer of the design layout, the area of ​​the final circuit diagram can be calculated. This method involves less computation and is highly efficient.

[0074] Please combine Figure 1 and Figure 2 In step S2 above, defining the preset area on the design layout includes the following steps:

[0075] S21, Identify the center point of the design layout;

[0076] S22, establish two reference axes based on the center point, and set a strip-shaped preset area based on the two reference axes.

[0077] It should be understood that the critical areas of the circuit diagram in the design layout are distributed near the center point of the design layout. Therefore, when defining the preset area, it is necessary to define the area near the center point as the preset area. If the defined preset area does not pass through the center point, there will be a significant lack of circuit diagram information in the preset area, and the circuit diagram area calculated subsequently by the probability of falling into the center point will have a large error compared with the actual area of ​​the circuit diagram. Therefore, the position of the center point of the design layout is first identified by a preset recognition device, and then two reference axes are established based on the center point. Specifically, the two reference axes are intersected and both pass through the center point.

[0078] In step S22 above, a strip-shaped preset area is set based on two reference axes. This strip-shaped area refers to a region formed within a preset distance on both sides of the reference axes, with the reference axes as the center lines. It should be noted that the size of the preset distance depends on the user's actual needs; it only needs to ensure that the width of the strip-shaped preset area set on both sides of the reference axes is less than or equal to the minimum size of the design layout. Please refer to this in conjunction with... Figure 6 and Figure 7Specifically, the reference axis can be the diagonal of the design layout or the axis of symmetry of the design layout. Preferably, the reference axis is the two axes of symmetry of the design layout, and a cross-shaped preset area is set based on the two axes of symmetry. It should be understood that, taking the screen where the design layout is located as the reference, the two axes of symmetry of the design layout are the X-axis and Y-axis on this plane, and the cross-shaped area formed on both sides of the two axes of symmetry is the preset area. By identifying the position of the center point, and using the two axes of symmetry of the design layout as the reference to form a cross-shaped area, and using the cross-shaped area as the preset area, the area of ​​the circuit diagram in the design layout can be calculated by calculating the probability that the sampling point within the cross-shaped area falls into the circuit diagram. This method is efficient and convenient. Moreover, by establishing the cross-shaped area, the calculated area result is more accurate.

[0079] In step S2 above, the process of uniformly distributing a preset number of sampling points within a preset area includes the following steps: uniformly distributing a preset number of sampling points in an array within the preset area.

[0080] It should be understood that the number of sampling points distributed is unrelated to the area of ​​the design layout, but rather to the complexity of the circuit diagram within the preset area. For example, if the circuit diagram is polygonal, a more complex polygon can be used to evenly distribute a larger number of sampling points within the preset area, thus improving the accuracy of the probability of falling into the polygon and consequently increasing the accuracy of the calculated circuit diagram area compared to the actual area of ​​the circuit diagram. Conversely, if the polygon is simple, a smaller number of sampling points can be evenly distributed within the preset area, improving the efficiency of obtaining the circuit diagram area. It should be noted that the sampling points are evenly distributed across the preset area using an array distribution method, ensuring that the distance between adjacent sampling points within the preset area is equal, resulting in better accuracy of the subsequently calculated probability of falling into the polygon.

[0081] Please combine Figure 1 and Figure 3 In step S3 above, calculating the number of sampling points and the probability of sampling points falling into the circuit diagram of the preset area includes the following steps:

[0082] S31 uses the cross-point discrimination method to determine whether each sampling point is within the circuit diagram;

[0083] S32, count the number of sampling points that fall into the circuit diagram to get the number of falling points;

[0084] S33, the probability of falling in is obtained based on the number of falling in and the preset number.

[0085] Please refer to the following: Figure 5 The method for determining the number of cross intersections specifically includes the following steps:

[0086] Obtain the coordinates of the sampling point, and draw a ray parallel to the X-axis with the sampling point as the starting point and infinity as the ending point;

[0087] Obtain the coordinates of the edges of the circuit diagram in the design layout;

[0088] Obtain each edge in the circuit diagram and determine whether the ray is parallel to the edge;

[0089] If so, obtain the coordinates of another sampling point and re-evaluate;

[0090] If not, then determine whether the sampling point is on the edge;

[0091] If so, then determine that the sampling point is within the circuit diagram;

[0092] If not, then determine whether the ray intersects the edge;

[0093] If not, then the sampling point is determined to be outside the circuit diagram;

[0094] If so, then determine the number of intersections between the ray and the edge;

[0095] If the number is odd, then the sampling point is determined to be within the circuit diagram;

[0096] If the number is even, then the sampling point is determined to be outside the circuit diagram.

[0097] The method of determining whether a sampling point falls within the circuit diagram can be used by counting the number of sampling points within the preset area. This method is simple and convenient.

[0098] Furthermore, in this embodiment of the invention, the probability of falling in is the ratio of the number of falling in to a preset number. For example, the design layout area M = 10 × 10 mm is obtained by extracting the preset extraction module 11. Please refer to the extraction module 11 for further details. Figure 6 The preset number of sampling points evenly distributed within the preset area is 200. After using the cross-point discrimination method, the number of sampling points falling into the circuit diagram is statistically determined to be 178. Therefore, the probability of falling into the circuit diagram is P = 178 ÷ 200 = 89%. Based on the probability of falling into the circuit diagram and the area of ​​the design layout image, the area of ​​the circuit diagram is calculated as: A = 10 × 10 × 89% = 89 mm. 2 This means that by obtaining the probability of a preset region's sampling points falling into the circuit diagram, the area of ​​the final circuit diagram can be quickly calculated. It is simple and convenient, and further improves the efficiency of circuit diagram acquisition.

[0099] Please combine Figure 1 and Figure 4 As a variation, in step S3 above, after obtaining the image area of ​​each layer in the design layout with a preset number of layers, the following steps are also included:

[0100] S301, define multiple preset areas of different sizes on each layer of the design layout, and calculate the probability of sampling points falling into each of the multiple preset areas;

[0101] S302, or, define a preset area on each layer of the design layout, and generate multiple types of sampling points within the preset area, and calculate the probability of each type of sampling point falling into the preset area respectively;

[0102] S303, calculates the area of ​​multiple circuit diagrams in the design layout of this layer based on the falling probability and the image area of ​​the design layout;

[0103] S304, take the average of the areas of multiple circuit diagrams as the final circuit diagram area of ​​the design layout of this layer;

[0104] S305, sum up the final circuit diagram area of ​​each layer.

[0105] Understandably, there are multiple methods for calculating the probability of obtaining a sampling point. Optionally, the user can choose to define multiple preset areas of different sizes on the design layout and calculate the probability of a sampling point falling into each of the multiple preset areas.

[0106] Specifically, the center point of the design layout is identified, and two reference axes are established based on this center point. These reference axes are the axes of symmetry of the design layout. Pre-defined cross-shaped regions, each with dimensions of m×n, are then defined based on these axes of symmetry. For example, three pre-defined regions are defined on the design layout, with bandwidths of 20×10, 10×5, and 20×5, respectively. Sampling points are evenly distributed across these three regions, and the probability of each sampling point falling into the region is calculated as P1, P2, and P3, respectively. As a variation, the user can choose to define a pre-defined region on the design layout and generate multiple types of sampling points within that region. Specifically, the type of sampling point is related to the distance between adjacent sampling points; that is, different types of sampling points have different distances between adjacent points. Users can choose between dense or sparse sampling points according to their needs. For example, the center point of the design layout is identified, and two reference axes are established based on the center point. These reference axes are the axes of symmetry of the design layout. A cross-shaped preset region with dimensions m×n is set based on these axes of symmetry. Three types of sampling points are evenly distributed within this region, with different distances between adjacent sampling points of each type. The probability of a sampling point falling within this preset region is calculated as P4, P5, and P6. This embodiment can obtain the falling probability in multiple ways, thereby calculating the average area of ​​the circuit diagram, effectively improving the accuracy of the calculated structure.

[0107] In step S304 above, the average of multiple circuit diagram areas is taken to obtain the final circuit diagram area. It should be understood that after obtaining the fall probability using the method described above, multiple circuit diagram areas are calculated based on the multiple fall probabilities and the image area of ​​the design layout. For example, if the design layout area is M, the circuit diagram areas that can be obtained based on fall probabilities P1, P2, and P3 are A1, A2, and A3, respectively; then the final circuit diagram area is: A0 = (A1 + A2 + A3) ÷ 3. Calculating the average of multiple circuit diagram areas as the final circuit diagram area results in higher accuracy.

[0108] In step S4 above, obtaining the final circuit diagram area in the design layout includes the following steps: calculating the preprocessed circuit diagram area based on the fall probability and the image area of ​​the design layout, and performing confidence analysis on the preprocessed circuit diagram area to obtain the final circuit diagram area.

[0109] It should be understood that the preprocessed circuit diagram area can be obtained by calculating the fall-in probability and the image area of ​​the design layout. After obtaining the preprocessed circuit diagram area, a confidence analysis is performed. The confidence analysis is as follows: the average area of ​​the preprocessed circuit diagram is defined as A, and the probability that the test area A is distributed in the interval [A-3σ, A+3σ] is given, where σ is the standard deviation of the standard layout area, and A is the average area of ​​the layout. For example, if the confidence analysis of the average area of ​​the preprocessed circuit diagram yields a probability of 0.9974, it indicates that the preprocessed circuit diagram has high confidence, and thus its average area can be selected as the final circuit diagram area in the design layout. Confidence analysis is used to verify the area of ​​the circuit diagram, further enhancing the confidence of the final circuit diagram area.

[0110] Please combine Figure 1 and Figure 6 This invention also provides an apparatus 1, applied to the above-described method for obtaining the circuit area of ​​an integrated circuit design layout, the apparatus 1 comprising:

[0111] Extraction module 11: Used to obtain the image area of ​​the design layout;

[0112] Identification module 12: Used to identify sampling points in the circuit diagram of a preset area;

[0113] Calculation module 13: used to calculate the number and probability of sampling points falling in the circuit diagram of the preset area and / or to calculate and obtain the final circuit diagram area in the design layout based on the falling probability and the image area of ​​the design layout;

[0114] Output module 14: Used to output the area value of the final circuit diagram.

[0115] The apparatus 1 provided in this embodiment of the invention has the same beneficial effects as the above-described computational photolithography defect analysis method, and will not be described in detail here.

[0116] Please combine Figure 1 and Figure 7 The present invention also provides a computer device 2 for use in the above-mentioned method for obtaining the circuit area of ​​integrated circuit design layout, including a memory 21, a processor 22 and a computer program 23 stored in the memory 21, wherein the processor 22 executes the computer program 23 to implement the steps of the method for obtaining the circuit area of ​​integrated circuit design layout.

[0117] The computer device 2 provided in this embodiment of the invention has the same beneficial effects as the method for obtaining the circuit area of ​​the integrated circuit design layout described above, and will not be elaborated here.

[0118] Compared with the prior art, the integrated circuit design layout circuit area acquisition method, apparatus, and computer equipment provided by the present invention have the following beneficial effects:

[0119] 1. This invention provides a method for obtaining the circuit area of ​​an integrated circuit design layout, comprising the following steps: obtaining the image area of ​​the design layout; defining a preset region on the design layout and uniformly distributing a preset number of sampling points within the preset region; calculating the number of sampling points falling into the circuit diagram of the preset region and the probability of falling into the circuit diagram; and calculating the final circuit diagram area in the design layout based on the falling into the circuit diagram and the image area of ​​the design layout. The circuit diagram can be a curve or a polygon. In existing designs, the circuit diagram is usually a polygon, that is, the geometric shape formed by the closed circuit diagram is a polygon. By defining a preset region on the design layout and uniformly distributing sampling points within the preset region, identifying the number of sampling points falling into the polygon diagram of the preset region, and then calculating the probability of the sampling points falling into the polygon, the final circuit diagram area in the design layout can be obtained by calculating based on the falling into the circuit diagram and the image area of ​​the design layout. This method is simple and convenient, and can quickly improve the efficiency of circuit diagram area calculation in the layout, filling the gap in the field of full layout area calculation.

[0120] 2. The method for obtaining the image area of ​​a design layout according to this embodiment of the invention includes the following steps: obtaining the image area of ​​each layer in a design layout with a preset number of layers; calculating the final circuit diagram area in each layer of the design layout; and summing the final circuit diagram areas of each layer; wherein the preset number of layers is 8-40 layers. Design layouts are often very complex; by first identifying the area of ​​the circuit diagram in a single layer and then calculating the area of ​​the final circuit diagram, the computational load is small and the efficiency is high.

[0121] 3. The method of defining a preset area on the design layout in this embodiment includes the following steps: identifying the center point of the design layout; establishing two reference axes based on the center point, and setting a strip-shaped preset area based on the two reference axes; calculating the area of ​​the circuit diagram in the design layout by calculating the probability that a sampling point within the cross-shaped area falls into the circuit diagram. This method is efficient and convenient. Furthermore, establishing a cross-shaped area makes the calculated area result more accurate.

[0122] 4. The reference axis in this embodiment of the invention is at least one of the axis of symmetry or the diagonal of the design layout. The variety of reference axes allows users to select different types of reference axes to set preset areas according to their needs.

[0123] 5. The method of uniformly distributing a preset number of sampling points within a preset area according to an embodiment of the present invention includes the following steps: uniformly distributing a preset number of sampling points in an array within the preset area. The sampling points are evenly distributed within the preset area through an array distribution, ensuring that the distance between adjacent sampling points within the preset area is equal, thereby improving the accuracy of the subsequent calculation of the probability of falling into the target area.

[0124] 6. The method for calculating the number of sampling points and the probability of sampling points falling within a preset area in the circuit diagram of this invention includes the following steps: using the cross-point counting method to determine whether each sampling point is within the circuit diagram; counting the total number of sampling points falling within the circuit diagram as the number of sampling points; and obtaining the probability of sampling points based on the number of sampling points and the preset number. The cross-point counting method can easily determine whether a sampling point falls within the circuit diagram, and then count the number of sampling points falling within the circuit diagram in the preset area, which is simple and convenient.

[0125] 7. After obtaining the image area of ​​each layer in the design layout with a preset number of layers, the embodiment of the present invention further includes the following steps: defining multiple preset regions of different sizes on each layer of the design layout, and calculating the probability of sampling points falling into each of the multiple preset regions; or, defining a preset region on each layer of the design layout, generating multiple types of sampling points within the preset region, and calculating the probability of each type of sampling point falling into the preset region; calculating multiple circuit diagram areas in the design layout of that layer based on the falling probability and the image area of ​​the design layout; taking the average of the multiple circuit diagram areas as the final circuit diagram area of ​​the design layout of that layer; and summing the final circuit diagram areas of each layer. By obtaining the falling probability in multiple ways, and then calculating the average area of ​​the circuit diagram, the accuracy of the calculated structure is effectively improved.

[0126] 8. Obtaining the final circuit diagram area in the design layout according to embodiments of the present invention includes the following steps: calculating the preprocessed circuit diagram area based on the fall-in probability and the image area of ​​the design layout; and performing confidence analysis on the preprocessed circuit diagram area to obtain the final circuit diagram area. Verifying the circuit diagram area through confidence analysis improves accuracy.

[0127] 9. The present invention also provides an apparatus that has the same beneficial effects as the above-described method for obtaining the circuit area of ​​an integrated circuit design layout, and will not be described in detail here.

[0128] 10. This invention also provides a computer device that has the same beneficial effects as the above-described method for obtaining the circuit area of ​​an integrated circuit design layout, and will not be described in detail here.

[0129] The foregoing has provided a detailed description of a method, apparatus, and computer device for obtaining the circuit area of ​​an integrated circuit design layout, as disclosed in the embodiments of the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention. Any modifications, equivalent substitutions, and improvements made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for obtaining the circuit area of ​​an integrated circuit design layout, characterized in that: Includes the following steps: Obtain the image area of ​​the design layout; A preset area is defined on the design layout, and a preset number of sampling points are evenly distributed within the preset area. The center point of the design layout is identified, two reference axes are established based on the center point, and a cross-shaped area is set as the preset area based on the two reference axes. The reference axes are the axes of symmetry of the design layout. Calculate the number of sampling points and the probability of sampling points falling into the circuit diagram of the preset area; The final circuit diagram area in the design layout is calculated based on the fall probability and the image area of ​​the design layout.

2. The method for obtaining the circuit area of ​​an integrated circuit design layout as described in claim 1, characterized in that: The specific steps for obtaining the image area of ​​the design layout include the following: obtaining the image area of ​​each layer in the design layout with a preset number of layers; calculating the final circuit diagram area of ​​each layer in the design layout; and summing the final circuit diagram areas of each layer. The preset number of layers is 8-40 layers.

3. The method for obtaining the circuit area of ​​an integrated circuit design layout as described in claim 1, characterized in that: The step of uniformly distributing a preset number of sampling points within a preset area includes the following steps: uniformly distributing a preset number of sampling points in an array within the preset area.

4. The method for obtaining the circuit area of ​​an integrated circuit design layout as described in claim 1, characterized in that: The calculation of the number of sampling points and the probability of sampling points falling into the circuit diagram of the preset region includes the following steps: The cross-point counting method is used to determine whether each sampling point is within the circuit diagram; The total number of sampling points that fall within the circuit diagram is the number of points that fall within the circuit diagram. The probability of falling in is obtained based on the number of falls and the preset number.

5. The method for obtaining the circuit area of ​​an integrated circuit design layout as described in claim 2, characterized in that: After obtaining the image area of ​​each layer in the design layout with a preset number of layers, the following steps are also included: On each layer of the design plan, define multiple preset areas of different sizes, and calculate the probability of sampling points falling into each of the multiple preset areas. Alternatively, define a preset area on each layer of the design layout, generate multiple types of sampling points within the preset area, and calculate the probability of each type of sampling point falling into the preset area. The areas of multiple circuit diagrams in the design layout of this layer are calculated based on the fall-in probability and the image area of ​​the design layout. The average area of ​​multiple circuit diagrams is taken as the final circuit diagram area of ​​the design layout for this layer; Sum the final circuit diagram area of ​​each layer.

6. The method for obtaining the circuit area of ​​an integrated circuit design layout as described in claim 1, characterized in that: The process of obtaining the final circuit diagram area in the design layout includes the following steps: calculating the preprocessed circuit diagram area based on the fall probability and the image area of ​​the design layout, and performing confidence analysis on the preprocessed circuit diagram area to obtain the final circuit diagram area.

7. An apparatus applied to the method for obtaining the circuit area of ​​an integrated circuit design layout as described in any one of claims 1-6, characterized in that: The device includes: Extraction module: Used to obtain the image area of ​​the design layout; Identification module: used to identify sampling points in the circuit diagram of a preset area, wherein the center point of the design layout is identified, two reference axes are established based on the center point, and a cross-shaped area is set as the preset area based on the two reference axes, and the reference axes are the axes of symmetry of the design layout; Calculation module: used to calculate the number and probability of sampling points falling in the circuit diagram of the preset area and / or to calculate and obtain the final circuit diagram area in the design layout based on the falling probability and the image area of ​​the design layout; Output module: Used to output the area value of the final circuit diagram.

8. A computer device, applied to the method for obtaining the circuit area of ​​an integrated circuit design layout as described in any one of claims 1-6, characterized in that: The system includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the method for obtaining the circuit area of ​​the integrated circuit design layout.

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