Clock generation device for asynchronous memory

Abstract

The application is suitable for the field of electronic technology, and provides a clock generating device for asynchronous memory, which comprises a multi-pulse generating and converging circuit, an input end of the multi-pulse generating and converging circuit being connected with an address bus output by a memory controller, a filter clock reconstruction circuit, an input end of the filter clock reconstruction circuit being connected with an output end of the multi-pulse generating and converging circuit, a clock confirmation circuit, an input end of the clock confirmation circuit being connected with an output end of the filter clock reconstruction circuit, an output end of the clock confirmation circuit being connected with an input end of a sensitive amplification circuit of the asynchronous memory, an address latching selection circuit, input ends of the address latching selection circuit being respectively connected with the address bus, the output end of the filter clock reconstruction circuit and the output end of the clock confirmation circuit, and an output end of the address latching selection circuit being connected with an input end of an address decoding circuit of the asynchronous memory. The application greatly reduces the dynamic power consumption of the asynchronous memory.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of electronics, and particularly relates to a clock generation device for an asynchronous memory. BACKGROUND

[0002] At present, single-chip parallel port asynchronous memories are still widely applied in electronic systems such as data temporary storage, instruction storage and storage-computing integration, for example, a pseudo static random access memory (PSRAM), a parallel nonvolatile memory (Nor Flash), a parallel magnetoresistive random access memory (MRAM) and a parallel resistance random access memory (RRAM). Such asynchronous memories have simple parallel bus interfaces, are easy to interconnect and convenient for bus sharing; the asynchronous memories respond to read data only when there is a change in address or control signals, and therefore have low power consumption; as instruction cache (Cache) applications, the asynchronous memories have the advantage of execute in place (XIP) instructions, and instruction codes can be directly run in the memory without being read into a system random access memory (RAM), thereby simplifying system program scheduling. Compared with synchronous memories such as double data rate synchronous dynamic random access memory (DDR), the parallel port asynchronous memory has no clock port on the interface, but uses the transition of address chip selection signals and other signals to trigger the read and write operations of the memory. The period of address change is equivalent to the clock period of the synchronous memory, and when there is no change in the address and chip selection control signals, the asynchronous memory is in a low-power standby state. Therefore, the parallel port asynchronous memory contains an address transition detection (ATD) circuit. The main function of the ATD circuit is to detect the transition of external address and chip selection control signals and generate a clock signal, which controls the data readout of the memory.

[0003] Due to the difference in delay of each input / output (IO) of the previous stage controller and the difference in signal board-level wiring path, the time of each signal of the address bus and the control line to reach the pin of the memory is not equal, which is called signal input delay skew. Each address line generates a clock, and there is input signal delay skew, which generates multiple high pulses with different time intervals. However, except for the last pulse which is the effective pulse, the previous pulses are invalid pulses, because the previous addresses are still in an unstable state. These unstable addresses and invalid clock pulses control the decoding, sensitive amplification and input / output logic inversion of the memory, which greatly consumes dynamic power consumption.

[0004] The common solution is to add a filter circuit for filtering multiple pulses in the memory ATD clock generation circuit, but the filter circuit can only filter invalid clocks with a preset fixed time, and the non-final valid address is still latched and decoded, so this method can only reduce the dynamic power consumption to a certain extent. SUMMARY

[0005] Embodiments of the present application provide a clock generation device for an asynchronous memory, which can solve the problem of high dynamic power consumption of the asynchronous memory.

[0006] Embodiments of the present application provide a clock generation device for an asynchronous memory, which comprises:

[0007] A multiple pulse generation and convergence circuit, an input end of the multiple pulse generation and convergence circuit being connected with an address bus output by a storage controller, the storage controller being used for controlling read and write operations of the asynchronous memory;

[0008] A filter clock reconstruction circuit, an input end of the filter clock reconstruction circuit being connected with an output end of the multiple pulse generation and convergence circuit;

[0009] A clock confirmation circuit, an input end of the clock confirmation circuit being connected with an output end of the filter clock reconstruction circuit, and an output end of the clock confirmation circuit being connected with an input end of a sense amplifier circuit of the asynchronous memory;

[0010] An address latch selection circuit, input ends of the address latch selection circuit being connected with the address bus, the output end of the filter clock reconstruction circuit and the output end of the clock confirmation circuit respectively, and an output end of the address latch selection circuit being connected with an input end of an address decoding circuit of the asynchronous memory;

[0011] The multiple pulse generation and convergence circuit is used for processing multiple address signals output by the address bus to obtain a high-level pulse sequence; the filter clock reconstruction circuit is used for filtering the high-level pulse sequence and reconstructing the filtered high-level pulse sequence; the clock confirmation circuit is used for confirming whether the reconstructed high-level pulse sequence is a single pulse sequence; and the address latch selection circuit is used for outputting a signal of the address bus to the address decoding circuit when the reconstructed high-level pulse sequence is the single pulse sequence.

[0012] Optionally, the multiple pulse generation and convergence circuit comprises:

[0013] A plurality of rising and falling edge triggered pulse circuits, input ends of the plurality of rising and falling edge triggered pulse circuits being connected with a plurality of address lines included in the address bus, the plurality of rising and falling edge triggered pulse circuits corresponding to the plurality of address lines one by one, and each rising and falling edge triggered pulse circuit being used for processing an address signal output by an address line connected with the rising and falling edge triggered pulse circuit to obtain a high-level pulse;

[0014] a first OR gate, an input end of the first OR gate being connected with the output ends of the plurality of up / down edge triggered pulse circuits, and an output end of the first OR gate being connected with an input end of the filtered clock reconstruction circuit, the first OR gate being used for converging high level pulses output by the plurality of up / down edge triggered pulse circuits to obtain a high level pulse sequence.

[0015] Optionally, the up / down edge triggered pulse circuit comprises an up edge triggered circuit, a down edge triggered circuit and a second OR gate.

[0016] The up edge triggered circuit comprises a first delay unit, a first inverter, a first AND gate, and the down edge triggered circuit comprises a second inverter, a second delay unit, a third inverter and a second AND gate.

[0017] An input end of the first delay unit is connected with an address line, a first input end of the first AND gate and an input end of the second inverter respectively, an output end of the first delay unit is connected with an input end of the first inverter, an output end of the first inverter is connected with a second input end of the first AND gate, an output end of the first AND gate is connected with a first input end of the second OR gate, and an output end of the second OR gate is connected with an input end of the first OR gate.

[0018] An output end of the second inverter is connected with an input end of the second delay unit and a first input end of the second AND gate respectively, an output end of the second delay unit is connected with an input end of the third inverter, an output end of the third inverter is connected with a second input end of the second AND gate, and an output end of the second AND gate is connected with a second input end of the second OR gate.

[0019] Optionally, the filtered clock reconstruction circuit comprises a third AND gate, a filter circuit, a first flip-flop, a first reset unit, a second flip-flop, a second reset unit and a sampling pulse generation unit.

[0020] A first input end of the third AND gate is connected with an output end of the multi-pulse generation convergence circuit, an output end of the third AND gate is connected with an input end of the filter circuit, an output end of the filter circuit is connected with a clock end of the first flip-flop, an output end of the first flip-flop is connected with an input end of the first reset unit and an input end of the clock confirmation circuit respectively, an output end of the first reset unit is connected with a reset end of the first flip-flop, a second input end of the third AND gate and a clock end of the second flip-flop respectively, an output end of the second flip-flop is connected with an input end of the second reset unit and an input end of the sampling pulse generation unit respectively, an output end of the second reset unit is connected with a reset end of the second flip-flop, an output end of the sampling pulse generation unit is connected with an input end of the clock confirmation circuit, and a data end of the first flip-flop and a data end of the second flip-flop are connected with high level.

[0021] Optionally, the first reset unit comprises a fourth inverter and a third delay unit, an input end of the fourth inverter is connected with an output end of the first flip-flop, an output end of the fourth inverter is connected with an input end of the third delay unit, and an output end of the third delay unit is connected with a reset end of the first flip-flop, a second input end of the third AND gate and a clock end of the second flip-flop respectively.

[0022] The second reset unit comprises a fifth inverter and a fourth delay unit, an input end of the fifth inverter is connected with an output end of the second flip-flop, an output end of the fifth inverter is connected with an input end of the fourth delay unit, and an output end of the fourth delay unit is connected with a reset end of the second flip-flop.

[0023] Optionally, the sampling pulse generation unit comprises a fifth delay unit, a sixth delay unit, a seventh delay unit and an eighth delay unit.

[0024] An input end of the fifth delay unit is connected with an output end of the second flip-flop, an output end of the fifth delay unit is connected with an input end of the sixth delay unit, an output end of the sixth delay unit is connected with an input end of the seventh delay unit and an input end of the clock confirmation circuit respectively, an output end of the seventh delay unit is connected with an input end of the eighth delay unit and an input end of the clock confirmation circuit respectively, and an output end of the eighth delay unit is connected with an input end of the clock confirmation circuit.

[0025] Optionally, the clock confirmation circuit comprises a third flip-flop, a fourth flip-flop, a fifth flip-flop, a NOR gate, a third reset unit, a clock end of the third flip-flop is connected with an output end of the sixth delay unit, a data end of the third flip-flop is connected with an output end of the first flip-flop, an output end of the third flip-flop is connected with a first input end of the NOR gate, a clock end of the fourth flip-flop is connected with an output end of the seventh delay unit, a data end of the fourth flip-flop is connected with an output end of the first flip-flop, an output end of the fourth flip-flop is connected with a second input end of the NOR gate, a clock end of the fifth flip-flop is connected with an output end of the eighth delay unit, a data end of the fifth flip-flop is connected with an output end of the first flip-flop, an output end of the fifth flip-flop is connected with a third input end of the NOR gate, an output end of the NOR gate is connected with an input end of a sensitive amplification circuit of the asynchronous memory, an input end of the third reset unit and an input end of an address latch selection circuit respectively, and output ends of the third reset unit are connected with reset ends of the third flip-flop, the fourth flip-flop and the fifth flip-flop respectively.

[0026] Optionally, the third reset unit comprises a sixth inverter and a ninth delay unit, an input end of the sixth inverter is connected with an output end of the NOR gate, an output end of the sixth inverter is connected with an input end of the ninth delay unit, and output ends of the ninth delay unit are connected with reset ends of the third flip-flop, the fourth flip-flop and the fifth flip-flop respectively.

[0027] Optionally, the address latch selection circuit comprises a sixth flip-flop and a fourth AND gate, the clock end of the sixth flip-flop is connected with the output end of the seventh delay unit, the data end of the sixth flip-flop is connected with the address bus, the output end of the sixth flip-flop is connected with the first input end of the fourth AND gate, the second input end of the fourth AND gate is connected with the output end of the NOR gate, and the output end of the fourth AND gate is connected with the input end of the address decoding circuit of the asynchronous memory.

[0028] The above-mentioned scheme of the present application has the following advantages:

[0029] In the embodiment of the present application, the multiple address signals output by the address bus are processed by the multiple pulse generation converging circuit to obtain a high-level pulse sequence, the high-level pulse sequence glitches triggered by the input address skew are filtered out by the filter clock reconstruction circuit, the filtered high-level pulse sequence is clocked, the reconstructed high-level pulse sequence is confirmed by the clock confirmation circuit to be a single pulse sequence, and when it is determined that the reconstructed high-level pulse sequence is a single pulse sequence, the signal of the address bus is output to the address decoding circuit of the asynchronous memory by the address latch selection circuit. Since the clock confirmation circuit outputs the final single pulse sequence to trigger the address latch selection circuit to release the valid address to the asynchronous memory only when the address is stable and valid, the invalid clock can be triggered less in the address access period, the asynchronous memory is prevented from being accessed multiple times invalidly, and the dynamic power consumption of the asynchronous memory is greatly reduced.

[0030] Other advantages of the present application will be described in detail in the following specific implementation part. BRIEF DESCRIPTION OF DRAWINGS

[0031] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0032] Figure 1 The structural schematic diagram of the clock generation device for the asynchronous memory provided by an embodiment of the present application is shown in the figure.

[0033] Figure 2 The timing schematic diagram of the asynchronous memory address access control provided by an embodiment of the present application is shown in the figure.

[0034] Figure 3 The circuit structural diagram of the clock generation device for the asynchronous memory provided by an embodiment of the present application is shown in the figure.

[0035] Figure 4A structure diagram of a delay unit provided by an embodiment of the present application is shown in the figure.

[0036] Figure 5 A detailed timing diagram of a clock generating device for an asynchronous memory provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0037] In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular sequences of steps, techniques, etc., in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, and circuits are omitted so as not to obscure the description of the present application with unnecessary detail.

[0038] It is to be understood that the terminology "includes", "has", "holds", "contains" and / or "comprising", when used in this specification and in the following claims, indicates the presence of the described features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0039] It is also to be understood that the terminology "and / or", when used in this specification and in the following claims, indicates any and all possible combinations of the associated listed items and that the expression includes the combinations of the items themselves and the collection of possible combinations.

[0040] As used in this specification and in the claims, the terms "if" and "when" can be interpreted to mean "upon" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]", depending on the context.

[0041] In addition, in the description of the specification and the appended claims, the terms "first", "second", "third", etc. are used only to distinguish descriptions, and cannot be understood as indicating or implying relative importance.

[0042] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. The terms "including," "comprising," "having" and variations thereof are meant to encompass the items listed thereafter and equivalents thereof as well as additional items.

[0043] At present, in solving the problem of large dynamic power consumption of asynchronous memory, the common solution is to add a filter circuit for filtering multiple pulses in the memory ATD clock generation circuit, but this filter circuit can only filter the invalid clock of a preset fixed time, and the non-final valid address is still latched and decoded, so this method can only reduce the dynamic power consumption to a certain extent.

[0044] To solve the above problems, the embodiment of the present application provides a clock generation device for asynchronous memory. The device processes multiple address signals output by an address bus through a multiple pulse generation and convergence circuit to obtain a high-level pulse sequence, filters the high-level pulse sequence glitches triggered by input address skew through a filter clock reconstruction circuit, reconstructs the filtered high-level pulse sequence, confirms whether the reconstructed high-level pulse sequence is a single pulse sequence through a clock confirmation circuit, and outputs the signal of the address bus to the address decoding circuit of the asynchronous memory through an address latch selection circuit when it is determined that the reconstructed high-level pulse sequence is a single pulse sequence. Since the clock confirmation circuit outputs the final single pulse sequence to trigger the address latch selection circuit to release the valid address to the asynchronous memory only when the address is stable and valid, the invalid clock can be triggered less during the address access period, the invalid access to the memory is avoided, and the dynamic power consumption of the asynchronous memory is greatly reduced.

[0045] The clock generation device for asynchronous memory provided by the present application will be exemplarily described in combination with specific embodiments.

[0046] In some embodiments of the present application, the working process of the clock generation device for asynchronous memory mainly includes four stages of multiple pulse generation and convergence, filter and clock reconstruction, single pulse confirmation and final clock generation, address latching and selection release, corresponding to each part of the clock generation device for asynchronous memory.

[0047] As Figure 1As shown, the asynchronous memory clock generation device provided in this application embodiment includes: a multi-pulse generation and convergence circuit 101, a filtered clock reconstruction circuit 102, a clock confirmation circuit 103, and an address latch selection circuit 104.

[0048] The input terminal of the multi-pulse generation and convergence circuit 101 is connected to the address bus 100 output by the memory controller; the input terminal of the filter clock reconstruction circuit 102 is connected to the output terminal of the multi-pulse generation and convergence circuit 101; the input terminal of the clock confirmation circuit 103 is connected to the output terminal of the filter clock reconstruction circuit 102; the output terminal of the clock confirmation circuit 103 is connected to the input terminal of the sensitive amplifier circuit 105 of the asynchronous memory; the input terminal of the address latch selection circuit 104 is connected to the address bus 100, the output terminal of the filter clock reconstruction circuit 102, and the output terminal of the clock confirmation circuit 103, respectively; and the output terminal of the address latch selection circuit 104 is connected to the input terminal of the address decoding circuit 106 of the asynchronous memory.

[0049] The aforementioned storage controller is a controller used to control the read and write operations of the asynchronous memory. The aforementioned multi-pulse generation and convergence circuit 101 is used to process multiple address signals output from the address bus 100 to obtain a high-level pulse sequence. The aforementioned filtering clock reconstruction circuit 102 is used to filter the high-level pulse sequence and reconstruct the clock of the filtered high-level pulse sequence. The aforementioned clock confirmation circuit 103 is used to confirm whether the reconstructed high-level pulse sequence is a single-pulse sequence. The aforementioned address latch selection circuit 104 is used to output the signal of the address bus 100 to the address decoding circuit 106 when the reconstructed high-level pulse sequence is a single-pulse sequence, so that the asynchronous memory completes the read and write operations according to the signal of the address bus 100.

[0050] In some embodiments of this application, the multi-pulse generation and convergence circuit corresponds to the multi-pulse generation and convergence stage, the filter clock reconstruction circuit corresponds to the filtering and clock reconstruction stage, the clock confirmation circuit corresponds to the single-pulse confirmation and final clock generation stage, and the address latch selection circuit corresponds to the address latch and selection release stage.

[0051] It is worth mentioning that, in some embodiments of this application, since the clock confirmation circuit only outputs the final single-pulse sequence to trigger the address latch selection circuit to release the valid address to the asynchronous memory when the address is stable and valid, the invalid clock is triggered less during the address access cycle, avoiding multiple invalid accesses to the memory and greatly reducing the dynamic power consumption of the asynchronous memory.

[0052] In some embodiments of this application, such as Figure 2 As shown, the storage controller accesses the asynchronous memory in address cycles t. AVAV The change triggers the read from memory with a delay t.AVQV The data is retrieved after collection, and due to the random access feature of the asynchronous memory, the rising edge and the falling edge of each address line (A[0]-A[n]) can individually trigger the clock.

[0053] wherein, Figure 2 A[n:0] is an address bus, t AVAV is an address period, DQ[n:0] is an input / output data bus, t AVQV is a readout delay of the memory, t AXQX is a time for stable data to unstable data in a previous access period, Previous Valid Data is stable data in the previous access period, and Valid Data is valid data read in the current access period.

[0054] In some embodiments of the present application, as shown in Figure 3 the multi-pulse generation convergence circuit includes:

[0055] a plurality of rising and falling edge triggered pulse circuits (such as Figure 3 I1 of the multi-pulse generation convergence circuit) and a first OR gate J0.

[0056] The input end of each of the plurality of rising and falling edge triggered pulse circuits I1 is connected to a plurality of address lines (A[0]-A[n]) included in the address bus, and the plurality of rising and falling edge triggered pulse circuits I1 correspond to the plurality of address lines one by one. The output end of each of the plurality of rising and falling edge triggered pulse circuits I1 is connected to the input end of the first OR gate J0, and the output end of the first OR gate J0 is connected to the input end of the filter clock reconstruction circuit.

[0057] Each of the plurality of rising and falling edge triggered pulse circuits I1 is used to process the address signal output by the address line connected to the rising and falling edge triggered pulse circuit I1, and obtain a high-level pulse.

[0058] It should be noted that the n address lines correspond to n rising edge triggered pulse circuits I1, and at most n high-level pulses can be generated.

[0059] Due to the delay skew of the signal reaching the asynchronous memory port caused by the front-stage driving and the printed circuit board (PCB) wiring, n high-level pulses with different phases can be generated. The OR gate is used to converge the high-level pulses output by the plurality of rising and falling edge triggered pulse circuits, and obtain a high-level pulse sequence CK0.

[0060] In some embodiments of the present application, the rising and falling edge triggered pulse circuit includes a rising edge triggered circuit, a falling edge triggered circuit, and a second OR gate U0.

[0061] The aforementioned upper edge triggering circuit includes a first delay unit X0, a first inverter X1, and a first AND gate U1, while the aforementioned lower edge triggering circuit includes a second inverter X2, a second delay unit X3, a third inverter X4, and a second AND gate U2.

[0062] The input terminal of the first delay unit X0 is connected to an address line, the first input terminal of the first AND gate U1, and the input terminal of the second inverter X2. The output terminal of the first delay unit X0 is connected to the input terminal of the first inverter X1. The output terminal of the first inverter X1 is connected to the second input terminal of the first AND gate U1. The output terminal of the first AND gate U1 is connected to the first input terminal of the second OR gate U0. The output terminal of the second OR gate U0 is connected to the input terminal of the first OR gate U0.

[0063] The output of the second inverter X2 is connected to the input of the second delay unit X3 and the first input of the second AND gate U2, respectively. The output of the second delay unit X3 is connected to the input of the third inverter X4. The output of the third inverter X4 is connected to the second input of the second AND gate U2. The output of the second AND gate U2 is connected to the second input of the second OR gate U0.

[0064] For example, when the detection address signal changes upward, the A[0] address signal passes through the first delay unit X0 and the first inverter X1 and is then connected to the first AND gate U1 to generate a high-level pulse with a pulse width of delay0.

[0065] When the detection address signal changes downward, the A[0] address signal is inverted by the second inverter X2, and then connected to the second AND gate U2 after passing through the second delay unit X3 and the third inverter X4, generating a high-level pulse with a pulse width of delay0.

[0066] It should be noted that, as Figure 4 As shown, all delay units used in this application can adopt the delay module circuit structure shown in the figure. The delay module is composed of an even number of 2n identical inverters connected end to end. Figure 4 Middle I 2n This represents the 2nth inverter.

[0067] Where A is the input terminal of the delay module and Y is the output terminal of the delay module.

[0068] The inverters described above employ an inverting transistor design, meaning that the channel lengths of the PMOS and NMOS transistors in the inverters are greater than the minimum feature size of the selected fabrication process. This increases the delay of each inverter stage, reduces the number of stages in the inverter chain, and ultimately saves chip layout area.

[0069] In some embodiments of this application, such as Figure 3As shown, the filter clock reconstruction circuit comprises a third AND gate I1, a filter circuit I2, a first flip-flop I3, a first reset unit, a second flip-flop I6, a second reset unit, and a sampling pulse generation unit.

[0070] It should be noted that the labels of the components of the filter clock reconstruction circuit are all Figure 3 in the filter clock reconstruction circuit.

[0071] The first input end of the third AND gate I1 is connected with the output end of the multi-pulse generation and convergence circuit, the output end of the third AND gate I1 is connected with the input end of the filter circuit I2, the output end of the filter circuit I2 is connected with the clock end of the first flip-flop I3, the output end of the first flip-flop I3 is connected with the input end of the first reset unit and the input end of the clock confirmation circuit respectively, the output end of the first reset unit is connected with the reset end of the first flip-flop I3, the second input end of the third AND gate I1 and the clock end of the second flip-flop I6 respectively, the output end of the second flip-flop I6 is connected with the input end of the second reset unit and the input end of the sampling pulse generation unit respectively, the output end of the second reset unit is connected with the reset end of the second flip-flop I6, the output end of the sampling pulse generation unit is connected with the input end of the clock confirmation circuit, and the data end of the first flip-flop I3 and the data end of the second flip-flop I6 are connected with high level.

[0072] The filter circuit I2 is used for filtering the high-level pulse sequence CK0, the first flip-flop I3 and the first reset unit are used for reconstructing the clock of the filtered high-level pulse sequence CK0 to obtain the high-level pulse CK1 and the feedback signal CK1n_delay, and the second flip-flop I6, the second reset unit and the sampling pulse generation unit are used for processing the feedback signal CK1n_delay to obtain three single pulses CK_late1, CK_late2 and CK_late3 of different phases.

[0073] Specifically, the filter circuit I2 comprises a delay unit X0, C2MOS switches (P1, P2, N1 and N2) and a data keeper (inverters X2 and X3).

[0074] The input end of the delay unit X0 is connected with the gate of the P1 PMOS transistor, the gate of the N2 NMOS transistor and the output end of the third AND gate I1 respectively, the output end of the delay unit X0 is connected with the gate of the P2 PMOS transistor and the gate of the N1 NMOS transistor, the source of the P1 PMOS transistor is connected with the power supply, the drain of the P1 PMOS transistor is connected with the source of the P2 PMOS transistor, the drain of the P2 PMOS transistor is connected with the drain of the N1 NMOS transistor, the source of the N1 NMOS transistor is connected with the drain of the N2 NMOS transistor, the source of the N2 NMOS transistor is connected with the ground, the input end of the inverter X2 is connected with the drain of the P2 PMOS transistor, the drain of the N1 NMOS transistor and the output end of the inverter X3 respectively, the output end of the inverter X2 is connected with the input end of the inverter X3.

[0075] The filter circuit I2 is used to filter out the narrow low level pulse in the high level pulse sequence CK0. It should be noted that the filter circuit I2 is a common filter structure, and thus the principle thereof will not be described in detail here.

[0076] For example, the high level pulse sequence CK0 and the feedback signal CK1n_delay are connected with the two input ends of the third AND gate I1 respectively, the output end of the third AND gate I1 passes through the filter circuit I2, the filter circuit I2 filters out the low level pulse in CK0 which is less than the pulse width <delay1, so as to meet the timing requirement of the minimum pulse interval (T min_pulse_width ) of the first flip-flop I3, and thus T min_pulse_width <delay1 < delay0 / 2.

[0077] In some embodiments of the present application, the first reset unit comprises a fourth inverter I4 and a third delay unit I5, the second reset unit comprises a fifth inverter I8 and a fourth delay unit I7, and the sampling pulse generation unit comprises a fifth delay unit I9, a sixth delay unit I10, a seventh delay unit I11 and an eighth delay unit I12.

[0078] The input end of the fourth inverter I4 is connected with the output end of the first flip-flop I3, the output end of the fourth inverter I4 is connected with the input end of the third delay unit I5, and the output end of the third delay unit I5 is connected with the reset end of the first flip-flop I3, the second input end of the third AND gate I1 and the clock end of the second flip-flop I6 respectively.

[0079] For example, the filtered high-level pulse sequence is input to the clock terminal of the first flip-flop I3, the data terminal of the first flip-flop I3 is fixedly connected to a high level ("1"), the output terminal Q of the first flip-flop I3 is connected to the fourth inverter I4 and the third delay unit I5, and the feedback signal CK1n_delay is input to the reset terminal RN of the first flip-flop I3. Since the first flip-flop I3, the fourth inverter I4 and the third delay unit I5 form a self-resetting circuit, the output terminal Q of the first flip-flop I3 remains at a "0" level after the chip is powered on. Thus, the first pulse of the high-level pulse sequence triggers the first flip-flop I3 to generate a high-level pulse CK1 with a pulse width of delay2.

[0080] It should be noted that, according to the address input skew, the pulse interval of the high-level pulse CK1 is greater than 2*delay2, and delay2 can be set to be less than or equal to (delay0+delay1) / 2. Assuming that there are only two addresses (A[0] and A[1]) of the address line (A[0]~A[n]) jump, A[1] is later than A[0] jump, and the skew of the two address jumps of A[0] and A[1] is Δskew, when Δskew is less than delay0+delay1, the adaptive clock CK1 is automatically delayed by delay1 relative to the jump time of the address A[0], and the adaptive clock CK1 is a single high pulse; when Δskew is greater than delay0+delay1, the adaptive clock CK1 generates two high pulses, each high pulse width is fixed as delay2, and the time interval of the rising edges of the two high pulses is Δskew, the first high pulse of the adaptive clock CK2 is automatically delayed by delay1 relative to the jump time of the address A[0], and the second high pulse of the adaptive clock CK2 is automatically delayed by delay1 relative to the jump time of the address A[1].

[0081] The input terminal of the fifth inverter I8 is connected to the output terminal of the second flip-flop I6, the output terminal of the fifth inverter I8 is connected to the input terminal of the fourth delay unit I7, and the output terminal of the fourth delay unit I7 is connected to the reset terminal of the second flip-flop I6.

[0082] The input terminal of the fifth delay unit I9 is connected to the output terminal of the second flip-flop I6, the output terminal of the fifth delay unit I9 is connected to the input terminal of the sixth delay unit I10, the output terminal of the sixth delay unit I10 is connected to the input terminal of the seventh delay unit I11 and the input terminal of the clock confirmation circuit, respectively, the output terminal of the seventh delay unit I11 is connected to the input terminal of the eighth delay unit I12 and the input terminal of the clock confirmation circuit, respectively, and the output terminal of the eighth delay unit I12 is connected to the input terminal of the clock confirmation circuit.

[0083] For example, the feedback signal CK1n_delay is connected to the clock terminal of the second flip-flop I6, the data terminal of the second flip-flop I6 is fixedly connected to a high level ("1"), the output terminal Q of the second flip-flop I6 is connected to the reset terminal RN of the second flip-flop I6 through the fifth inverter I8 and the fourth delay unit I7, and the second flip-flop I6, the fifth inverter I8 and the fourth delay unit I7 also constitute a self-resetting circuit. After the chip is powered on, the output terminal Q of the second flip-flop I6 remains at a "0" level state, and the clock CK_late0 generated by the output terminal Q of the second flip-flop I6 has a pulse width of delay2 and a phase delayed by 2*delay2 relative to CK1. The clock CK_late0 passes through the delay units (I9-I12) to generate three sampling clocks CK_late1, CK_late2 and CK_late3 which are different in phase, and the delay difference of the three sampling clocks is delay3, and delay3<delay2.

[0084] In some embodiments of the present application, as shown in Figure 3 The clock confirmation circuit includes a third flip-flop I2, a fourth flip-flop I3, a fifth flip-flop I4, an NOR gate I5 and a third reset unit.

[0085] It should be noted that the labels of the components of the clock confirmation circuit described above are Figure 3 the labels in the clock confirmation circuit and the address latch selection circuit.

[0086] The clock terminal of the third flip-flop I2 is connected to the output terminal of the sixth delay unit I10, the data terminal of the third flip-flop I2 is connected to the output terminal of the first flip-flop I3, the output terminal of the third flip-flop I2 is connected to the first input terminal of the NOR gate I5, the clock terminal of the fourth flip-flop I3 is connected to the output terminal of the seventh delay unit I11, the data terminal of the fourth flip-flop I3 is connected to the output terminal of the first flip-flop I3, the output terminal of the fourth flip-flop I3 is connected to the second input terminal of the NOR gate I5, the clock terminal of the fifth flip-flop I4 is connected to the output terminal of the eighth delay unit I12, the data terminal of the fifth flip-flop I4 is connected to the output terminal of the first flip-flop I3, the output terminal of the fifth flip-flop I4 is connected to the third input terminal of the NOR gate I5, the output terminal of the NOR gate I5 is connected to the input terminal of the sensitive amplification circuit of the asynchronous memory, the input terminal of the third reset unit and the input terminal of the address latch selection circuit respectively, the output terminal of the third reset unit is connected to the reset terminal of the third flip-flop I2, the reset terminal of the fourth flip-flop I3 and the reset terminal of the fifth flip-flop I4 respectively.

[0087] The third flip-flop I2, the fourth flip-flop I3, the fifth flip-flop I4, or the non gate I5 and the third reset unit are used to process the high level pulse CK1 and three single pulses CK_late1, CK_late2 and CK_late3 of different phases, and when the high level pulse CK1 is a single pulse, a high level pulse clock CK2 is obtained.

[0088] For example, the three single pulses CK_late1, CK_late2 and CK_late3 of different phases are connected to the clock terminals of the reset flip-flops (I2-I4), the data terminals of the flip-flops (I2-I4) are connected to the reconstructed high level pulse CK1, the output terminals Q of the flip-flops (I2-I4) are connected to the three-input non gate I5 to generate the final confirmed clock CK2, and the CK2 is fed back to the set terminals of the flip-flops (I2-I4) after passing through the inverter I7 and the delay unit I6; the flip-flops (I2-I4), the non gate I5, the inverter I7 and the delay unit I6 form a self-reset circuit, and the output terminal CK2 of the non gate I5 keeps at a "0" level state after the chip is powered on; the CK_late1, CK_late2 and CK_late3 sample the high level pulse CK1 respectively, and confirm whether the CK1 is a single pulse within a certain time (2 delay2+delay1+3 delay3), if the CK1 is a single pulse, the three flip-flops (I2-I4) all latch "0" level to generate the final clock CK2 with a pulse width of delay2, and if the CK1 is a multi-pulse within a certain time (2 delay2+delay1+3 delay3), the CK2 keeps at a low level and no pulse clock is generated until the final pulse of the CK1 in the address access period to generate the final clock CK2 with a pulse width of delay2.

[0089] It should be noted that the above method determines whether to generate the final clock CK2 by judging whether the CK1 is a single pulse within a certain time, so that the invalid clock can be reduced to propagate to the next stage.

[0090] In some embodiments of the present application, the third reset unit includes a sixth inverter I7 and a ninth delay unit I6.

[0091] The input terminal of the sixth inverter I7 is connected to the output terminal of the non gate I5, the output terminal of the sixth inverter I7 is connected to the input terminal of the ninth delay unit I6, and the output terminal of the ninth delay unit I6 is connected to the reset terminals of the third flip-flop I2, the fourth flip-flop I3 and the fifth flip-flop I4 respectively.

[0092] In some embodiments of the present application, as Figure 3As shown, the address latch selection circuit includes a sixth flip-flop I1 and a fourth AND gate I8.

[0093] It should be noted that the above address latch selection circuit components are labeled as Figure 3 in the clock confirmation circuit and the address latch selection circuit.

[0094] The clock end of the sixth flip-flop I1 is connected to the output end of the seventh delay unit I11, the data end of the sixth flip-flop I1 is connected to the address bus, the output end of the sixth flip-flop I1 is connected to the first input end of the fourth AND gate I8, the second input end of the fourth AND gate I8 is connected to the output end of the NOR gate I5, and the output end of the fourth AND gate I8 is connected to the input end of the address decoding circuit of the asynchronous memory.

[0095] Among them, the sixth flip-flop I1 is used to latch the address bus, the fourth AND gate I8 is used to process the latched address and the pulse clock CK2, and when the pulse clock CK2 is a high level clock, the latched address is released to the address decoding circuit of the asynchronous memory.

[0096] For example, CK_late2 is connected to the clock end of the flip-flop group I1 as a clock, the address A[n:0] is connected to the data end of the flip-flop group I1, and the flip-flop group I1 latches the address bus A[n:0]; the latched address A[n:0]_latched and CK2 are used as inputs of the AND gate I8, to determine whether the latched address A[n:0]_latched is selected to be released, if the CK2 generates a final high level clock, the latched address A[n:0]_latched is selected to be released to the lower decoding circuit, otherwise A[n:0]_released remains low.

[0097] It should be noted that the above method determines whether to release the latched address by determining whether the CK2 generates a final high level clock, thereby reducing the dynamic flip power consumption of the decoding circuit. The detailed timing of the asynchronous memory generated by the clock generation device is as shown in Figure 5 .

[0098] As shown in Figure 3 , Memory_IP is a small capacity storage module (i.e. the above asynchronous memory), mainly including an address decoding circuit, a sensitive amplification circuit, an input and output control circuit and a storage array, A[n:0]_released is connected to the address bus in Memory_IP as the input of the address decoding module, CK2 is connected to the input of the sensitive amplification module in Memory_IP to control the opening and closing of the sensitive amplification circuit, and the final confirmed clock CK2 controls the address decoding, the sensitive amplifier and the input and output logic to complete the data write and read operation.

[0099] The above is the preferred embodiment of the present application, it should be noted that for those skilled in the art, without departing from the principles described in the present application, can also be made several improvements and refinements, these improvements and refinements should also be considered the scope of protection of the present application.

Claims

1. A clock generating device for an asynchronous memory, characterized by comprising: The application relates to a memory control circuit, which comprises: a multi-pulse generation convergence circuit, an input end of the multi-pulse generation convergence circuit being connected with an address bus output by a storage controller, the storage controller being used for controlling read and write operations of an asynchronous memory; a filter clock reconstruction circuit, an input end of the filter clock reconstruction circuit being connected with an output end of the multi-pulse generation convergence circuit; a clock confirmation circuit, an input end of the clock confirmation circuit being connected with an output end of the filter clock reconstruction circuit, an output end of the clock confirmation circuit being connected with an input end of a sense amplifier circuit of the asynchronous memory; an address latch selection circuit, input ends of the address latch selection circuit being respectively connected with the address bus, an output end of the filter clock reconstruction circuit and an output end of the clock confirmation circuit, an output end of the address latch selection circuit being connected with an input end of an address decoding circuit of the asynchronous memory; the multi-pulse generation convergence circuit is used for processing a plurality of address signals output by the address bus, and a high-level pulse sequence is obtained; the filter clock reconstruction circuit is used for filtering the high-level pulse sequence, and clock reconstruction is performed on the filtered high-level pulse sequence; the clock confirmation circuit is used for confirming whether the reconstructed high-level pulse sequence is a single pulse sequence; and the address latch selection circuit is used for outputting a signal of the address bus to the address decoding circuit when the reconstructed high-level pulse sequence is a single pulse sequence; the filter clock reconstruction circuit comprises a third AND gate, a filter circuit, a first flip-flop, a first reset unit, a second flip-flop, a second reset unit and a sampling pulse generation unit; a first input end of the third AND gate is connected with an output end of the multi-pulse generation convergence circuit, an output end of the third AND gate is connected with an input end of the filter circuit, an output end of the filter circuit is connected with a clock end of the first flip-flop, an output end of the first flip-flop is respectively connected with an input end of the first reset unit and an input end of the clock confirmation circuit, an output end of the first reset unit is respectively connected with a reset end of the first flip-flop, a second input end of the third AND gate and a clock end of the second flip-flop, an output end of the second flip-flop is respectively connected with an input end of the second reset unit and an input end of the sampling pulse generation unit, an output end of the second reset unit is connected with a reset end of the second flip-flop, an output end of the sampling pulse generation unit is connected with an input end of the clock confirmation circuit, and a data end of the first flip-flop and a data end of the second flip-flop are connected with high-level.

2. The clock generating device according to claim 1, wherein the multi-pulse generation convergence circuit comprises: a plurality of up-down edge trigger pulse circuits, input ends of the plurality of up-down edge trigger pulse circuits being connected with a plurality of address lines contained in the address bus, the plurality of up-down edge trigger pulse circuits corresponding to the plurality of address lines in one-to-one correspondence, and each up-down edge trigger pulse circuit being used for processing an address signal output by an address line connected with the up-down edge trigger pulse circuit, and obtaining a high-level pulse. a first OR gate, an input terminal of the first OR gate being connected with an output terminal of each of the plurality of up-down edge triggered pulse circuits, and an output terminal of the first OR gate being connected with an input terminal of the filter clock reconstruction circuit, the first OR gate being configured to converge high level pulses output by the plurality of up-down edge triggered pulse circuits to obtain a high level pulse sequence.

3. The clock generating device according to claim 2, wherein The up-down edge triggered pulse circuit comprises an up edge triggered circuit, a down edge triggered circuit and a second OR gate. The up edge triggered circuit comprises a first delay unit, a first inverter, and a first AND gate, and the down edge triggered circuit comprises a second inverter, a second delay unit, a third inverter, and a second AND gate. An input terminal of the first delay unit is connected with an address line, a first input terminal of the first AND gate, and an input terminal of the second inverter, respectively, an output terminal of the first delay unit is connected with an input terminal of the first inverter, an output terminal of the first inverter is connected with a second input terminal of the first AND gate, an output terminal of the first AND gate is connected with a first input terminal of the second OR gate, and an output terminal of the second OR gate is connected with an input terminal of the first OR gate. An output terminal of the second inverter is connected with an input terminal of the second delay unit and a first input terminal of the second AND gate, respectively, an output terminal of the second delay unit is connected with an input terminal of the third inverter, an output terminal of the third inverter is connected with a second input terminal of the second AND gate, and an output terminal of the second AND gate is connected with a second input terminal of the second OR gate.

4. The clock generating device according to claim 1, wherein The first reset unit comprises a fourth inverter and a third delay unit, an input terminal of the fourth inverter is connected with an output terminal of the first flip-flop, an output terminal of the fourth inverter is connected with an input terminal of the third delay unit, and an output terminal of the third delay unit is connected with a reset terminal of the first flip-flop, a second input terminal of the third AND gate, and a clock terminal of the second flip-flop, respectively. The second reset unit comprises a fifth inverter and a fourth delay unit, an input terminal of the fifth inverter is connected with an output terminal of the second flip-flop, an output terminal of the fifth inverter is connected with an input terminal of the fourth delay unit, and an output terminal of the fourth delay unit is connected with a reset terminal of the second flip-flop.

5. The clock generating device according to claim 4, wherein The sampling pulse generation unit comprises a fifth delay unit, a sixth delay unit, a seventh delay unit, and an eighth delay unit. An input terminal of the fifth delay unit is connected with an output terminal of the second flip-flop, an output terminal of the fifth delay unit is connected with an input terminal of the sixth delay unit, an output terminal of the sixth delay unit is connected with an input terminal of the seventh delay unit and an input terminal of the clock confirmation circuit, respectively, an output terminal of the seventh delay unit is connected with an input terminal of the eighth delay unit and an input terminal of the clock confirmation circuit, respectively, and an output terminal of the eighth delay unit is connected with an input terminal of the clock confirmation circuit.

6. The clock generating device according to claim 5, wherein The clock confirmation circuit comprises a third flip-flop, a fourth flip-flop, a fifth flip-flop, a NOR gate, a third reset unit, the clock end of the third flip-flop is connected with the output end of the sixth delay unit, the data end of the third flip-flop is connected with the output end of the first flip-flop, the output end of the third flip-flop is connected with the first input end of the NOR gate, the clock end of the fourth flip-flop is connected with the output end of the seventh delay unit, the data end of the fourth flip-flop is connected with the output end of the first flip-flop, the output end of the fourth flip-flop is connected with the second input end of the NOR gate, the clock end of the fifth flip-flop is connected with the output end of the eighth delay unit, the data end of the fifth flip-flop is connected with the output end of the first flip-flop, the output end of the fifth flip-flop is connected with the third input end of the NOR gate, the output end of the NOR gate is connected with the input end of the sensitive amplification circuit of the asynchronous memory, the input end of the third reset unit and the input end of the address latching selection circuit respectively, the output end of the third reset unit is connected with the reset end of the third flip-flop, the reset end of the fourth flip-flop and the reset end of the fifth flip-flop respectively.

7. The clock generating device according to claim 6, wherein The third reset unit comprises a sixth inverter and a ninth delay unit, the input end of the sixth inverter is connected with the output end of the NOR gate, the output end of the sixth inverter is connected with the input end of the ninth delay unit, the output end of the ninth delay unit is connected with the reset end of the third flip-flop, the reset end of the fourth flip-flop and the reset end of the fifth flip-flop respectively.

8. The clock generating device according to claim 6, wherein The address latching selection circuit comprises a sixth flip-flop and a fourth AND gate, the clock end of the sixth flip-flop is connected with the output end of the seventh delay unit, the data end of the sixth flip-flop is connected with the address bus, the output end of the sixth flip-flop is connected with the first input end of the fourth AND gate, the second input end of the fourth AND gate is connected with the output end of the NOR gate, the output end of the fourth AND gate is connected with the input end of the address decoding circuit of the asynchronous memory.

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