Refresh address counting circuit and method, refresh address reading and writing circuit, and electronic equipment

Abstract

The present disclosure relates to a refresh address counting circuit, a refresh address counting method, a refresh address read / write circuit, and an electronic device, and relates to the field of integrated circuit technology. The refresh address counting circuit includes: a self-oscillating clock generation module for generating a self-oscillating clock signal according to an array activation signal within each refresh cycle after obtaining a refresh signal; a self-oscillating shielding module for generating a self-oscillating shielding signal under a preset refresh command; and a refresh address counting module for counting refresh addresses according to the self-oscillating clock signal and the self-oscillating shielding signal, and outputting a self-oscillating refresh address. The present disclosure provides a refresh address counting circuit suitable for DDR5.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a refresh address counting circuit, a refresh address counting method, a refresh address reading and writing circuit, and an electronic device. Background Art

[0002] DDR5 SDRAM (Double Data Rate fifth-generation Synchronous Dynamic Random-Access Memory) is a high-bandwidth computer memory.

[0003] DDR5 typically includes two types of refresh commands: full array refresh and single array refresh. With a single array refresh command, only one array is refreshed at a time, while with a full array refresh command, all arrays are refreshed at a time. Therefore, the specific refresh count is counted differently.

[0004] The existing refresh method applicable to one type of refresh command cannot meet the refresh method of DDR5. Therefore, determining a unified counting circuit applicable to DDR5 has become an urgent problem to be solved.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a refresh address counting circuit, a refresh address counting method, a refresh address reading and writing circuit and an electronic device, so as to provide a refresh address counting circuit suitable for DDR5.

[0007] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, a refresh address counting circuit is provided, the circuit comprising:

[0009] A self-oscillating clock generating module is used to generate a self-oscillating clock signal according to the array activation signal in each refresh cycle after obtaining the refresh signal;

[0010] A self-oscillation shielding module, used to generate a self-oscillation shielding signal under a preset refresh command;

[0011] The refresh address counting module is used to count the refresh addresses according to the self-oscillation clock signal and the self-oscillation shielding signal, and output the self-oscillation refresh address.

[0012] In some embodiments of the present disclosure, the preset refresh command includes: a single array refresh command, a full array refresh command, or a self-refresh command.

[0013] In some embodiments of the present disclosure, the self-oscillating shielding signal includes: a shielding sub-signal and a non-shielding sub-signal; wherein,

[0014] The shielding sub-signal is used to shield the self-oscillating clock signal, and the non-shielding sub-signal is used to not shield the self-oscillating clock signal.

[0015] In some embodiments of the present disclosure, the self-oscillation shielding module includes: a full array refresh shielding submodule and a single array refresh shielding submodule; wherein,

[0016] The full array refresh shielding submodule is used to generate the shielding sub-signal when receiving a full array refresh command in the normal refresh mode and when the lowest bit of the current refresh address is an odd number;

[0017] The single array refresh shielding submodule is used to generate the shielding sub-signal before the entire array is refreshed when a single array refresh command is received.

[0018] In some embodiments of the present disclosure, the full array refresh masking submodule is further configured to generate the non-masking sub-signal when a full array refresh command is received in normal refresh mode and when the lowest bit of the current refresh address is an even number.

[0019] In some embodiments of the present disclosure, the full array refresh shielding submodule is further configured to turn off the shielding sub-signal and generate the non-shielding sub-signal when a system reset signal is generated or a periodic refresh command is received within the next refresh cycle.

[0020] In some embodiments of the present disclosure, the full array refresh shield submodule includes: a first NOR gate, a first NAND gate, a first latch and a first NOT gate; wherein,

[0021] The input end of the first NOR gate is connected to the system reset signal and the periodic refresh command, and the output end of the first NOR gate is connected to the reset end of the first latch;

[0022] The input end of the first NAND gate is connected to the normal refresh mode command, the least significant odd signal of the current refresh address and the full array refresh command, and the output end of the first NAND gate is connected to the set end of the first latch;

[0023] The output end of the first latch is connected to the input end of the first NOT gate, and the output end of the first NOT gate outputs the self-oscillation shielding signal.

[0024] In some embodiments of the present disclosure, the single array refresh shielding submodule includes: a refresh array counter, a reset signal generator, and a self-oscillation shielding signal generator; wherein,

[0025] The refresh array counter is used to obtain the refresh status of each array and generate a refresh cycle signal after each array is refreshed once;

[0026] The self-oscillating shielding signal generator is used to generate the shielding sub-signal or the non-shielding sub-signal according to the refresh status of each array;

[0027] The reset signal generator is used to generate a reset signal according to a full array refresh command, a self-refresh command, a system reset signal and the refresh cycle signal; the reset signal is used to reset the refresh array counter to generate the non-masked sub-signal.

[0028] In some embodiments of the present disclosure, the refresh array counter includes: a plurality of XOR gates, a plurality of first AND gates, a plurality of counters and a second AND gate; wherein,

[0029] The XOR gate is connected to a preset array address and a refresh array address, the output end of the XOR gate is connected to a first input end of the first AND gate, the second input end of the first AND gate is connected to a single array refresh command, the output end of the first AND gate is connected to a set end of the counter, and the reset end of the counter is connected to the reset signal;

[0030] An inverter is provided at the output end of the counter, and the inverter outputs the refresh state; one XOR gate corresponds to one first AND gate, one counter and one inverter;

[0031] An input end of the second AND gate is connected to the output ends of the plurality of inverters, and an output end of the second AND gate outputs the refresh cycle signal.

[0032] In some embodiments of the present disclosure, the self-oscillating shielding signal generator includes: a second NOT gate, a second NAND gate, and a second latch; wherein,

[0033] The first input terminal of the second NAND gate is connected to the refresh cycle signal through the second NOT gate, the second input terminal of the second NAND gate is connected to the single array refresh command, and the output terminal of the second NAND gate is connected to the reset terminal of the second latch;

[0034] The set terminal of the second latch is connected to the reset signal, and the output terminal of the second latch outputs the self-oscillation shielding signal.

[0035] In some embodiments of the present disclosure, the reset signal generator includes: a NOR gate; wherein,

[0036] The input end of the NOR gate receives the full array refresh command, the self-refresh command, the system reset signal and the refresh cycle signal, and the output end of the NOR gate outputs the reset signal.

[0037] In some embodiments of the present disclosure, the self-oscillation shielding module further includes: an OR gate; wherein,

[0038] The full array refresh shielding submodule and the single array refresh shielding submodule are arranged in parallel;

[0039] The input end of the OR gate is connected to the output end of the full array refresh shielding submodule and the output end of the single array refresh shielding submodule, and the output end of the OR gate is connected to the refresh address counting module.

[0040] In some embodiments of the present disclosure, the circuit further includes: a third AND gate; wherein,

[0041] The input end of the third AND gate is connected to the output end of the self-oscillation shielding module and the output end of the self-oscillation clock generating module, and the output end of the third AND gate is connected to the input end of the refresh address counting module.

[0042] In some embodiments of the present disclosure, the self-oscillation clock generation module includes: an edge generation unit and a delay unit; wherein,

[0043] The edge generation unit is used to obtain each array activation signal within a refresh period and extract falling edge information of the array activation signal;

[0044] The delay unit is used to adjust the timing of the falling edge information.

[0045] In some embodiments of the present disclosure, the edge generation unit includes: two NAND gates, two NOT gates and a first delay device; wherein,

[0046] The input end of the first NAND gate is connected to the refresh cycle signal and the array activation signal, and the input end of the second NAND gate is connected to the output end of the first NAND gate;

[0047] The input end of the first NOT gate is connected to the output end of the first NAND gate, the output end of the first NOT gate is connected to the input end of the second NAND gate, and the first delay device is provided between the output end of the first NOT gate and the input end of the second NAND gate;

[0048] The output end of the second NAND gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is used to output the falling edge information of the array activation signal.

[0049] In some embodiments of the present disclosure, the delay unit includes: a second delay device; wherein,

[0050] The input end of the second delay device is connected to the output end of the second NOT gate, and the output end of the second delay device outputs the self-oscillating clock signal.

[0051] According to a second aspect of the present disclosure, a refresh address counting method is provided, which is used in the above-mentioned refresh address counting circuit. The method includes:

[0052] After obtaining the refresh signal, the self-oscillation clock generation module generates a self-oscillation clock signal according to the array activation signal in each refresh cycle;

[0053] Generate a self-oscillation shielding signal through the self-oscillation shielding module under a preset refresh command;

[0054] The refresh address counting module counts the refresh address according to the self-oscillation clock signal and the self-oscillation shielding signal, and outputs the self-oscillation refresh address.

[0055] According to a third aspect of the present disclosure, a refresh address read / write circuit is provided, comprising a latch module, a decoding module, a reading module and the above-mentioned refresh address counting circuit;

[0056] The output end of the refresh address counting circuit is connected to the input end of the latch module, the output end of the latch module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the reading module.

[0057] In some embodiments of the present disclosure, the latch module includes a multiplexer and a latch; wherein,

[0058] The input end of the multiplexer is connected to the self-oscillating refresh address and activation address output by the refresh address counting circuit, the control end of the multiplexer is connected to the refresh cycle signal, the output end of the multiplexer is connected to the input end of the latch, and the output end of the latch is connected to the decoding module.

[0059] According to a fourth aspect of the present disclosure, there is provided an electronic device, including:

[0060] multiple arrays;

[0061] An array control unit is provided with the above-mentioned refresh address counting circuit.

[0062] The technical solution provided by the present disclosure may have the following beneficial effects:

[0063] The refresh address counting circuit provided in the exemplary embodiment of the present disclosure generates a self-oscillation shielding signal through a self-oscillation shielding module, and can shield the self-oscillation clock signal generated by the array activation signal according to actual conditions. Finally, the refresh address can be counted according to the shielded self-oscillation clock signal, thereby meeting the different requirements of DDR5 under different refresh commands; in addition, the refresh address counting circuit can also meet the refresh address counting requirements during the refresh mode switching process, and the functional requirements of DDR5 under different refresh modes and refresh instructions can be met through one circuit structure, thereby improving the compatibility of the counting circuit.

[0064] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0066] Figure 1 Schematic diagram showing the refresh address count during the refresh mode transition under the full array refresh command in DDR5 Figure 1 ;

[0067] Figure 2 Schematic diagram showing the refresh address count during the refresh mode transition under the full array refresh command in DDR5 Figure 2 ;

[0068] Figure 3 Schematically shows a refresh address count diagram under a single array refresh command in DDR5;

[0069] Figure 4 Schematically shows a block diagram of a refresh address counting circuit according to an exemplary embodiment of the present disclosure;

[0070] Figure 5 Schematically shows Figure 4 The signal waveform corresponding to the refresh address counting circuit shown is shown in FIG. Figure 1 ;

[0071] Figure 6 Schematically shows Figure 4 The signal waveform corresponding to the refresh address counting circuit shown is shown in FIG. Figure 2 ;

[0072] Figure 7Schematically shows another block diagram of a refresh address counting circuit according to an exemplary embodiment of the present disclosure;

[0073] Figure 8 Schematically shows a circuit diagram of a full array refresh shielding submodule according to an exemplary embodiment of the present disclosure;

[0074] Figure 9 Schematically shows a block diagram of a single array refresh shielding submodule according to an exemplary embodiment of the present disclosure;

[0075] Figure 10 Schematically shows a circuit diagram of a refresh array counter according to an exemplary embodiment of the present disclosure;

[0076] Figure 11 Schematically shows a circuit diagram of a self-oscillating shielding signal generator according to an exemplary embodiment of the present disclosure;

[0077] Figure 12 Schematically shows a circuit diagram of a reset signal generator according to an exemplary embodiment of the present disclosure;

[0078] Figure 13 Schematically shows a structural diagram of a refresh address counting circuit according to an exemplary embodiment of the present disclosure;

[0079] Figure 14 Schematically shows a circuit diagram of a self-oscillating clock generation module according to an exemplary embodiment of the present disclosure;

[0080] Figure 15 A flowchart of a refresh address counting method according to an exemplary embodiment of the present disclosure is schematically shown;

[0081] Figure 16 The figure schematically shows a structural diagram of a refresh address read-write circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the drawings represent like or similar parts, and thus repetitive description thereof will be omitted.

[0083] In addition, the described features, structures or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials or operations are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0084] The blocks shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. Specifically, these functional entities may be implemented in software, or in one or more software-hardened modules, or in different networks and / or processor devices and / or microcontroller devices.

[0085] DDR4 is the abbreviation for the fourth generation of DDR SDRAM, and DDR5 is the abbreviation for the fifth generation of DDR SDRAM. DDR SDRAM is the abbreviation for Double Data Rate SDRAM, which is translated into Chinese as Double Data Rate SDRAM. SDRAM is the abbreviation for Synchronous Dynamic Random Access Memory, which synchronizes with the system clock frequency. Therefore, in combination, DDR4 is the fourth generation of double data rate synchronous dynamic random access memory, and DDR5 is the fifth generation of double data rate synchronous dynamic random access memory. From DDR4 to DDR5, the refresh command has changed from a single refresh command to include the full array refresh command REFab and the single array refresh command REFsb.

[0086] For DDR5, there are usually multiple refresh modes (REF Mode), including normal refresh mode (Normal 1×), normal refresh mode with 2x rate (Normal 2×), and 2x fine-grained refresh mode (FGR 2×).

[0087] Reference Figure 1 For the full array refresh command REFab, in normal refresh mode (Normal 1×), the DRAM generates a self-oscillating refresh address when processing the REFab command, and uses the global refresh counter (Global Refresh Counter) to count the global refreshes. While generating the self-oscillating refresh address, the parity (REF Count) of the current self-oscillating refresh address is monitored. Figure 1 Odd represents odd numbers, and Even represents even numbers.

[0088] like Figure 1 As shown in the figure, when the refresh mode (REF Mode) switches from FGR 2× to Normal 1×, if the current count of REFCount is an even number, then the Global Refresh Counter will continue to count in an even number manner, that is, +2, so that at the end of Normal 1×, the REFCount recorded is still an even number.

[0089] Reference Figure 2 When the refresh mode (REF Mode) switches from FGR 2× to Normal 1×, if the current count of REFCount is odd, then in Normal 1× refresh mode, when the REFab command is received for the first time, REFCount will first be incremented by 1 to obtain an even number, Even, and then counted normally by +2 to ensure that the REFCount recorded is still an even number, Even, when the Normal 1× refresh mode ends.

[0090] It should be noted that Figure 1 and Figure 2 There is a refresh interval between two adjacent REFab commands.

[0091] Reference Figure 3 For single array refresh command REFsb, each REFsb command corresponds to refreshing only one array. Therefore, before all arrays are refreshed, the global refresh counter (GlobalRefresh Counter) will not be accumulated for consecutive REFsb commands. Only after all arrays are refreshed, the global refresh counter will be accumulated. In order to count the number of arrays refreshed each time, Figure 3 An internal bank counter is also added to count each bank refreshed under the REFsb command.

[0092] Because the refresh commands of DDR5 are different from those of DDR4, and in DDR5, there are different counting methods during the refresh mode conversion process, the counting method suitable for DDR4 can no longer meet the requirements of DDR5.

[0093] Based on this, an exemplary embodiment of the present disclosure provides a refresh address counting circuit, which is mainly used in DDR5. Figure 4 The refresh address counting circuit 400 may include: a self-oscillation clock generating module 420, a self-oscillation shielding module 440 and a refresh address counting module 460; wherein,

[0094] The self-oscillating clock generating module 420 can be used to generate a self-oscillating clock signal according to the array activation signal in each refresh cycle after obtaining the refresh signal; Figure 5 and Figure 6 As shown, the self-oscillating clock generation module 420 is primarily used to generate the self-oscillating clock signal OSC_CLK_Pre. Regardless of whether the current refresh instruction is the full array refresh command REFab or the single array refresh command REFsb, as long as the array activation signal BANK_ACT is currently in effect, the self-oscillating clock signal OSC_CLK_Pre is generated. Furthermore, one array activation signal BANK_ACT corresponds to one self-oscillating clock signal OSC_CLK_Pre.

[0095] The self-oscillation masking module 440 can be used to generate a self-oscillation masking signal under a preset refresh command. In the exemplary embodiment of the present disclosure, the preset refresh command can be the single array refresh command REFsb, the full array refresh command REFab, or the self-refresh command SREF. For example, within a refresh cycle, the self-oscillation masking signal OSC_MASK generated by the self-oscillation masking module 440 can be used to mask the self-oscillation clock signal OSC_CLK_Pre.

[0096] In practical applications, under a full array refresh command REFab or a self-refresh command SREF, the entire array is refreshed, which is equivalent to a refresh cycle. Therefore, Figure 5 As shown, under a full array refresh command REFab or a self-refresh command SREF, the self-oscillation masking signal OSC_MASK does not mask the self-oscillation clock signal OSC_CLK_Pre. The self-oscillation masking signal OSC_MASK generated at this time is a non-masking sub-signal, that is, the non-masking sub-signal is used to not mask the self-oscillation clock signal OSC_CLK_Pre under the full array refresh command REFab or the self-refresh command SREF.

[0097] However, for a single array refresh command REFsb, multiple REFsb commands are usually generated in one refresh cycle. Figure 6 As shown, during a refresh cycle, the self-oscillation clock signal OSC_CLK_Pre generated by the array activation signal BANK_ACT is masked by the self-oscillation masking signal OSC_MASK. The masked target self-oscillation clock signal OSC_CLK is generated only once during a refresh cycle. The self-oscillation masking signal OSC_MASK generated at this time is a masking sub-signal, which is used to mask the self-oscillation clock signal OSC_CLK_Pre under a single array refresh command REFsb.

[0098] In the exemplary embodiment of the present disclosure, since the self-oscillating clock signal OSC_CLK_Pre and the self-oscillating mask signal OSC_MASK are both self-generated stable and continuous oscillations without an external excitation signal, the word "self-oscillation" is added to the names of the self-oscillating clock signal OSC_CLK_Pre and the self-oscillating mask signal OSC_MASK to indicate the self-oscillation.

[0099] In the refresh address counting circuit provided by the exemplary embodiments of the present disclosure, the refresh address counting module 460 can be configured to count refresh addresses based on the self-oscillation clock signal OSC_CLK_Pre and the self-oscillation mask signal OSC_MASK, and output the self-oscillation refresh address OSC_RA. In other words, the refresh address counting module 460 counts refresh addresses based on the result of masking the self-oscillation clock signal OSC_CLK_Pre by the self-oscillation mask signal OSC_MASK.

[0100] In the exemplary embodiment of the present disclosure, in addition to the above-mentioned method of counting refresh addresses by masking the self-oscillation clock signal OSC_CLK_Pre through the self-oscillation mask signal OSC_MASK within one refresh cycle, there is also Figure 1 and Figure 2 In the case shown, during the refresh mode conversion process, the self-oscillation clock signal OSC_CLK_Pre is shielded according to the parity state of the current refresh address.

[0101] Specifically, in the exemplary embodiment of the present disclosure, referring to Figure 7 The self-oscillation shielding module 440 includes: a full array refresh shielding submodule 441 and a single array refresh shielding submodule 442; wherein, the full array refresh shielding submodule 441 can be used to generate a shielding sub-signal when receiving the full array refresh command REFab in the normal refresh mode Normal 1×, when the lowest bit REF Count of the current refresh address is an odd number Odd, to shield the self-oscillation clock signal OSC_CLK_Pre so as to perform all array address alignment work in the first cycle, and then generate a new even address, so that the refresh address generated after the refresh is completed is still an even address.

[0102] Once the shielding sub-signal is generated, if you want to turn off the shielding sub-signal, you can use the full array refresh shielding sub-module 441 to turn off the shielding sub-signal and generate a non-shielding sub-signal when the system reset signal RST is generated or the periodic refresh command REF2 in the next refresh cycle is received. After shielding the refresh address in the first refresh cycle, the shielding is released in the second refresh cycle to ensure that the final refresh address is an even address.

[0103] In addition, the full array refresh mask submodule 441 can also be used to generate a non-masked sub-signal when receiving the full array refresh command REFab in the normal refresh mode Normal 1×, when the lowest bit of the current refresh address is an even number Even, to maintain the normal count of the refresh address so that the refresh address generated after the refresh is completed is still an even address.

[0104] Based on the above functional description, the exemplary embodiment of the present disclosure provides a circuit structure of a full array refresh shielding submodule 441, referring to Figure 8 The full-array refresh mask submodule 441 includes a first NOR gate 810, a first NAND gate 820, a first latch 830, and a first NOT gate 840. The inputs of the first NOR gate 810 are connected to the system reset signal RST and the periodic refresh command REF2, so that the first NOR gate 810 outputs a high level when both the system reset signal RST and the periodic refresh command REF2 are low. The output of the first NOR gate 810 is connected to the reset terminal of the first latch 830. The first latch 830 is composed of two NAND gates. When the reset terminal input is high, the output of the first latch 830 is determined by the signal input to the set terminal.

[0105] The input end of the first NAND gate 820 is connected to the normal refresh mode Normal 1× command, the lowest odd signal REF Count of the current refresh address, and the full array refresh command REFab, and the output end of the first NAND gate 820 is connected to the set end of the first latch 830; when the three input signals are all high, that is, when the full array refresh command is received in the normal refresh mode and the lowest bit of the current refresh address is an odd signal, the first NAND gate 820 outputs a low level.

[0106] Under the influence of the low level output by the first NAND gate 820 and the high level output by the first NOR gate 810, the output terminal of the first latch 830 outputs a low level. However, if at least one of the system reset signal RST and the periodic refresh command REF2 is high, the output terminal of the first latch 830 outputs a high level.

[0107] Because the output of the first latch 830 is connected to the input of the first NOT gate 840, the output of the first NOT gate 840 outputs the self-oscillating masking signal OSC_MASK. When the first latch 830 outputs a low level, the self-oscillating masking signal OSC_MASK is high, i.e., it is a masking sub-signal. This is equivalent to the full array refresh masking sub-module 441 outputting a masking sub-signal when a full array refresh command is received in normal refresh mode and the lowest bit of the current refresh address is an odd signal. When the first latch 830 outputs a high level, the self-oscillating masking signal OSC_MASK is low, i.e., it is a non-masking sub-signal. This is equivalent to disabling the masking sub-signal and generating a non-masking sub-signal when the system reset signal RST is generated or the periodic refresh command REF2 is received.

[0108] It should be noted that the above-mentioned full array refresh shielding submodule 441 is set when the high level is valid. For the low level valid situation, it is sufficient to set a corresponding inverter, which will not be repeated here.

[0109] In the exemplary embodiment of the present disclosure, the single array refresh mask submodule 442 is configured to generate a mask subsignal upon receiving a single array refresh command REFsb and before the full array refresh is complete. This allows the self-oscillation mask signal OSC_MASK to mask the self-oscillation clock signal OSC_CLK_Pre even if a single array refresh command is received within a refresh cycle, thereby preventing refresh address counting until the full array refresh is complete.

[0110] Reference Figure 9 In the exemplary embodiment of the present disclosure, the single array refresh shield submodule 442 includes a refresh array counter 910, a reset signal generator 920, and a self-oscillation shield signal generator 930; wherein,

[0111] The refresh array counter 910 can be used to obtain the refresh status of each array and generate a refresh cycle signal after each array is refreshed once; the self-oscillating shielding signal generator 930 can be used to generate a shielded sub-signal or an unshielded sub-signal according to the refresh status of each array; the reset signal generator 920 can be used to generate a reset signal based on the full array refresh command, the self-refresh command, the system reset signal and the refresh cycle signal; the reset signal is used to reset the refresh array counter to generate an unshielded sub-signal.

[0112] The circuit structures of the refresh array counter 910 , the reset signal generator 920 and the self-oscillation shielding signal generator 930 are described below by taking the high level active as an example.

[0113] In the exemplary embodiment of the present disclosure, referring to Figure 10, the refresh array counter 910 includes multiple XOR gates 911, multiple first AND gates 912, multiple counters 913 and second AND gates 914; wherein the XOR gate 911 is connected to the preset array address BA1, BA2, BA3 or BA4 ( Figure 10 ) and the refresh array address REF_BA, the output of the XOR gate 911 is connected to the first input of the first AND gate 912, the second input of the first AND gate 912 is connected to the single array refresh command REF_SB, the output of the first AND gate 912 is connected to the set terminal of the counter 913, and the reset terminal of the counter 913 is connected to the reset signal RSTB, wherein the reset signal RSTB is determined by the reset signal generator 920.

[0114] The output of counter 913 is provided with an inverter 915, which outputs the refresh status. One XOR gate 911 corresponds to one first AND gate 912, one counter 913, and one inverter 915. A set of XOR gates 911, first AND gate 912, counter 913, and inverter 915 outputs the refresh status of an array. For example, when the array is refreshed, a high level is output. When all four arrays are refreshed, all four inverters 915 output a high level, indicating that each array has been refreshed once.

[0115] After determining the refresh status of each array, the refresh status can be switched via the second AND gate 914. Specifically, the input of the second AND gate 914 is connected to the output of multiple inverters 915, and the output of the second AND gate 914 outputs the refresh cycle signal REF_1CYCLE. When the outputs of the multiple inverters 915 are all high, the refresh cycle signal REF_1CYCLE output by the second AND gate 914 is high.

[0116] In the exemplary embodiment of the present disclosure, referring to Figure 11 The self-oscillation masking signal generator 930 includes a second NOT gate 931, a second NAND gate 932 and a second latch 933; wherein, the first input end of the second NAND gate 932 is connected to the refresh cycle signal REF_1CYCLE through the second NOT gate 931, the second input end of the second NAND gate 932 is connected to the single array refresh command REFsb, and the output end of the second NAND gate 932 is connected to the reset end of the second latch 933; the set end of the second latch 933 is connected to the reset signal RSTB, and the output end of the second latch 933 outputs the self-oscillation masking signal OSC_MASK.

[0117] Through the above-mentioned self-oscillation masking signal generator 930, when the refresh cycle signal REF_1CYCLE is at a low level, it means that a refresh cycle has not been completed. At this time, under the action of the single array refresh command REFsb, the output self-oscillation masking signal OSC_MASK is at a high level, that is, the masked sub-signal is output; when the refresh cycle signal REF_1CYCLE is at a high level, it means that a refresh cycle has been completed. At this time, under the action of the single array refresh command REFsb, the output self-oscillation masking signal OSC_MASK is at a low level, that is, the non-masked sub-signal is output.

[0118] In the exemplary embodiment of the present disclosure, referring to Figure 12 Reset signal generator 920 includes a NOR gate 921. The inputs of NOR gate 921 are connected to the full array refresh command REFab, the self-refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE. The output of NOR gate 921 outputs the reset signal RSTB. That is, when any of the full array refresh command REFab, the self-refresh command SREF, the system reset signal RST, and the refresh cycle signal REF_1CYCLE is enabled, reset signal RSTB is triggered. The triggered reset signal RSTB converts the masked sub-signal generated by the self-oscillation masking signal generator 930 into a non-masked sub-signal.

[0119] Based on the above description, it can be seen that the full array refresh shield submodule 441 is used to generate a shield sub-signal under the full array refresh command, and the single array refresh shield submodule 442 is used to generate a shield sub-signal under the single array refresh command. The two belong to modules under different commands. Therefore, in the exemplary embodiment of the present disclosure, the full array refresh shield submodule 441 and the single array refresh shield submodule 442 are arranged in parallel.

[0120] And, refer to Figure 13 Self-oscillation shielding module 440 further includes an OR gate 443. The input of OR gate 443 is connected to the output of full-array refresh shielding submodule 441 and the output of single-array refresh shielding submodule 442. The output of OR gate 443 is connected to refresh address counting module 460. As long as either full-array refresh shielding submodule 441 or single-array refresh shielding submodule 442 outputs a shielding sub-signal, both can affect the counting result of refresh address counting module 460.

[0121] In addition, in the exemplary embodiment of the present invention, the self-oscillation shielding signal OSC_MASK output by the self-oscillation shielding module 440 also needs to be used when shielding the self-oscillation clock signal OSC_CLK_Pre output by the self-oscillation clock generating module 420. Figure 13The third AND gate 480 has an input connected to the output of the self-oscillation shielding module 440 and the output of the self-oscillation clock generating module 420, and an output connected to the input of the refresh address counting module 460. The third AND gate 480 is configured to shield the self-oscillation clock signal OSC_CLK_Pre when the self-oscillation shielding signal OSC_MASK is at a low level, and not shield the self-oscillation clock signal OSC_CLK_Pre when the self-oscillation shielding signal OSC_MASK is at a high level.

[0122] If the high level is enabled, an inverter is also required to invert the self-oscillation shielding signal OSC_MASK output by the self-oscillation shielding module 440, such as Figure 13 shown.

[0123] In practical applications, the refresh address counting module 460 may be composed of a plurality of counting units, each of which is configured to count according to the unshielded self-oscillating clock signal OSC_CLK_Pre output by the third AND gate 480. The counting unit may be composed of a device such as a counter, which is not particularly limited in the exemplary embodiment of the present disclosure.

[0124] In the exemplary embodiment of the present disclosure, referring to Figure 14 The self-oscillation clock generation module 420 may include an edge generation unit 1410 and a delay unit 1420. The edge generation unit 1410 is used to obtain each array activation signal within a refresh cycle and extract the falling edge information of the array activation signal. The delay unit 1420 is used to adjust the timing of the falling edge information. The falling edge information ultimately output by the self-oscillation clock generation module 420 is the self-oscillation clock signal OSC_CLK_Pre.

[0125] In an exemplary embodiment of the present disclosure, edge generation unit 1410 may include: two NAND gates, two NOT gates, and a first delay device. The first NAND gate has its input connected to a refresh cycle signal and an array activation signal, and the second NAND gate has its input connected to the output of the first NAND gate. The first NOT gate has its input connected to the output of the first NAND gate, and the output of the first NOT gate is connected to the input of the second NAND gate. A first delay device is further provided between the output of the first NOT gate and the input of the second NAND gate. The output of the second NAND gate is connected to the input of the second NOT gate, and the output of the second NOT gate is used to output falling edge information of the array activation signal. Delay unit 1420 may include: a second delay device; the input of the second delay device is connected to the output of the second NOT gate, and the output of the second delay device outputs the self-oscillating clock signal OSC_CLK_Pre. The structures of edge generation unit 1410 and delay unit 1420 described herein are merely examples and may be configured in different ways according to actual needs. This exemplary embodiment of the present disclosure is not particularly limited in this regard.

[0126] To sum up, the refresh address counting circuit provided in the exemplary embodiment of the present disclosure generates a self-oscillation shielding signal through a self-oscillation shielding module, and can shield the self-oscillation clock signal generated by the array activation signal according to actual conditions, and finally can count the refresh address according to the shielded self-oscillation clock signal, thereby meeting the different requirements of DDR5 under different refresh commands; in addition, the refresh address counting circuit can also meet the refresh address counting requirements during the refresh mode switching process, and can meet the functional requirements of DDR5 under different refresh modes and refresh instructions through one circuit structure, thereby improving the compatibility of the counting circuit.

[0127] The exemplary embodiment of the present disclosure also provides a refresh address counting method. Figure 15 The refresh address counting method may specifically include the following steps:

[0128] Step S152: After obtaining the refresh signal, the self-oscillation clock generation module generates a self-oscillation clock signal according to the array activation signal in each refresh cycle;

[0129] Step S154: generating a self-oscillation shielding signal through the self-oscillation shielding module under a preset refresh command;

[0130] Step S156 : Counting the refresh address according to the self-oscillation clock signal and the self-oscillation shielding signal by the refresh address counting module, and outputting the self-oscillation refresh address.

[0131] The specific details of each step in the above refresh address counting method have been described in detail in the corresponding refresh address counting circuit, so they will not be repeated here.

[0132] The exemplary embodiment of the present disclosure also provides a refresh address read-write circuit, referring to Figure 16 The refresh address read / write circuit includes a latch module 1610, a decoding module 1620, a reading module 1630, and the aforementioned refresh address counting circuit 400. The output of the refresh address counting circuit 400 is connected to the input of the latch module 1610, the output of the latch module 1610 is connected to the input of the decoding module 1620, and the output of the decoding module 1620 is connected to the reading module 1630. The self-oscillating refresh address output by the refresh address counting circuit can be latched by the latch module 1610, decoded by the decoding module 1620, and read by the reading module 1630. The decoding module 1620 and the reading module 1630 can refer to existing conventional circuit structures, and the specific structures of the decoding module 1620 and the reading module 1630 are not particularly limited herein.

[0133] In an exemplary embodiment of the present disclosure, latch module 1610 includes a multiplexer 1611 and a latch 1612. The input of multiplexer 1611 is connected to the self-oscillating refresh address OSC_RA and activation address ACT_RA output by refresh address counting circuit 400. The control terminal of multiplexer 1611 is connected to the refresh cycle signal REF_1CYCLE. The output of multiplexer 1611 is connected to the input of latch 1612, and the output of latch 1612 is connected to decoding module 1620. Under the control of refresh cycle signal REF_1CYCLE, multiplexer 1611 is configured to select and output the activation address ACT_RA before a refresh cycle is completed, and to select and output the self-oscillating refresh address OSC_RA after a refresh cycle is completed. The address selected and output by multiplexer 1611 is latched by latch 1612.

[0134] In addition, the specific structure of the refresh address counting circuit 400 has been described in detail in the above embodiment, and thus will not be repeated here.

[0135] The exemplary embodiments of the present disclosure further provide an electronic device that may include: a plurality of arrays and an array control unit, wherein the array control unit is provided with the aforementioned refresh address counting circuit. The specific structural details of the refresh address counting circuit have been described in detail in the aforementioned embodiments and will not be repeated here.

[0136] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer commands. When the computer program command is loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer command can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that can be integrated with one or more media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a tape), an optical medium (for example, a DVD), or a semiconductor medium (for example, a solid state disk (SSD)). In the embodiment of the present disclosure, the computer may include the device described above.

[0137] Although the present disclosure is described herein in conjunction with various embodiments, in the process of implementing the disclosure for which protection is sought, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude multiple components. A single processor or other unit may implement several functions listed in the claims. The fact that certain measures are recorded in mutually different dependent claims does not mean that these measures cannot be combined to produce good results.

[0138] Although the present disclosure has been described with reference to specific features and embodiments thereof, it will be apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present disclosure. Accordingly, this specification and the drawings are merely illustrative of the present disclosure as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present disclosure. Obviously, those skilled in the art may make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is intended to encompass such modifications and variations if they fall within the scope of the claims of the present disclosure and their equivalents.

Claims

1. A refresh address counting circuit, characterized in that: The circuit comprises: A self-oscillating clock generating module is used to generate a self-oscillating clock signal according to the array activation signal in each refresh cycle after obtaining the refresh signal; The self-oscillation shielding module is configured to generate a self-oscillation shielding signal under a preset refresh command; the preset refresh command includes a single array refresh command, a full array refresh command, or a self-refresh command; the self-oscillation shielding signal includes a shielding sub-signal and an unshielding sub-signal; wherein the shielding sub-signal is used to shield the self-oscillation clock signal, and the unshielding sub-signal is used to unshield the self-oscillation clock signal; the self-oscillation shielding module includes a full array refresh shielding sub-module and a single array refresh shielding sub-module; wherein the full array refresh shielding sub-module is configured to generate the shielding sub-signal when receiving a full array refresh command in a normal refresh mode and when the lowest bit of the current refresh address is an odd number; and the single array refresh shielding sub-module is configured to generate the shielding sub-signal when receiving a single array refresh command and before the full array is refreshed. The refresh address counting module is used to count the refresh addresses according to the self-oscillation clock signal and the self-oscillation shielding signal, and output the self-oscillation refresh address.

2. The refresh address counting circuit according to claim 1, wherein: The full array refresh mask submodule is further configured to generate the non-masking sub-signal when a full array refresh command is received in a normal refresh mode and when the lowest bit of the current refresh address is an even number.

3. The refresh address counting circuit according to claim 1, wherein: The full array refresh shielding submodule is further configured to turn off the shielding sub-signal and generate the non-shielding sub-signal when a system reset signal is generated or a periodic refresh command in the next refresh cycle is received.

4. The refresh address counting circuit according to claim 3, wherein: The full array refresh shield submodule includes: a first NOR gate, a first NAND gate, a first latch and a first NOT gate; wherein, The input end of the first NOR gate is connected to the system reset signal and the periodic refresh command, and the output end of the first NOR gate is connected to the reset end of the first latch; The input end of the first NAND gate is connected to the normal refresh mode command, the least significant odd signal of the current refresh address and the full array refresh command, and the output end of the first NAND gate is connected to the set end of the first latch; The output end of the first latch is connected to the input end of the first NOT gate, and the output end of the first NOT gate outputs the self-oscillation shielding signal.

5. The refresh address counting circuit according to claim 1, wherein: The single array refresh shield submodule includes: a refresh array counter, a reset signal generator and a self-oscillation shield signal generator; wherein, The refresh array counter is used to obtain the refresh status of each array and generate a refresh cycle signal after each array is refreshed once; The self-oscillating shielding signal generator is used to generate the shielding sub-signal or the non-shielding sub-signal according to the refresh status of each array; The reset signal generator is used to generate a reset signal according to a full array refresh command, a self-refresh command, a system reset signal and the refresh cycle signal; the reset signal is used to reset the refresh array counter to generate the non-masked sub-signal.

6. The refresh address counting circuit according to claim 5, wherein: The refresh array counter includes: a plurality of XOR gates, a plurality of first AND gates, a plurality of counters and a second AND gate; wherein, The XOR gate is connected to a preset array address and a refresh array address, the output end of the XOR gate is connected to a first input end of the first AND gate, the second input end of the first AND gate is connected to a single array refresh command, the output end of the first AND gate is connected to a set end of the counter, and the reset end of the counter is connected to the reset signal; An inverter is provided at the output end of the counter, and the inverter outputs the refresh state; one XOR gate corresponds to one first AND gate, one counter and one inverter; An input end of the second AND gate is connected to the output ends of the plurality of inverters, and an output end of the second AND gate outputs the refresh cycle signal.

7. The refresh address counting circuit according to claim 5, wherein: The self-oscillation shielding signal generator includes: a second NOT gate, a second NAND gate and a second latch; wherein, The first input terminal of the second NAND gate is connected to the refresh cycle signal through the second NOT gate, the second input terminal of the second NAND gate is connected to the single array refresh command, and the output terminal of the second NAND gate is connected to the reset terminal of the second latch; The set terminal of the second latch is connected to the reset signal, and the output terminal of the second latch outputs the self-oscillation shielding signal.

8. The refresh address counting circuit according to claim 5, wherein: The reset signal generator includes: a NOR gate; wherein, The input end of the NOR gate receives the full array refresh command, the self-refresh command, the system reset signal and the refresh cycle signal, and the output end of the NOR gate outputs the reset signal.

9. The refresh address counting circuit according to claim 1, wherein: The self-oscillation shielding module further includes: an OR gate; wherein, The full array refresh shielding submodule and the single array refresh shielding submodule are arranged in parallel; The input end of the OR gate is connected to the output end of the full array refresh shielding submodule and the output end of the single array refresh shielding submodule, and the output end of the OR gate is connected to the refresh address counting module.

10. The refresh address counting circuit according to claim 1, wherein: The circuit further includes: a third AND gate; wherein, The input end of the third AND gate is connected to the output end of the self-oscillation shielding module and the output end of the self-oscillation clock generating module, and the output end of the third AND gate is connected to the input end of the refresh address counting module.

11. The refresh address counting circuit according to any one of claims 1 to 10, characterized in that: The self-oscillation clock generation module includes: an edge generation unit and a delay unit; wherein, The edge generating unit is used to obtain each array activation signal within a refresh period and extract falling edge information of the array activation signal; The delay unit is used to adjust the timing of the falling edge information.

12. The refresh address counting circuit according to claim 11, wherein: The edge generation unit includes: two NAND gates, two NOT gates and a first delay device; wherein, The input end of the first NAND gate is connected to the refresh cycle signal and the array activation signal, and the input end of the second NAND gate is connected to the output end of the first NAND gate; The input end of the first NOT gate is connected to the output end of the first NAND gate, the output end of the first NOT gate is connected to the input end of the second NAND gate, and the first delay device is provided between the output end of the first NOT gate and the input end of the second NAND gate; The output end of the second NAND gate is connected to the input end of the second NOT gate, and the output end of the second NOT gate is used to output the falling edge information of the array activation signal.

13. The refresh address counting circuit according to claim 12, wherein: The delay unit includes: a second delay device; wherein, The input end of the second delay device is connected to the output end of the second NOT gate, and the output end of the second delay device outputs the self-oscillating clock signal.

14. A refresh address counting method, used in the refresh address counting circuit according to any one of claims 1 to 13, characterized in that: The method comprises: After obtaining the refresh signal, the self-oscillation clock generation module generates a self-oscillation clock signal according to the array activation signal in each refresh cycle; Generate a self-oscillation shielding signal through the self-oscillation shielding module under a preset refresh command; The refresh address counting module counts the refresh address according to the self-oscillation clock signal and the self-oscillation shielding signal, and outputs the self-oscillation refresh address.

15. A refresh address read-write circuit, characterized in that: comprising a latch module, a decoding module, a reading module and a refresh address counting circuit according to any one of claims 1 to 13; The output end of the refresh address counting circuit is connected to the input end of the latch module, the output end of the latch module is connected to the input end of the decoding module, and the output end of the decoding module is connected to the reading module.

16. The refresh address read / write circuit according to claim 15, wherein: The latch module includes a multiplexer and a latch; wherein, The input end of the multiplexer is connected to the self-oscillating refresh address and activation address output by the refresh address counting circuit, the control end of the multiplexer is connected to the refresh cycle signal, the output end of the multiplexer is connected to the input end of the latch, and the output end of the latch is connected to the decoding module.

17. An electronic device, characterized in that: include: multiple arrays; An array control unit, wherein the array control unit is provided with a refresh address counting circuit according to any one of claims 1 to 13.

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