Sense Amplifying Structure and Memory Architecture

Abstract

This application relates to the field of semiconductor circuit design, and relates to a sense amplifier structure and a memory architecture, including: a first PMOS transistor, whose gate is connected to a second complementary read bit line, and whose source is connected to a first signal terminal; a first NMOS transistor, whose gate is connected to an initial bit line; the drains of the first PMOS transistor and the first NMOS transistor are connected to a first complementary read bit line; a second PMOS transistor, whose gate is connected to the second complementary read bit line; a second NMOS transistor, whose gate is connected to an initial complementary bit line, and whose source is connected to a second signal terminal; the drains of the second PMOS transistor and the second NMOS transistor are connected to the first complementary read bit line; an offset cancellation module, connected to the initial bit line and the first complementary read bit line, and connected to the initial complementary bit line and the first read bit line; a control module, connected to the second read bit line and the second complementary read bit line, and configured to provide a bias voltage to the first PMOS transistor and the second PMOS transistor according to a control signal, so as to stably cancel the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line.

Description

Technical Field

[0001] This application relates to the field of semiconductor circuit design, and relates to a sense amplifier structure and a memory architecture. Background Art

[0002] Dynamic Random Access Memory (DRAM) writes data through the charge in the cell capacitor; the cell capacitor is connected to the bit line and the complementary bit line. In DRAM, when a read operation or a refresh operation is performed, the sense amplifier reads and amplifies the voltage difference between the bit line and the complementary bit line.

[0003] Semiconductor devices constituting the sense amplifier may have different device characteristics (e.g., threshold voltage) due to factors such as process variations and temperature. Different device characteristics will cause offset noise in the sense amplifier, and the offset noise will reduce the effective read margin of the sense amplifier and reduce the performance of DRAM.

[0004] The applicant found that during the current process of eliminating the offset noise of DRAM, the bit line and the complementary read bit line are electrically connected, and the complementary bit line and the read bit line are electrically connected. The voltage difference between the bit line and the complementary bit line is used to cancel the offset noise. However, since the gates of the PMOS transistors in the sense amplifier circuit are respectively connected to the read bit line and the complementary read bit line, it is easy to cause voltage fluctuations in the read bit line and the complementary read bit line, thereby affecting the voltages of the bit line and the complementary bit line, reducing the accuracy of DRAM reading, and reducing the performance of DRAM.

[0005] Therefore, how to stably eliminate the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line is an urgent problem to be solved at present. Summary of the Invention

[0006] Embodiments of this application relate to a sense amplifier structure and a memory architecture, and provide a sense amplifier circuit to stably eliminate the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line.

[0007] An embodiment of the present application provides a sense amplification structure disposed between adjacent memory arrays, including: a first PMOS transistor, whose gate is connected to a second complementary read bit line and whose source is connected to a first signal terminal; a first NMOS transistor, whose gate is connected to an initial bit line and whose source is connected to a second signal terminal; the drains of the first PMOS transistor and the first NMOS transistor are connected to a first complementary read bit line, wherein the first signal terminal is used to receive a first level signal and the second signal terminal is used to receive a second level signal; a second PMOS transistor, whose gate is connected to the second complementary read bit line and whose source is connected to the first signal terminal; a second NMOS transistor, whose gate is connected to an initial complementary bit line and whose source is connected to the second signal terminal; the drains of the second PMOS transistor and the second NMOS transistor are connected to the first complementary read bit line, wherein the initial bit line is connected to the memory cells of a memory array in adjacent memory arrays, and the initial complementary bit line is connected to the memory cells of another memory array in adjacent memory arrays; an offset cancellation module, partially connected between the initial bit line and the first complementary read bit line and partially connected between the initial complementary bit line and the first read bit line, configured to electrically connect the initial bit line and the first complementary read bit line and electrically connect the initial complementary bit line and the first read bit line according to an offset cancellation signal; a control module, connected to the second read bit line and the second complementary read bit line, configured to provide a bias voltage to the first PMOS transistor and the second PMOS transistor according to a control signal.

[0008] An embodiment of the present application further provides a memory architecture, including: a plurality of memory arrays arranged in the extending direction of the initial bit line and the extending direction of the word line, the extending direction of the initial bit line and the extending direction of the word line being perpendicular to each other; the above-mentioned sense amplification structure, disposed between adjacent memory arrays in the extending direction of the initial bit line; wherein, the sense amplification structure is connected to the memory cells of a memory array in adjacent memory arrays through the initial bit line and connected to the memory cells of another memory array in adjacent memory arrays through the initial complementary bit line; a control module, disposed between adjacent memory arrays in the extending direction of the word line, the control module being configured to provide a data read signal, a control signal and a bias voltage to the sense amplification structure.

[0009] When the control module is turned on based on the control signal, a bias voltage is provided to the gates of the first PMOS transistor and the second PMOS transistor. The first PMOS transistor is turned on based on the bias voltage, and the first signal terminal is electrically connected to the first complementary sense bit line, and the first level signal is transmitted to the first complementary sense bit line. The second PMOS transistor is turned on based on the bias voltage, and the first signal terminal is electrically connected to the first sense bit line, and the first level signal is transmitted to the first sense bit line, thereby achieving the offset cancellation of the PMOS transistor. After the offset cancellation module is turned on based on the offset cancellation signal, the initial bit line is electrically connected to the first complementary sense bit line and shares the voltage, the initial complementary bit line is electrically connected to the first sense bit line and shares the voltage, the voltage of the initial bit line is used as the gate voltage of the first NMOS transistor to turn on the first NMOS transistor, the second signal terminal is electrically connected to the first complementary sense bit line, and the second level signal is transmitted to the first complementary sense bit line. The voltage of the initial complementary bit line is used as the gate voltage of the second NMOS transistor to turn on the second NMOS transistor, the second signal terminal is electrically connected to the first sense bit line, and the second level signal is transmitted to the first sense bit line, thereby achieving the offset cancellation of the NMOS transistor. Since the first PMOS transistor and the second PMOS transistor are turned on based on a stable bias voltage, that is, the voltages of the first sense bit line and the first complementary sense bit line are kept stable, the voltages of the initial bit line and the initial complementary bit line are further stabilized to avoid voltage fluctuations on the bit line and the complementary bit line, and the offset noise in the sense amplifier circuit is stably eliminated. Description of the Drawings

[0010] Figure 1 It is a schematic circuit diagram of a sense amplifier structure provided by an embodiment of the present application;

[0011] Figure 2 It is a schematic structural layout diagram of a memory architecture provided by another embodiment of the present application;

[0012] Figure 3 It is a specific structural schematic diagram of a memory architecture provided by another embodiment of the present application. Detailed Embodiments

[0013] Currently, during the process of eliminating the offset noise of DRAM, the bit line is electrically connected to the complementary sense bit line, and the complementary bit line is electrically connected to the sense bit line. The offset noise is cancelled by the voltage difference between the bit line and the complementary bit line. However, since the gates of the PMOS transistors in the sense amplifier circuit are respectively connected to the sense bit line and the complementary sense bit line, it is easy to cause voltage fluctuations in the sense bit line and the complementary sense bit line, thereby affecting the voltages of the bit line and the complementary bit line, reducing the accuracy of DRAM reading, and reducing the performance of DRAM. Therefore, how to stably eliminate the offset noise in the sense amplifier circuit while avoiding voltage fluctuations on the bit line and the complementary bit line is an urgent problem to be solved at present.

[0014] An embodiment of the present application provides a sense amplifier structure disposed between adjacent memory arrays, including: a first PMOS transistor, whose gate is connected to a second complementary read bit line, and whose source is connected to a first signal terminal; a first NMOS transistor, whose gate is connected to an initial bit line, and whose source is connected to a second signal terminal; the drains of the first PMOS transistor and the first NMOS transistor are connected to a first complementary read bit line, wherein the first signal terminal is used to receive a first level signal, and the second signal terminal is used to receive a second level signal; a second PMOS transistor, whose gate is connected to the second complementary read bit line, and whose source is connected to the first signal terminal; a second NMOS transistor, whose gate is connected to an initial complementary bit line, and whose source is connected to the second signal terminal; the drains of the second PMOS transistor and the second NMOS transistor are connected to the first complementary read bit line, wherein the initial bit line is connected to a memory cell of one memory array in the adjacent memory arrays, and the initial complementary bit line is connected to a memory cell of another memory array in the adjacent memory arrays; an offset cancellation module, partially connected between the initial bit line and the first complementary read bit line, and partially connected between the initial complementary bit line and the first read bit line, for electrically connecting the initial bit line and the first complementary read bit line, and electrically connecting the initial complementary bit line and the first read bit line according to an offset cancellation signal; a control module, connected to the second read bit line and the second complementary read bit line, for providing a bias voltage to the first PMOS transistor and the second PMOS transistor according to a control signal.

[0015] Those of ordinary skill in the art can understand that in various embodiments of the present application, many technical details are proposed to help readers better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented.

[0016] Figure 1 FIG. is a schematic circuit diagram of the sense amplifier structure provided in this embodiment. The sense amplifier structure provided in each embodiment of the present application will be further described in detail below with reference to the accompanying drawings, specifically as follows:

[0017] Refer to Figure 1 , the sense amplifier structure is disposed between adjacent memory arrays 400 and includes:

[0018] The first PMOS transistor <p1>, the gate is connected to the second read bit line ISABL, and the source is connected to the first signal terminal; wherein, the first signal terminal is used to receive a first level signal (Positive Cell Storing Signal, PCS).

[0019] The first NMOS transistor <n1>, the gate is connected to the initial bit line BL, and the source is connected to the second signal terminal, where the second signal terminal is used to receive the second level signal (Negative Cell Storing Signal, NCS).

[0020] The first PMOS transistor <p1>The drain of and the first NMOS transistor <n1>Its drain is connected to the first complementary read bit line SABLB.

[0021] In this embodiment, the voltage of the first level signal PCS is greater than the voltage of the second level signal NCS, that is, the first level signal PCS is a high level corresponding to logic "1", and the second level signal NCS is a low level corresponding to logic "0".

[0022] The second PMOS transistor <p2>, the gate is connected to the second complementary read bit line ISABLB, and the source is connected to the first signal terminal.

[0023] The second NMOS transistor <n2>, the gate is connected to the initial complementary bit line BLB, and the source is connected to the second signal terminal.

[0024] The second PMOS transistor <p2>The drain of the [device] and the second NMOS transistor <n2>The drain is connected to the first read bit line SABL.

[0025] For the initial bit line BL and the initial complementary bit line BLB, the initial bit line BL is connected to the memory cells of a memory array 400 in the adjacent memory array 400, and the initial complementary bit line is connected to the memory cells of another memory array 400 in the adjacent memory array 400.

[0026] In this embodiment, referring to Figure 1 , the initial bit line BL is connected to the first memory cell through the first switching transistor <01>, and the initial complementary bit line BLB is connected to the second memory cell through the second switching transistor <02>.

[0027] For the first switching transistor <01> and the second switching transistor <02>, the gate of the first switching transistor <01> is connected to the word line WL, the source is connected to the initial bit line BL, and the drain is connected to the first memory cell. The gate of the second switching transistor <02> is connected to the word line WL, the source is connected to the initial complementary BLB, and the drain is connected to the second memory cell.

[0028] Among them, the word line WL is used to conduct based on the row selection signal. When the word line WL conducts, the switching transistor connected to the word line WL conducts, sharing the charge of the memory cell to the initial bit line BL or the initial complementary bit line BLB. The initial bit line BL or the initial complementary bit line BLB conducts based on the column selection signal. When the initial bit line BL or the initial complementary bit line BLB conducts, the memory reads out the data.

[0029] The offset cancellation module is partially connected between the initial bit line BL and the first complementary read bit line SABLB, and partially connected between the initial complementary bit line BLB and the first read bit line SABL, and is used to electrically connect the initial bit line BL to the first complementary read bit line SABLB and electrically connect the initial complementary bit line BLB to the first read bit line SABL according to the offset cancellation signal (OffsetCancelling Signal, OC).

[0030] The control module 100 is connected to the second read bit line ISABL and the second read bit line ISABLB, and is used to supply a control signal to the first PMOS transistor <p1>and the second PMOS transistor <p2>Provide a bias voltage V BIAS 。

[0031] When the control module 100 is turned on based on the control signal, it supplies power to the first PMOS transistor <p1>of the gate and the second PMOS transistor <p2>The gate of provides a bias voltage V BIAS , the first PMOS transistor <p1>Based on the bias voltage V BIAS conducts, the first signal terminal is electrically connected to the first complementary read bit line SABLB, and the first level signal PCS is transmitted to the first complementary read bit line SABLB, and the second PMOS transistor <p2>Based on the offset voltage V BIAS conducts, the first signal terminal is electrically connected to the first read bit line SABL, and the first level signal PCS is transmitted to the first read bit line SABL, thereby realizing the offset cancellation of the PMOS transistor; when the offset cancellation module conducts based on the offset cancellation signal OC, the initial bit line BL is electrically connected to the first complementary read bit line SABLB and shares the voltage, the initial complementary bit line BLB is electrically connected to the first read bit line SABL and shares the voltage, and the voltage of the initial bit line BL is used as the first NMOS transistor <n1>to turn on the first NMOS transistor by applying a gate voltage <n1>, the second signal terminal is electrically connected to the first complementary read bit line SABLB, and the second level signal NCS is transmitted to the first complementary read bit line SABLB. The voltage of the initial complementary bit line BL is used as the second NMOS transistor <n2>The gate voltage of to turn on the second NMOS transistor <n2>, the second signal terminal is electrically connected to the first read bit line SABL, and the second-level signal NCS is transmitted to the first read bit line SABL, thereby realizing the offset cancellation of the NMOS transistor; since the first PMOS transistor <p1>and the second PMOS transistor <p2>Based on the stable bias voltage V BIAS conducts, that is, keeps the voltages of the first sense bit line SABL and the first complementary sense bit line SABLB stable, further stabilizes the voltages of the initial bit line BL and the initial complementary bit line BLB, so as to avoid voltage fluctuations on the bit line and the complementary bit line, and stably eliminates the offset noise in the sense amplifier circuit.

[0032] For the control module, in one example, the control module includes: a first control unit 101, one end of which is connected to the second sense bit line ISABL, and the other end is used to receive the bias voltage V BIAS and is used to, according to the control signal, supply power to the first PMOS transistor <p1>Provide a bias voltage V BIAS The second control unit 102 has one end connected to the second complementary read bit line ISABLB and the other end for receiving the bias voltage V BIAS and is configured to, according to a control signal, supply power to the second PMOS transistor <p2>Provide a bias voltage V BIAS .

[0033] In one example, the control signal is the same as the offset cancellation signal OC, that is, the control module 100 is turned on according to the offset cancellation signal OC. By setting the control signal to be the same as the offset cancellation signal OC, the control module 100 and the offset cancellation module are synchronized, so as to achieve offset cancellation of the sense amplifier circuit, as shown in the circuit of Figure 1 .

[0034] In one example, the control signal includes a first control signal and a second control signal. Among them, the first control unit 101 is turned on based on the first control signal, and the second control unit 102 is turned on based on the second control signal. That is, the first control unit 101 supplies power to the first PMOS transistor through the first control signal <p1>Provide a bias voltage V BIAS ; The second control unit 102 supplies a second control signal to the second PMOS transistor <p2>Provide a bias voltage V BIAS ; By separately controlling the first control unit and the second control unit through different control signals, the precise control of the control module 100 is further realized.

[0035] Specifically, the first control unit 101 includes a first control MOS transistor <11>. The source of the first control MOS transistor <11> is connected to the second read bit line ISABL, the gate is used to receive the first control signal, and the drain is used to receive the bias voltage V BIAS ; The second control unit 102 includes a second control MOS transistor <12>. The source of the second control MOS transistor <12> is connected to the second complementary read bit line ISABLB, the gate is used to receive the second control signal, and the drain is used to receive the bias voltage V BIAS .

[0036] In one example, the control module can also use the same control unit to simultaneously supply power to the first PMOS transistor <p1>and the second PMOS transistor <p2>Provide a bias voltage V BIAS The bias voltage V is provided by the same control unit BIAS to reduce the layout area of the sense amplifier circuit structure, which is beneficial to improving the integration degree of the memory.

[0037] For the offset cancellation module, refer to Figure 1 The offset cancellation module includes: a first offset cancellation MOS transistor <31> with its source connected to the initial bit line BL, its drain connected to the first complementary read bit line SABLB, and its gate for receiving the offset cancellation signal OC, and is used to electrically connect the initial bit line BL and the first complementary read bit line SABLB according to the offset cancellation signal OC; a second offset cancellation MOS transistor <32> with its source connected to the initial complementary bit line BLB, its drain connected to the first read bit line SABL, and its gate for receiving the offset cancellation signal OC, and is used to electrically connect the initial complementary bit line BLB and the first read bit line SABL according to the offset cancellation signal OC.

[0038] In this embodiment, the sense amplifier structure further includes: a first isolation unit 201 with one end connected to the first read bit line SABL and the other end connected to the second read bit line ISABL, and is used to electrically connect the first read bit line SABL and the second read bit line ISABL according to the first isolation signal (Isolation Signal 1, ISO1); a second isolation unit 202 with one end connected to the first complementary read bit line SABLB and the other end connected to the second complementary read bit line ISABLB, and is used to electrically connect the first complementary read bit line SABLB and the second complementary read bit line ISABLB according to the first isolation signal (Isolation Signal1, ISO1).

[0039] Specifically, the first isolation unit 201 includes a first isolation MOS transistor <21> with its source connected to the first read bit line SABL, its drain connected to the second read bit line ISABL, and its gate for receiving the first isolation signal ISO1; the second isolation unit 202 includes a second isolation MOS transistor <22> with its source connected to the first complementary read bit line SABLB, its drain connected to the second complementary read bit line ISABLB, and its gate for receiving the first isolation signal ISO1.

[0040] During the pre-charge stage, the sense amplifier circuit provides the first isolation signal ISO1 to pre-charge the second read bit line ISABL and the second complementary read bit line ISABLB. During the sense amplifier stage, the first isolation signal ISO1 is provided to enable the first PMOS transistor <p1>The gate of which is connected to the first read bit line SABL, the first PMOS transistor <p1>Its gate is connected to the first complementary read bit line SABLB.

[0041] At this time, for the first PMOS transistor <p1>and the first NMOS transistor <n1>, due to the first PMOS transistor <p1>Gate and the first NMOS transistor <n1>The connection relationships of the gates are the same, that is, based on different levels of the second read bit line ISABL, the first PMOS transistor <p1>or the first NMOS transistor <n1>When conducting, the first PMOS transistor <p1>and the first NMOS transistor <n1>There is only one conducting MOS transistor; for the second PMOS transistor <p2>and the second NMOS transistor <n2>, due to the second PMOS transistor <p2>Gate and the second NMOS transistor <n2>The connection relationships of the gates are the same, that is, based on different levels of the second complementary bit line ISABLB, the second PMOS transistor <p2>or the second NMOS transistor <n2>When conducting, the second PMOS transistor <p2>and the second NMOS transistor <n2>There is only one conducting MOS transistor.

[0042] Specifically, when the second PMOS transistor <p2>After conduction, the first signal terminal is connected to the first read bit line SABL, thereby pulling up the first read bit line SABL to the first level signal PCS, and further pulling up the initial bit line BL to the first level signal PCS, so that the data read by the memory through the initial bit line BL is the high level corresponding to the logic "1" of the first level signal PCS; when the first NMOS transistor <n1>After conduction, the second signal terminal is connected to the first complementary read bit line SABLB, thereby pulling down the first complementary read bit line SABLB to the second level signal NCS, and further pulling down the initial complementary bit line BLB to the second level signal NCS, so that the data read by the memory through the initial complementary bit line BLB is the low level corresponding to the logic "0" of the second level signal NCS; when the first PMOS transistor <p1>After conduction, the first signal terminal is connected to the first complementary read bit line SABLB, thereby pulling up the first complementary read bit line SABLB to the first level signal PCS, and further pulling up the initial complementary bit line BLB to the first level signal PCS, so that the data read by the memory through the initial complementary bit line BLB is the high level corresponding to the logic "1" of the first level signal PCS; when the second NMOS transistor <n2>After conduction, the second signal terminal is connected to the first sense bit line SABL, thereby pulling down the first sense bit line SABL to the second level signal NCS, and further pulling down the initial bit line BL to the second level signal NCS, so that the data read by the memory through the initial bit line BL is the low level corresponding to the logic "0" of the second level signal NCS.

[0043] In this embodiment, the sense amplification structure further includes: a third isolation unit 203, with one end connected to the initial bit line BL and the other end connected to the first sense bit line SABL, for electrically connecting the initial bit line BL and the first sense bit line SABL according to the second isolation signal (Isolation Signal 2, ISO2); a fourth isolation unit 204, with one end connected to the initial complementary bit line BLB and the other end connected to the first complementary sense bit line SABLB, for electrically connecting the initial complementary bit line BLB and the first complementary sense bit line SABLB according to the second isolation signal (Isolation Signal 2, ISO2).

[0044] The third isolation unit 203 includes a third isolation MOS transistor <23>, the source of the third isolation MOS transistor <23> is connected to the initial bit line BL, the drain is connected to the first sense bit line SABL, and the gate is used to receive the second isolation signal (Isolation Signal 2, ISO2). The fourth isolation unit 204 includes a fourth isolation MOS transistor <24>, the source of the fourth isolation MOS transistor <24> is connected to the initial complementary bit line BLB, the drain is connected to the first complementary sense bit line SABLB, and the gate is used to receive the second isolation signal (Isolation Signal 2, ISO2).

[0045] During the offset cancellation stage and the amplification stage, the sense amplifier circuit provides the second isolation signal ISO2 to achieve charge sharing between the initial bit line BL and the first sense bit line SABL, and between the initial complementary bit line BLB and the first complementary sense bit line SABLB.

[0046] In this embodiment, the sense amplification structure further includes: an equalization unit 401, with one end connected to the first sense bit line SABL and the other end connected to the first complementary sense bit line SABLB, for making the voltage of the first sense bit line SABL the same as the voltage of the first complementary sense bit line SABLB according to the equalization signal (Equalizing Signal, EQ).

[0047] Specifically, the equalization unit 401 includes an equalization MOS transistor <41>, the source is connected to the first sense bit line SABL, the drain is connected to the first complementary sense bit line SABLB, and the gate is used to receive the equalization signal EQ.

[0048] It should be noted that the connection manners of the specific "source electrodes" and "drain electrodes" defined by the above transistors do not constitute a limitation to this embodiment. In other embodiments, the connection manner of replacing the "source electrode" with the "drain electrode" and the "drain electrode" with the "source electrode" can be adopted.

[0049] When the control module is turned on based on the control signal, a bias voltage is provided to the gates of the first PMOS transistor and the second PMOS transistor. The first PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first complementary read bit line, and the first level signal is transmitted to the first complementary read bit line. The second PMOS transistor is turned on based on the bias voltage, the first signal terminal is electrically connected to the first read bit line, and the first level signal is transmitted to the first read bit line, thereby realizing the offset cancellation of the PMOS transistor. After the offset cancellation module is turned on based on the offset cancellation signal, the initial bit line is electrically connected to the first complementary read bit line and shares the voltage, the initial complementary bit line is electrically connected to the first read bit line and shares the voltage. The voltage of the initial bit line is used as the gate voltage of the first NMOS transistor to turn on the first NMOS transistor. The second signal terminal is electrically connected to the first complementary read bit line, and the second level signal is transmitted to the first complementary read bit line. The voltage of the initial complementary bit line is used as the gate voltage of the second NMOS transistor to turn on the second NMOS transistor. The second signal terminal is electrically connected to the first read bit line, and the second level signal is transmitted to the first read bit line, thereby realizing the offset cancellation of the NMOS transistor. Since the first PMOS transistor and the second PMOS transistor are turned on based on a stable bias voltage, that is, the voltages of the first read bit line and the first complementary read bit line are kept stable, further stabilizing the voltages of the initial bit line and the initial complementary bit line to avoid voltage fluctuations on the bit line and the complementary bit line, and stably eliminating the offset noise in the sense amplifier circuit.

[0050] It should be noted that in order to highlight the innovative part of this application, units not closely related to solving the technical problems proposed by this application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment. Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of this application.

[0051] Another embodiment of the present application provides a memory architecture, including: a plurality of memory arrays arranged in an initial bit line extension direction and a word line extension direction, where the initial bit line extension direction and the word line extension direction are perpendicular to each other; the sense amplifier structure provided in the above embodiment is disposed between adjacent memory arrays in the initial bit line extension direction; wherein, the sense amplifier structure connects the memory cells of one memory array in the adjacent memory arrays through the initial bit line, and connects the memory cells of the other memory array in the adjacent memory arrays through the initial complementary bit line; a control module is disposed between adjacent memory arrays in the word line extension direction, and the control module is configured to provide a data readout signal, a control signal, and a bias voltage to the sense amplifier structure.

[0052] Figure 2 Schematic diagram of the structural layout of the memory architecture provided in this embodiment Figure 3 Schematic diagram of the specific structure of the memory architecture provided in this embodiment. The following further describes the memory architecture provided in each embodiment of the present application in detail with reference to the accompanying drawings, specifically as follows:

[0053] Reference Figure 2 And Figure 3 , the memory architecture includes:

[0054] A plurality of memory arrays 400 are arranged in the initial bit line BL extension direction and the word line WL extension direction.

[0055] Specifically, the initial bit line BL extension direction and the word line WL extension direction are perpendicular to each other. In this embodiment, referring to Figure 3 , the initial bit line BL extension direction is longitudinal, and the word line WL extension direction is transverse.

[0056] The sense amplifier structure 402 provided in the above embodiment is disposed between adjacent memory arrays 400 in the initial bit line BL extension direction. Among them, the sense amplifier structure 402 connects the memory cells of one memory array 400 in the adjacent memory arrays through the initial bit line BL, and connects the memory cells of the other memory array 400 in the adjacent memory arrays through the initial complementary bit line BLB.

[0057] The control module 401 is disposed between adjacent memory arrays 400 in the word line WL extension direction, and the control module 401 is configured to provide a data readout signal, a control signal, and a bias voltage to the sense amplifier structure.

[0058] Among them, the control signal is used to turn on the first control MOS transistor <11> and the second control MOS transistor <12>; the bias voltage V BIAS is used to provide a gate conduction voltage to the PMOS transistor of the sense amplifier circuit when the first control MOS transistor <11> and the second control MOS transistor <12> are turned on.

[0059] Specifically, referring to Figure 1 The data readout signal includes at least one of an offset cancellation signal OC, a first isolation signal ISO1, a second isolation signal ISO2, and an equalization signal EQ.

[0060] Among them, the first isolation signal ISO1 is used to turn on the first isolation MOS transistor <21> and the second isolation MOS transistor <22>; the second isolation signal ISO2 is used to turn on the third isolation MOS transistor <23> and the fourth isolation MOS transistor <24>; the offset cancellation signal OC is used to turn on the first offset cancellation MOS transistor <31> and the second offset cancellation MOS transistor <32>; the equalization signal EQ is used to turn on the equalization MOS transistor <11>.

[0061] In one example, the control signal is the same as the offset cancellation signal OC, that is, the control module 100 is turned on according to the offset cancellation signal OC. By setting the control signal to be the same as the offset cancellation signal OC, the control module 100 and the offset cancellation module are synchronously controlled, thereby realizing the offset cancellation of the sense amplifier circuit.

[0062] Specifically, referring to Figure 2 and Figure 3 the control module 401 includes: a signal control unit 413 for providing a readout signal and a control signal to the sense amplification structure; a bias control unit 414 for providing a bias voltage to the sense amplification structure.

[0063] Among them, in the word line WL extension direction, the signal control unit 413 and the bias control unit 414 are arranged on opposite sides of the sense amplification structure 402.

[0064] In this embodiment, the control module 401 further includes: a column selection control unit 412 for providing a column selection signal, and the column selection signal is used to turn on some of the initial bit lines BL or the initial complementary bit lines BLB in the memory array 400; a row selection control unit 411 for providing a row selection signal, and the row selection signal is used to turn on some of the word lines WL in the memory array 400; that is, the column selection control unit 412 is used to select the corresponding bit line BL according to the column selection signal so as to select the corresponding memory cell, and the row selection control unit 411 is used to select the corresponding word line WL according to the row selection signal so as to select the corresponding memory cell.

[0065] Since the above embodiment corresponds to this embodiment, this embodiment can be implemented in cooperation with the above embodiment. The relevant technical details mentioned in the above embodiment are still valid in this embodiment, and the technical effects achievable in the above embodiment can also be achieved in this embodiment. To avoid repetition, they are not elaborated here. Correspondingly, the relevant technical details mentioned in this embodiment can also be applied to the above embodiment.

[0066] It should be noted that each unit involved in this embodiment is a logical unit. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or implemented as a combination of multiple physical units. In addition, to highlight the innovative part of this application, units that are not closely related to solving the technical problems proposed in this application are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0067] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing this application. In practical applications, various changes can be made to them in form and details without departing from the spirit and scope of this application.

Claims

1. A sense amplification structure is disposed between adjacent memory arrays. Characterized in that: It includes: A first PMOS transistor, whose gate is connected to a second read bit line, and whose source is connected to a first signal terminal; A first NMOS transistor, whose gate is connected to an initial bit line, and whose source is connected to a second signal terminal; The drain of the first PMOS transistor and the drain of the first NMOS transistor are connected to a first complementary read bit line, wherein the first signal terminal is used to receive a first level signal, and the second signal terminal is used to receive a second level signal; A second PMOS transistor, whose gate is connected to a second complementary read bit line, and whose source is connected to the first signal terminal; A second NMOS transistor, whose gate is connected to an initial complementary bit line, and whose source is connected to the second signal terminal; The drain of the second PMOS transistor and the drain of the second NMOS transistor are connected to a first read bit line, wherein the initial bit line is connected to a memory cell of one of the adjacent memory arrays, and the initial complementary bit line is connected to a memory cell of the other of the adjacent memory arrays; An offset cancellation module, partially connected between the initial bit line and the first complementary read bit line, and partially connected between the initial complementary bit line and the first read bit line, for electrically connecting the initial bit line and the first complementary read bit line, and electrically connecting the initial complementary bit line and the first read bit line according to an offset cancellation signal; A control module, connected to the second read bit line and the second complementary read bit line, for providing a bias voltage to the first PMOS transistor and the second PMOS transistor according to a control signal.

2. The sense amplification structure according to claim 1, Characterized in that: The control signal is the same as the offset cancellation signal.

3. The sense amplification structure according to claim 1 or 2, Characterized in that: The control signal includes a first control signal and a second control signal, and the control module includes: A first control unit, one end of which is connected to the second read bit line, and the other end of which is used to receive the bias voltage, for providing the bias voltage to the first PMOS transistor according to the first control signal; A second control unit, one end of which is connected to the second complementary read bit line, and the other end of which is used to receive the bias voltage, for providing the bias voltage to the second PMOS transistor according to the second control signal.

4. The sense amplification structure according to claim 3, Characterized in that: The first control unit includes a first control MOS transistor, and the second control unit includes a second control MOS transistor; The source of the first control MOS transistor is connected to the second read bit line, the gate is used to receive the first control signal, and the drain is used to receive the bias voltage; The source of the second control MOS transistor is connected to the second complementary read bit line, the gate is used to receive the second control signal, and the drain is used to receive the bias voltage.

5. The sense amplification structure according to claim 1, Characterized in that: It further includes: A first isolation unit, one end of which is connected to the first read bit line and the other end of which is connected to the second read bit line, for electrically connecting the first read bit line and the second read bit line according to a first isolation signal; A second isolation unit, one end of which is connected to the first complementary read bit line and the other end of which is connected to the second complementary read bit line, for electrically connecting the first complementary read bit line and the second complementary read bit line according to the first isolation signal.

6. The sense amplification structure according to claim 5, wherein, the first isolation unit includes a first isolation MOS transistor, and the second isolation unit includes a second isolation MOS transistor; the source of the first isolation MOS transistor is connected to the first read bit line, the drain is connected to the second read bit line, and the gate is for receiving the first isolation signal; the source of the second isolation MOS transistor is connected to the first complementary read bit line, the drain is connected to the second complementary read bit line, and the gate is for receiving the first isolation signal.

7. The sense amplification structure according to claim 1, wherein, further comprising: A third isolation unit, one end of which is connected to the initial bit line and the other end of which is connected to the first read bit line, for electrically connecting the initial bit line and the first read bit line according to a second isolation signal; A fourth isolation unit, one end of which is connected to the initial complementary bit line and the other end of which is connected to the first complementary read bit line, for electrically connecting the initial complementary bit line and the first complementary read bit line according to the second isolation signal.

8. The sense amplification structure according to claim 7, wherein, the third isolation unit includes a third isolation MOS transistor, and the fourth isolation unit includes a fourth isolation MOS transistor, the source of the third isolation MOS transistor is connected to the initial bit line, the drain is connected to the first read bit line, and the gate is for receiving the second isolation signal; the source of the fourth isolation MOS transistor is connected to the initial complementary bit line, the drain is connected to the first complementary read bit line, and the gate is for receiving the second isolation signal.

9. The sense amplification structure according to claim 1, wherein, further comprising: An equalization unit, one end of which is connected to the first read bit line and the other end of which is connected to the first complementary read bit line, for making the voltage of the first read bit line the same as the voltage of the first complementary read bit line according to an equalization signal.

10. The sense amplification structure according to claim 9, wherein, the equalization unit includes an equalization MOS transistor, the source of the equalization MOS transistor is connected to the first read bit line, the drain is connected to the first complementary read bit line, and the gate is for receiving the equalization signal.

11. The sense amplification structure according to claim 1, wherein, the offset cancellation module includes: A first offset cancellation MOS transistor, the source of which is connected to the initial bit line, the drain of which is connected to the first complementary read bit line, and the gate of which is for receiving the offset cancellation signal, for electrically connecting the initial bit line and the first complementary read bit line according to the offset cancellation signal; The second offset cancellation MOS transistor has its source connected to the initial complementary bit line, its drain connected to the first read bit line, and its gate for receiving the offset cancellation signal, and is used to electrically connect the initial complementary bit line and the first read bit line according to the offset cancellation signal.

12. A memory architecture, characterized in that, it includes: a plurality of memory arrays arranged in the initial bit line extension direction and the word line extension direction, and the initial bit line extension direction and the word line extension direction are perpendicular to each other; The sense amplifier structure according to any one of claims 1 to 11 is provided between adjacent ones of the memory arrays in the initial bit line extension direction; wherein, the sense amplifier structure is connected to the memory cells of one of the adjacent memory arrays through the initial bit line, and is connected to the memory cells of the other adjacent memory array through the initial complementary bit line; A control module is provided between adjacent ones of the memory arrays in the word line extension direction, and the control module is used to provide a data readout signal, a control signal and a bias voltage to the sense amplifier structure.

13. The memory architecture according to claim 12, characterized in that, The data readout signal includes at least one of an offset cancellation signal, a first isolation signal, a second isolation signal, and an equalization signal, and the control module includes: A signal control unit for providing the data readout signal and the control signal to the sense amplifier structure; A bias voltage control unit for providing the bias voltage to the sense amplifier structure.

14. The memory architecture according to claim 13, characterized in that, The signal control unit and the bias voltage control unit are arranged on opposite sides of the sense amplifier structure.

15. The memory architecture according to claim 13, characterized in that, The control signal and the offset cancellation signal are the same.

16. The memory architecture according to claim 12, characterized in that, The control module further includes: A column selection control unit for providing a column selection signal, and the column selection signal is used to conduct some of the initial bit lines or the initial complementary bit lines in the memory array; A row selection control unit for providing a row selection signal, and the row selection signal is used to conduct some of the word lines in the memory array.

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