Memory circuit and operating method thereof

Abstract

An embodiment of the present application provides a memory circuit and an operating method thereof. The memory circuit includes a data register configured to receive a signal including a plurality of data elements, a first selection circuit coupled to the data register, a counter, a second selection circuit coupled to the counter, and an inverter coupled between the counter and the second selection circuit. The data register outputs a plurality of bits of each data element to the first selection circuit, the counter and the inverter generate complementary signals, wherein the sequence data elements have cyclic values ​​that step in opposite directions, the second selection circuit alternately outputs each complementary signal as a selection signal to the first selection circuit, and the first selection circuit outputs the plurality of bits of the data element in an alternating sequence order in response to the selection signal.

Description

Technical Field

[0001] Embodiments of the present application relate to a memory circuit and an operating method thereof. Background Art

[0002] Memory arrays are commonly used to store and access data for various types of calculations, such as logical or mathematical operations. To perform these operations, data bits are moved between the memory array and the circuitry that performs the calculations. In some cases, the calculations involve multiple layers of operations, and the result of a first operation is used as input data for a second operation. Summary of the Invention

[0003] According to one aspect of an embodiment of the present application, a memory circuit is provided, comprising: a first data register configured to receive a first signal comprising a first plurality of data elements; a first selection circuit coupled to the first data register; a first counter; a second selection circuit coupled to the first counter; and an inverter coupled between the first counter and the second selection circuit, wherein the first data register is configured to output multiple bits of each data element of the first plurality of data elements to the first selection circuit, the first counter and the inverter are configured to generate complementary signals in which sequential data elements have cyclic values ​​that step in opposite directions, the second selection circuit is configured to alternately output each of the complementary signals as a first selection signal to the first selection circuit, and the first selection circuit is configured to output multiple bits of the data elements of the first plurality of data elements in an alternating sequence order in response to the first selection signal.

[0004] According to another aspect of an embodiment of the present application, a memory circuit is provided, comprising: an input circuit, the input circuit comprising: a first selection circuit, configured to receive a first selection signal and a first signal comprising a first plurality of data elements; and a first counter and a second counter, coupled to the second selection circuit, wherein the first counter and the second counter and the second selection circuit are configured to generate the first selection signal and the second selection signal; a first multiplier, coupled to the first selection circuit; an adder, coupled to the first multiplier; and an accumulator, coupled to the adder and configured to receive the second selection signal, wherein, in response to the first selection signal, the first selection circuit is configured to output multiple bits of data elements of the first plurality of data elements in an alternating sequence order to the first multiplier, and in response to the second selection signal, the accumulator is configured to perform a first accumulation operation and a second accumulation operation based on the multiple bits of the data elements of the first plurality of data elements output by the first selection circuit in an alternating sequence.

[0005] According to another aspect of an embodiment of the present application, a method of operating a memory circuit is provided, the method comprising: receiving a first signal at an input circuit, the first signal comprising a first plurality of data elements; generating a complementary signal in which the sequence data elements have cyclic values ​​that step in opposite directions; generating a selection signal by alternately selecting each of the complementary signals; and outputting a plurality of bits of the data elements of the first plurality of data elements in an alternating sequence order in response to the selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various components are not drawn to scale and are used for illustrative purposes only. In fact, the dimensions of various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a schematic diagram of a data serialization circuit according to some embodiments.

[0008] Figure 2 is a schematic diagram of an input circuit according to some embodiments.

[0009] Figure 3A and Figure 3B is a corresponding schematic diagram of an input circuit and operating parameters of the input circuit according to some embodiments.

[0010] Figure 4A and Figure 4B is a schematic diagram of an accumulator according to some embodiments.

[0011] Figure 5 is a flowchart of a method of performing a data sorting operation according to some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for implementing the different features of the present invention. Specific embodiments or examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Furthermore, for ease of description, spacing terms such as "below," "beneath," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. In addition to the orientations shown in the figures, spacing terms are intended to encompass different orientations of the device during use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spacing descriptors used herein should be interpreted accordingly.

[0014] In various embodiments, a data sequence circuit is configured to transmit bits of data elements in an alternating sequence order such that adjacent bits of consecutively transmitted data elements are identical to one of the most significant bit (MSB) or the least significant bit (LSB). In applications (e.g., compute-in-memory (CIM) operations) where consecutive data elements are more likely to have MSBs and / or LSBs of the same value, the data sequence circuit is able to reduce signal toggle rates and, therefore, power consumption compared to methods that do not transmit bits in an alternating sequence order.

[0015] Figure 1 FIG2 is a schematic diagram of a data sequence circuit 100 according to some embodiments. The data sequence circuit 100, also referred to as circuit 100 or memory circuit 100 in some embodiments, includes an input circuit 110, a storage element 120, multipliers M0 and M1, an adder 130, an accumulator 140, and a data bus OUTB.

[0016] Input circuit 110 includes input paths 111 and 113 configured to receive respective signals IN0[0:n] and IN1[0:n], output terminals 112 and 114 coupled to multipliers M0 and M1 and configured to output signals X and Y, and output terminal 116 coupled to input terminal 141 of accumulator 140 and configured to output signal SeqSel, also referred to as select signal SeqSel in some embodiments. Multipliers M0 and M1 are further coupled to storage element 120 and adder 130, and are configured to receive respective data elements W0 and W1 from storage element 120 and output respective data elements P0 and P1 to adder 130. Adder 130 is coupled to accumulator 140 via data bus PSB and is configured to output a partial sum PS on data bus PSB. The accumulator 140 is configured to receive the partial sum PS on the data bus PSB and the signal SeqSel on the input terminal 141 , and output a signal OUT on the data bus OUTB.

[0017] In some embodiments, the data sequence circuit 100 does not include the storage element 120, the multipliers M0 and M1, the adder 130, the accumulator 140, and the data bus OUTB, but includes an input circuit 110 configured to Figure 1 Signals X and Y are outputted at output terminals 112 and 114 in different configurations shown (eg, coupled to one or more external circuits).

[0018] Two or more circuit elements are considered coupled based on direct electrical connection or electrical connection involving one or more additional circuit elements and thus can be controlled, for example, by one or more transistors or other switching devices being made blocking or on.

[0019] Figure 1 The illustrated embodiment is a simplified non-limiting example for purposes of illustration. In some embodiments, the data sequence circuit 100 includes, in addition to Figure 1 Circuit elements other than those shown and discussed below, for example, control circuits or additional instances of the circuit elements shown. In some embodiments, Figure 1 The elements shown in are part of a memory array that includes rows and columns corresponding to multiple instances of input circuit 110 , storage element 120 , multipliers M0 and M1 , adder 130 , and / or accumulator 140 .

[0020] In some embodiments, the data sequence circuit 100 is part of a CIM circuit that includes elements configured to perform in-memory computations, such as performing a convolutional neural network (CNN), wherein an array includes stored weight data elements, such as data elements W0 and W1, that are applied to one or more sets of input data elements (e.g., signals IN0[0:n] and IN1[0:n]) in a multiply and accumulate (MAC) operation.

[0021] Figure 1 The relationships between the circuit elements shown are non-limiting examples provided for illustration purposes. In some embodiments, a total of more than two multipliers M0 and M1 correspond to a single instance of storage element 120 , adder 130 , and / or accumulator 140 .

[0022] Each of signals IN0[0:n] and IN1[0:n] (also referred to as input signals IN0[0:n] and IN1[0:n] in some embodiments) includes a group of data elements, each data element including a predetermined total number of bits equal to n+1, as discussed below.

[0023] Input circuit 110 is an electronic circuit, such as an integrated circuit (IC), configured to receive one or more input signals (e.g., signals IN0[0:n] and IN1[0:n]) and output data elements of the input signals as successive portions of corresponding one or more output signals (e.g., signals X and Y). As discussed below, input circuit 110 is configured to transmit bits of the data elements in an alternating sequence order such that adjacent bits of consecutively transmitted data elements are the same one of the MSB or LSB. In some embodiments, input circuit 110 includes the following regarding Figure 2 Input circuit 200 is discussed.

[0024] Each of the input paths 111 and 113 is one or more signal paths configured to receive respective signals IN0[0:n] and IN1[0:n]. In various embodiments, each of the input paths 111 and 113 is an input terminal configured to receive respective signals IN0[0:n] or IN1[0:n] transmitted serially or configured to receive respective signals IN0[0:n] or IN1[0:n] transmitted in a parallel configuration.

[0025] exist Figure 1 In the illustrated embodiment, input circuit 110 is configured to receive a total of two input signals, each input signal comprising a data element, each data element comprising n bits. As the number of input signals, the number of data elements, and the number of bits per data element each increase, circuit complexity and power consumption increase as functional capabilities (e.g., the ability to efficiently process large data sets) increase.

[0026] In some embodiments, input circuit 110 is configured to receive a total of one or more than two input signals. In some embodiments, input circuit 110 is configured to receive a total number of input signals ranging from 4 to 32. In some embodiments, input circuit 110 is configured to receive a total number of input signals ranging from 8 to 16.

[0027] In some embodiments, input circuit 110 is configured to receive a number of bits per data element equal to four. In some embodiments, input circuit 110 is configured to receive a number of bits per data element less than or greater than four. In some embodiments, input circuit 110 is configured to receive a number of bits per data element ranging from 1 to 16. In some embodiments, input circuit 110 is configured to receive a number of bits per data element ranging from 8 to 12.

[0028] In some embodiments, input circuit 110 is configured to receive a number of data elements for each of signals IN0[0:n] and IN1[0:n] ranging from 4 to 512. In some embodiments, input circuit 110 is configured to receive a number of data elements for each of signals IN0[0:n] and IN1[0:n] ranging from 32 to 128.

[0029] The input circuit 110 includes one or more data registers ( Figure 1 (not shown), the data registers are configured to receive and temporarily store data elements of signals IN0[0:n] and IN1[0:n], for example, by including one or more latch or flip-flop circuits. In various embodiments, the one or more data registers are configured to receive bit data of the data elements of signals IN0[0:n] and IN1[0:n] in parallel or serially.

[0030] One or more data registers are coupled to one or more selection circuits ( Figure 1 The circuits may further include a plurality of select circuits (not shown), such as multiplexers, and may be configured to output bits of a given data element to one or more selection circuits. The one or more selection circuits may be configured to sequentially output the data elements of signals IN0[0:n] and IN1[0:n] as signals X and Y, where the bits of the data elements in signals X and Y have a sequential order based on the logic level of signal SeqSel.

[0031] The input circuit 110 includes a signal generating portion configured to receive one or more clock signals ( Figure 1 Not shown), for example, the following Figure 3A and Figure 3B The clock signal CLK discussed above is used to generate a signal SeqSel that alternates between a first logic level corresponding to a first sequential order (e.g., 0 to n) and a second logic level corresponding to a second sequential order opposite to the first sequential order (e.g., n to 0). In some embodiments, the first sequential order is an LSB-to-MSB order corresponding to a progression from the LSB of a given data element to the MSB of the given data element, and the second sequential order is an MSB-to-LSB order corresponding to a progression from the MSB of the given data element to the LSB of the given data element.

[0032] The signal generation portion is configured to generate a signal SeqSel having first and second logic levels synchronized with the data elements so that all n bits of a given data element are output in the same sequential order. In some embodiments, the first logic level corresponds to a first operating mode of the data sequence circuit 100, and the second logic level corresponds to a second operating mode of the data sequence circuit 100.

[0033] Input circuit 110 is thus configured to generate signals X and Y that include bits of data elements of respective signals IN0[0:n] and IN1[0:n] in an alternating sequence order such that adjacent bits of successively transmitted data elements are the same one of the MSB or the LSB, and to generate signal SeqSel having alternating logic levels synchronized with the alternating sequence order.

[0034] A storage element (e.g., storage element 120) is an electrical, electromechanical, electromagnetic, or other device configured to store one or more data elements, each of which comprises one or more data bits represented by a logical state. In some embodiments, the logical state corresponds to the voltage level of the charge stored in part or all of the storage element. In some embodiments, the logical state corresponds to a physical property of part or all of the storage element, such as resistance or magnetic orientation.

[0035] In some embodiments, the storage element includes one or more static random access memory (SRAM) cells. In various embodiments, the SRAM cell (e.g., a five-transistor (5T), six-transistor (6T), eight-transistor (8T), or nine-transistor (9T) SRAM cell) includes a number of transistors ranging from two to twelve. In some embodiments, the SRAM cell includes a multi-rail SRAM cell. In some embodiments, the length of the SRAM cell is at least twice its width.

[0036] In some embodiments, the storage element includes one or more dynamic random access memory (DRAM) cells, resistive random access memory (RRAM) cells, magnetoresistive random access memory (MRAM) cells, ferroelectric random access memory (FeRAM) cells, NOR (exclusive OR) flash memory cells, NAND (non-and) flash memory cells, conductive bridging random access memory (CBRAM) cells, data registers, non-volatile memory (NVM) cells, 3D NVM cells, or other memory cell types capable of storing a bit of data. In some embodiments, the storage element is part or all of a memory array.

[0037] Storage element 120 includes data elements W0 and W1. In some embodiments where data sequence circuit 100 is included in a CIM circuit, data elements W0 and W1 correspond to weight data for one or more matrix calculations.

[0038] As the number of data elements and the number of bits per data element stored in storage element 120 increases, circuit complexity and power consumption increase as functional capabilities (eg, increased weight data resolution) increase.

[0039] exist Figure 1In the illustrated embodiment, storage element 120 includes a total of two data elements, W0 and W1. In some embodiments, storage element 120 includes one or more than two data elements, W0 and W1. In some embodiments, storage element 120 includes a number of data elements ranging from 4 to 1024. In some embodiments, storage element 120 includes a number of data elements ranging from 8 to 128.

[0040] In some embodiments, storage element 120 is configured to store a number of bits per data element (eg, data elements W0 and W1) ranging from 1 to 16. In some embodiments, storage element 120 is configured to store a number of bits per data element ranging from 4 to 8.

[0041] Storage element 120 includes one or more I / O connections (not shown) through which logic states are programmed in write operations and accessed in read operations (eg, multiplication operations).

[0042] A multiplier (e.g., multiplier M0 or M1) is an electronic circuit comprising one or more logic gates configured to perform a mathematical operation (e.g., a multiplication) based on a received data bit (e.g., one of the bits of signal X or Y) and a received data element (e.g., data element W0 or W1 received from storage element 120), thereby generating a product data element (e.g., data element P0 or P1) that is equal to the product of the input data bit and the input data element. In some embodiments, the multiplier is configured to generate a product data element that includes a number of bits equal to the number of bits of the received data element. In various embodiments, the multiplier comprises one or more AND or NOR gates or other circuitry suitable for performing some or all of the multiplication operations.

[0043] The data sequence circuit 100, including the input circuit 110 and the multipliers M0 and M1, is thus configured such that the multipliers M0 and M1 receive respective signals X and Y in the alternating bit sequence order discussed above so as to sequentially generate corresponding instances of data elements P0 and P1 as products of respective data elements W0 and W1 multiplied by the alternatingly ordered bits of the signals X and Y.

[0044] Adder 130 is an electronic circuit comprising multiple layers of adder circuitry (not shown), wherein a first layer is configured to receive a plurality of data elements, such as data elements P0 and P1, and a final layer comprises a single logical addition device configured to generate a data element, such as a partial sum PS, based on the received plurality of data elements. In some embodiments, each of one or more successive layers between the first and final layers is configured to receive a first number of sum data elements generated by a previous layer and, based on the first number of sum data elements, generate a second number of sum data elements, the second number being half the first number. Thus, the total number of layers includes the first and final layers, as well as each successive layer (if any).

[0045] The total number of layers of adder 130 is configured to correspond to the number of received data elements (e.g., data elements P0 and P1). In some embodiments, the total number of layers of adder 130 ranges from 1 to 9. In some embodiments, the total number of layers of adder 130 ranges from 2 to 6.

[0046] An adder circuit is an electronic circuit comprising one or more logic gates configured to perform a mathematical operation (e.g., addition) based on received first and second data elements (e.g., data elements P0 and P1) to generate a sum data element, the sum data element being equal to the sum of the received first and second data elements. In some embodiments, the adder circuit is configured to generate the sum data element including a bit quantity that is one greater than the bit quantity of each of the received first and second data elements. In various embodiments, the adder circuit comprises one or more full adder gates, half adder gates, ripple carry adder circuits, carry-save adder circuits, carry-select adder circuits, carry-lookahead adder circuits, or other circuits suitable for performing part or all of an addition operation.

[0047] In some embodiments, each adder circuit in each layer of adders 130 is configured to generate a corresponding sum data element that includes a number of bits that is one greater than the number of bits of the sum data element of the previous layer (or, in the case of the first layer, the data element of the received multiple data elements).

[0048] The data bus PSB includes a number of signal paths at least equal to the number of bits of the sum data elements of the last layer of adder circuitry.The adder 130 is configured to output portions of the sum PS bits arranged from LSB to MSB on the data bus PSB.

[0049] In some embodiments, the data bus PSB includes a number of signal paths that is at least twice the number of bits of the sum data elements of the last layer of adder circuitry, and the adder 130 is configured to generate the partial sum PS and append the partial sum PS by including a number of bits that is at least twice the number of bits of the sum data elements of the last layer of adder circuitry.

[0050] In such an embodiment, each of the at least two bits added has a low logic level, and the adder 130 is configured to output the additional bits at the outermost signal path of the data bus PSB, so that in operation, the partial sum PS is expanded in each of the LSB direction and the MSB direction by at least one bit having a low logic level. In some embodiments, the adder 130 is configured to output the additional bits at the outermost signal path of the data bus PSB, so that in operation, the partial sum PS is expanded in each of the LSB direction and the MSB direction by the total number of low logic level bits being one less than the number of bits per data element of the signals IN0[0:n], IN1[0:n], X, and Y (i.e., the total number of low logic level bits in each direction is equal to n).

[0051] The data sequence circuit 100 including the input circuit 110 and the adder 130 is thus configured such that the adder 130 receives instances of the sequentially generated data elements P0 and P1 and sequentially generates instances of the partial sum PS as the sum of the sequentially generated data elements P0 and P1 based on the alternating ordering of bits of the signals X and Y discussed above.

[0052] The accumulator 140 includes an adder circuit, a data register, a first shifter and a second shifter, and a first selection circuit and a second selection circuit ( Figure 1 The electronic circuits (not shown) are coupled together to form a feedback device. The feedback device includes a first selection circuit, an adder circuit, and a data register coupled in series between the data bus PSB and OUTB. The first feedback path includes a second selection circuit and a first shifter coupled between the data bus OUTB and the adder circuit. The second feedback path includes a second selection circuit and a second shifter coupled between the data bus OUTB and the adder circuit. In some embodiments, the accumulator 140 includes the following: Figure 4A and Figure 4B The accumulator 400 is discussed.

[0053] In various embodiments, a given one of the adder circuit, the data register, the two shifters, and the two selection circuits is an independent circuit, a collection of circuits, or part of a larger circuit. In some embodiments, the two shifters are part of the same shifter circuit (e.g., a reconfigurable circuit), and / or the two selection circuits are part of the same circuit.

[0054] The first selection circuit is coupled to the adder 130 via the data bus PSB and is thereby configured to receive an instance of the partial sum PS on the data bus PSB, and each of the first selection circuit and the second selection circuit is coupled to the input circuit 110 via the input terminal 141 and is thereby configured to receive the signal SeqSel from the input circuit 110.

[0055] In operation, the first selection circuit is configured to respond to a signal SeqSel having a first logic level by selecting an instance of the partial sum PS appended to the first LSB / MSB terminal as discussed above, respond to a signal SeqSel having a second logic level by selecting an instance of the partial sum PS appended to the second LSB / MSB terminal as discussed above, and output the selected instance of the partial sum PS (as appended) to the adder circuit. In various embodiments, the first selection circuit is configured to select the appended partial sum PS based on an appended bit received from the adder 130 as discussed above, or, for example, an appended bit received from one or more other sources within the first selection circuit.

[0056] In operation, the second selection circuit is configured to respond to a signal SeqSel having a first logic level by coupling a first shifter in a first feedback path, and to respond to a signal SeqSel having a second logic level by coupling a second shifter in a second feedback path. The first shifter is configured to perform one of a right shift (in the LSB direction) or a left shift (in the MSB direction), and the second shifter is configured to perform the other of the right shift or the left shift operation.

[0057] In operation, the first selection circuit and the second selection circuit are thus configured to select the portion appended at the LSB end and a given instance of PS while being coupled to the first or second shifter configured to perform a right shift operation, and to select the portion appended at the MSB end and a given instance of PS while being coupled to the first or second shifter configured to perform a left shift operation.

[0058] In operation, the data sequence circuit 100 includes an input circuit 110 configured to generate a signal SeqSel, whereby, for example, in a first operating mode, an instance of the partial sum PS appended at the LSB end is selected and coupled to a first or second shifter configured to perform a right shift operation, the right shift operation being performed while the signals X and Y have an LSB to MSB sequence order, and, for example, in a second operating mode, an instance of the partial sum PS appended at the MSB end is selected and coupled to a first or second shifter configured to perform a left shift operation, the left shift operation being performed while the signals X and Y have an MSB to LSB sequence order.

[0059] In operation, the adder circuit is configured to receive instances of the partial sum PS (as appended) in corresponding sequence order and the shifted data elements output from the first or second shifter, and to generate an inner sum data element ( Figure 1 The sequence is not shown).

[0060] The data register is configured to receive and store each of the internal sum data elements and output the internal sum element as a signal OUT to the data bus OUTB and the first and second feedback paths.

[0061] The accumulator 140 is thus configured to perform a first accumulation operation in a sequence order of instances of the partial sum PS corresponding to the signals X and Y having an LSB to MSB sequence order, and to perform a second accumulation operation in a sequence order of instances of the partial sum PS corresponding to the signals X and Y having an MSB to LSB sequence order, in response to the signal SeqSel received at the input terminal 141.

[0062] For example, in the first and second operating modes, the data sequence circuit 100 is configured to transmit n bits of consecutive data elements of the signals IN0[1:n] and IN1[1:n] as signals X and Y in an alternating sequence order to the multipliers M0 and M1, as discussed above, such that adjacent bits of the consecutively transmitted data elements are the same one of the MSB or LSB. Compared to a method that does not transmit bits in an alternating sequence order, the data sequence circuit 100, including the accumulator 140 configured as discussed above, is thus able to perform matrix operations that include a reduced signal toggle rate and, therefore, reduced power consumption.

[0063] Figure 2 FIG. 2 is a schematic diagram of an input circuit 200 according to some embodiments. The input circuit 200 may be used as described above with respect to Figure 1 Some or all of the input circuit 110 discussed.

[0064] Input circuit 200 includes a signal generating section 210, data registers R1 and R2, and selection circuits S2 and S3. Signal generating section 210 includes counters CTRA and CTRB, an inverter INV1, and selection circuit S1. In some embodiments, selection circuits S1-S3 are also referred to as multiplexers S1-S3.

[0065] exist Figure 2In the illustrated embodiment, input circuit 200 includes each of input paths 111 and 113 discussed above, with input paths 111 and 113 configured as data buses for receiving respective signals IN0[0:n] and IN1[0:n] thereon, corresponding to a total of four bits per data element for the case where n=3. In some embodiments, input circuit 200 includes each of input paths 111 and 113, with input paths 111 and 113 additionally configured, for example, to receive signals IN0[0:n] and IN1[0:n] corresponding to a total of fewer or more than four bits per data element.

[0066] Data register R1 is coupled to input path 111 and is thereby configured to receive signals IN0[0:n], which are input to the Figure 2 ] is represented as a single data element comprising bits IN0[0] to IN0[3]. An output terminal (not labeled) of data register R1 is coupled to an input terminal (not labeled) of selection circuit S2.

[0067] Data register R2 is coupled to input path 113 and is thereby configured to receive signal IN1[0:n], which is Figure 2 ] is represented as a single data element comprising bits IN1[0] to IN1[3]. An output terminal (not labeled) of data register R2 is coupled to an input terminal (not labeled) of selection circuit S3.

[0068] exist Figure 2 In the embodiment shown, each of the data registers R1 and R2 includes a total of four data flip-flops DFF, the four data flip-flops DFF corresponding to the four bits of each data element IN0[0] to IN0[3] and IN1[0] to IN1[3]. Each data flip-flop DFF is configured to receive a clock signal ( Figure 2 (not shown) such that, based on the clock signal, successive instances of the data elements of the signals IN0[0:n] and IN1[0:n] are synchronously latched and synchronously output to the respective selection circuits S2 and S3. In some embodiments, each data flip-flop DFF is configured to receive the signal SeqSel discussed above.

[0069] Each of counters CTRA and CTRB is configured to receive a clock signal and, based on the clock signal, generate a corresponding one of signal SA or signal SeqSel, discussed above. An output terminal (not labeled) of counter CTRA is coupled to input terminals (not labeled) of each of selection circuit S1 and inverter INV1. An output terminal (not labeled) of inverter INV1 is coupled to an input terminal (not labeled) of selection circuit S1. An output terminal (not labeled) of counter CTRB is coupled to an input terminal (not labeled) of selection circuit S1 and output terminal 116, discussed above. An output terminal (not labeled) of selection circuit S1 is coupled to an input terminal (not labeled) of each of selection circuits S2 and S3. Output terminals (not labeled) of selection circuits S2 and S3 are coupled to respective output terminals 112 and 114, discussed above.

[0070] exist Figure 2 In the illustrated embodiment, the counter CTRA is configured to generate a signal SA including sequential data elements having cyclic values ​​that decrease from the highest-numbered bit of each data element of the signals IN0[0:n] and IN1[0:n] to zero (e.g., from 3 to 0). Based on the signal SA, the inverter INV1 generates a signal SAb including sequential data elements having cyclic values ​​that increase from zero to the highest-numbered bit of each data element of the signals IN0[0:n] and IN1[0:n] (e.g., from 0 to 3).

[0071] The counter CTRA and the inverter INV1 are thus configured to output complementary signals SA and SAb to the selection circuit S1, in which the sequence data elements have cyclic values ​​that step in opposite directions. In some embodiments, for example, by including a counter CTRA configured to generate a signal SA including sequence data elements having cyclic values ​​that increment from zero to the highest-numbered bit of each data element of the signals IN0[0:n] and IN1[0:n], the counter CTRA and the inverter INV1 are further configured to output complementary signals SA and SAb to the selection circuit S1, in which the sequence data elements have cyclic values ​​that step in opposite directions.

[0072] The counter CTRB is configured to generate a signal SeqSel including a sequence of bits each having a low logic level and a high logic level, the low logic level and the high logic level lasting for a number of cycles of the clock signal equal to the number of bits of each data element of the signals IN0[0:n] and IN1[0:n]. The counters CTRA and CTRB are configured such that an endpoint of a cycle of values ​​(i.e., a time at which CTRA restarts the cycle of values) is synchronized with a transition of the signal SeqSel between a low logic level and a high logic level.

[0073] The selection circuit S1 is configured to output one of the alternating signals SA or SAb as a signal SEL (also referred to as a selection signal SEL in some embodiments) to each of the selection circuits S2 and S3 in response to the alternating logic levels of the signal SeqSel. In response to the signal SEL, the selection circuit S2 is configured to generate a signal X by sequentially selecting bits IN0[0] to IN0[3] in an alternating order corresponding to the selected signals SA and SAb, and the selection circuit S3 is configured to generate a signal Y by sequentially selecting bits IN1[0] to IN1[3] in an alternating order corresponding to the selected signals SA and SAb.

[0074] Figure 2 The number of selection circuits shown that are configured to receive signal SEL and sequentially select bits in an alternating order is a non-limiting example. In various embodiments, input circuit 200 includes a single one of selection circuits S2 or S3, or includes one or more selection circuits in addition to selection circuits S2 and S3 configured to receive signal SEL.

[0075] Through the configuration discussed above, the input circuit 200 can perform the above-mentioned operations with respect to the input circuit 110 and Figure 1 The discussed operations, such as operating in the first and second modes of operation, enable a circuit including the input circuit 200 to achieve the benefits discussed above with respect to the data sequence circuit 100 .

[0076] Figure 3A and Figure 3B is a corresponding schematic diagram of portions of the input circuit 200 and corresponding operating parameters according to some embodiments. Figure 3A Including counters CTRA and CTRB, inverter INV1, selection circuits S1 and S2 and data register R1, each of which is described above. Figure 2 A discussion was held. Figure 3B The clock signal CLK and each of the signals IN0[0:n] (depicted as IN0[3:0]), SA, SeqSel, SEL, and X are depicted for the non-limiting embodiment discussed above for n=3 corresponding to a total of 4 bits per data element of the signal IN0[0:n].

[0077] exist Figure 3B In the example shown, signal IN0[3:0] includes a first data element 0011 including four bits corresponding to four cycles of the clock signal CLK, and a second data element 0101 including four bits corresponding to four cycles of the clock signal CLK.

[0078] The counter CTRA generates a signal SA having values ​​that cycle in descending order from 11 to 00, and the counter CTRB generates a signal SeqSel that alternates between a low logic level and a high logic level. The selection circuit S1 thus generates a signal SEL having a first sequence of values ​​in descending order from 11 to 00 (corresponding to the signal SA) and a second sequence of values ​​in ascending order from 00 to 11 (corresponding to the signal SAb).

[0079] The selection circuit S2 generates a first data element 0011 of the signal X by selecting the bits of the first data element 0011 of the signal IN0[3:0] in a first order such that the first data element 0011 of the signal X matches the first data element 0011 of the signal IN0[3:0]. The selection circuit S2 generates a second data element 1010 of the signal X by selecting the bits of the second data element 0101 of the signal IN0[3:0] in a second order such that the second data element 1010 of the signal X has an order opposite to that of the second data element 0101 of the signal IN0[3:0].

[0080] Figure 4A and Figure 4B is a schematic diagram of an accumulator 400 according to some embodiments. The accumulator 400 can be used as described above with respect to Figure 1 Some or all of the accumulators 140 discussed. Figure 4A An accumulator 400 is depicted, for example operating in a first operating mode, the accumulator 400 corresponding to the signal SeqSel having a first logic level and each of the signals X and Y having an LSB to MSB sequential order, and Figure 4B The accumulator 400 is depicted, eg, operating in a second mode of operation, corresponding to the signal SeqSel having a second logic level and each of the signals X and Y having an MSB to LSB sequential order.

[0081] The accumulator 400 includes a selection circuit S4, an adder circuit A1 and a data register R3 coupled in series between the data bus PSB and OUTB, a first feedback path FB1 includes a selection circuit S5 and a right shifter SHR coupled between the data bus OUTB and the adder circuit A1, and a second feedback path FB2 includes a selection circuit S5 and a left shifter SHL coupled between the data bus OUTB and the adder circuit A5.

[0082] The selection circuit S4 includes a plurality of input terminals (not labeled) coupled to the adder 130 via the data bus PSB, and is configured to receive an instance of the partial sum PS on the data bus PSB, as described above with respect to the adder 130 and Figure 1 As discussed in the attached. Figure 4A and Figure 4BIn the embodiment shown, selection circuit S4 is configured to receive at least one additional bit BL and at least one additional bit BM from adder 130. In some embodiments, selection circuit S4 is further configured to receive some or all of the additional bits BL and BM from within selection circuit S4.

[0083] The selection circuit S4 includes an input terminal (not labeled) coupled to the input terminal 141 and is thus configured to receive the signal SeqSel from the input circuit 110. In operation, the selection circuit S4 is configured to respond to the signal SeqSel having a first logic level by selecting the portion and the instance of PS appended with at least one additional bit BL at the LSB end, as shown in FIG. Figure 4A As shown, and in response to the signal SeqSel having the second logic level by selecting the portion and the instance of PS to which at least one additional bit BM is appended at the MSB end, as shown Figure 4B shown.

[0084] The selection circuit S4 comprises a plurality of output terminals (unlabeled) coupled to a plurality of input terminals (unlabeled) of the adder circuit A1 and is thereby configured to output the selected instance of the partial sum PS appended with at least one additional bit BL to the adder circuit A1 as an instance of the data element PSL, as shown Figure 4A , and is configured to output the selected instance of the partial sum PS appended with at least one additional bit BM to the adder circuit A1 as an instance of the data element PSM, as shown Figure 4B shown.

[0085] The selection circuit S5 includes an input terminal (not labeled) coupled to the input terminal 141 and is thus configured to receive the signal SeqSel from the input circuit 110. In operation, the selection circuit S5 is configured to respond to the signal SeqSel having a first logic by coupling the right shifter SHR in the first feedback path FB1, as shown in FIG. Figure 4A As shown, and in response to the signal SeqSel having the second logic level by coupling the left shifter SHL in the second feedback path FB2, as shown Figure 4B shown.

[0086] Selection circuits S4 and S5 are thus configured such that, in operation, selection circuit S4 outputs an instance of data element PSL while selection circuit S5 is coupled to shifter SHR in first feedback path FB1 , and selection circuit S4 outputs an instance of data element PSM while selection circuit S5 is coupled to shifter SHL in second feedback path FB2 .

[0087] The data sequence circuit 100 including the input circuit 110 is configured to generate the signal SeqSel whereby, in operation, the instances of the selection circuits S4 and S5 outputting the data element PSL and coupling the shifter SHR in the first feedback path FB1 are performed simultaneously with the signals X and Y having an LSB to MSB sequence order (e.g., in a first operating mode), and the instances of the selection circuits S4 and S5 outputting the data element PSM and coupling the shifter SHL in the second feedback path FB2 are performed simultaneously with the signals X and Y having an MSB to LSB sequence order (e.g., in a second operating mode).

[0088] Each of the shifters SHR and SHL includes multiple input terminals (unlabeled) coupled to the data bus OUTB and multiple output terminals (unlabeled) coupled to multiple input terminals (unlabeled) of the selection circuit S5, and the selection circuit S5 includes multiple output terminals (unlabeled) coupled to multiple input terminals of the addition circuit A1.

[0089] The shifter SHR is thus configured to, in operation, receive an instance of the signal OUT on the data bus OUTB, perform a right shift function on the received instance, and output the right-shifted instance as an instance of the data element DER to the selection circuit S5. The shifter SHL is thus configured to, in operation, receive an instance of the signal OUT on the data bus OUTB, perform a left shift function on the received instance, and output the left-shifted instance as an instance of the data element DEL to the selection circuit S5.

[0090] During the period in which the selection circuit S5 is coupled to the shifter SHR in the first feedback path FB1, the selection circuit S5 thus outputs an instance of the data element DER to the adder circuit A1, as shown in FIG. Figure 4A As shown, and during the period in which the selection circuit S5 is coupled to the shifter SHL in the second feedback path FB2, the selection circuit S5 thereby outputs an instance of the data element DEL to the adder circuit A1, as shown. Figure 4B shown.

[0091] The adder circuit A1 is thus configured to receive, in operation, an instance of the data element PSL while simultaneously receiving an instance of the data element DER, as Figure 4A As shown, an instance of the data element DEL is received while an instance of the data element PSM is received, such as Figure 4B shown.

[0092] Adder circuit A1 includes multiple output terminals (unlabeled) coupled to multiple input terminals (unlabeled) of data register R3, and is thereby configured to generate and output to data register R3 an instance of a sum data element SDE, the instance of the sum data element SDE being, for example, equal to the sum of the instances of data elements PSL and DER in the first operating mode, or, for example, equal to the sum of the instances of data elements PSM and DEL in the second operating mode.

[0093] The data register R3 is configured to receive a clock signal (e.g. Figure 3A and Figure 3B 1 and 2. The data register R3 is configured to receive, store, and output instances of the data element SDE according to the clock signal CLK, as discussed above, and includes a plurality of output terminals (not labeled) coupled to the data bus OUTB. The data register R3 is thus configured to receive, store, and output instances of the data element SDE according to the clock signal, and output the instances of the data element SDE as the signal OUT to the data bus OUTB and the first feedback path FB1 and the second feedback path FB2. In various embodiments, the clock signal is one or more clock signals received by the input circuit 110 or a separate clock signal synchronized with the one or more clock signals received by the input circuit 100, thereby synchronizing the operation of the accumulator 400 discussed above with the operation of the input circuit 110.

[0094] The accumulator 400 is thus configured to, in operation, perform a first accumulation operation based on instances of data elements PSL corresponding to signals X and Y having an LSB-to-MSB sequential order in response to signal SeqSel having a first logic level, and to perform a second accumulation operation based on instances of data elements PSM corresponding to signals X and Y having an MSB-to-LSB sequential order in response to signal SeqSel having a second logic level.

[0095] With the configuration discussed above, the accumulator 400 is able to perform the above-mentioned operations with respect to the accumulators 140 and 141. Figure 1 The discussed matrix operations, such as operating in the first and second modes of operation, enable a circuit including the accumulator 400 to achieve the benefits discussed above with respect to the data sequence circuit 100 .

[0096] Figure 5 is a flow chart of a method 500 of operating a data sequence circuit according to some embodiments. The method 500 may be used in conjunction with a data sequence circuit (e.g., Figures 1 to 4B In various embodiments, method 500 includes performing sequence operations including some or all of operations 510-550 and / or performing matrix operations including some or all of operations 510-550, each of which is discussed below.

[0097] The order of operations of method 500 is Figure 5 The description is for illustration only; the operation of method 500 can be performed in different Figure 5 In some embodiments, Figure 5 The operations shown are performed before, between, during and / or after Figure 5 In some embodiments, the operations of method 500 are a subset of methods for performing CIM operations.

[0098] At operation 510, in some embodiments, a first signal comprising a first plurality of data elements is received at an input circuit. In some embodiments, receiving the first signal comprises receiving a signal IN0[0:n] at the input circuit 110, as described above with respect to Figures 1 to 3B discussed.

[0099] In some embodiments, receiving the first signal at the input circuit includes receiving a second signal at the input circuit, the second signal including a second plurality of data elements. In some embodiments, receiving the second signal at the input circuit includes receiving signal IN1[0:n] at input circuit 110, as described above with respect to Figures 1 to 3B discussed.

[0100] At operation 520, a complementary signal is generated in which the sequence data elements have cyclic values ​​that step in opposite directions. In some embodiments, generating the complementary signal includes generating signals SA and SAb, as described above with respect to Figures 2 to 3B discussed.

[0101] In some embodiments, generating the complementary signal includes using a first counter (e.g., Figures 2 to 3B The counter CTRA in question is used to generate a first complementary signal of complementary signals including sequence data elements having values ​​decreasing from the highest-numbered bit of each data element of the first plurality of data elements to zero, such as signal SA, and an inverter is used (e.g., inverter INV1) to generate a second complementary signal including sequence data elements having values ​​increasing from zero to the highest-numbered bit of each data element of the first plurality of data elements, such as signal SAb.

[0102] At operation 530, a selection signal is generated by alternately selecting each of the complementary signals. In some embodiments, generating the selection signal includes generating a selection signal SEL, as described above with respect to Figures 1 to 3B discussed.

[0103] Alternatingly selecting each of the complementary signals includes using a selection circuit, such as described above with respect to Figure 2 The selection circuit S1 is discussed.

[0104] In some embodiments, the selection signal is a first selection signal, and generating the selection signal includes generating a second selection signal, such as described above with respect to Figures 1 to 4B Discuss the signal SeqSel.

[0105] In some embodiments, generating the second select signal includes using a second counter (e.g., Figure 2 In some embodiments, generating the second selection signal includes outputting the second selection signal from the input circuit, such as outputting the signal SeqSel from the input circuit 110, as described above with respect to Figures 1 to 4B discussed.

[0106] At operation 540, in response to the select signal, a plurality of bits of the data elements of the first plurality of data elements are output in an alternating sequence order. In some embodiments, outputting a plurality of bits of the data elements of the first plurality of data elements includes outputting a signal X, as described above with respect to Figures 1 to 4B discussed.

[0107] In some embodiments, outputting a plurality of bits of data elements of the first plurality of data elements comprises outputting a plurality of bits of data elements of the second plurality of data elements in an alternating sequence order. In some embodiments, outputting a plurality of bits of data elements of the second plurality of data elements comprises outputting signal Y, as described above with respect to Figures 1 to 4B discussed.

[0108] In some embodiments, outputting a plurality of bits of a data element of the first and / or second plurality of data elements includes outputting the plurality of bits to one or more multipliers, e.g., as described above with respect to Figures 1 to 4B The multipliers in question are M0 and / or M1.

[0109] At operation 550, in some embodiments, an accumulator is used to output a plurality of bits of a data element of the first plurality of data elements in an alternating sequence order based on an input circuit to perform first and second accumulation operations. In some embodiments, using the accumulator includes using the accumulator as described above with respect to Figures 1 to 4B The accumulator 140 in question.

[0110] In some embodiments, using the accumulator to perform the first accumulation operation includes using a first shifter configured to perform a right shift operation, such as described above with respect to Figure 4A and Figure 4B The shifter SHR is discussed, and performing a second accumulation operation using the accumulator includes using a second shifter configured to perform a left shift operation, such as the shifter SHL.

[0111] In some embodiments, performing a first accumulation operation using the accumulator includes performing a right shift operation while a selection circuit outputs a plurality of bits of data elements of the first plurality of data elements in a first sequence order of an alternating sequence order, the first sequence order being an LSB to MSB sequence order, and performing a second accumulation operation using the accumulator includes performing a left shift operation while the first selection circuit outputs a plurality of bits of data elements of the first plurality of data in a second sequence order of an alternating sequence order, the second sequence order being an MSB to LSB sequence order.

[0112] By performing some or all of the operations of method 500, for example, in the first and second operating modes, bits of consecutive data elements of the input signal are transferred to the multiplier in an alternating sequence order such that adjacent bits of consecutively transferred data elements are the same one of the MSB or the LSB, thereby achieving the benefits discussed above with respect to data sequence circuit 100.

[0113] In some embodiments, a circuit includes: a first data register configured to receive a first signal comprising a first plurality of data elements; a first selection circuit coupled to the first data register; a first counter; a second selection circuit coupled to the first counter; and an inverter coupled between the first counter and the second selection circuit, wherein the first data register is configured to output a plurality of bits of each data element of the first plurality of data elements to the first selection circuit, the first counter and the inverter are configured to generate complementary signals in which sequential data elements have cyclic values ​​that step in opposite directions, the second selection circuit is configured to alternately output each of the complementary signals to the first selection circuit as a first selection signal, and the first selection circuit is configured to output the plurality of bits of the data elements of the first plurality of data elements in an alternating sequential order in response to the first selection signal. In some embodiments, the first counter is configured to generate a first one of the complementary signals comprising the sequential data elements having values ​​that decrease from a highest-numbered bit of each data element in the first plurality of data elements to zero, and the inverter is configured to generate a second one of the complementary signals comprising the sequential data elements having values ​​that increase from zero to a highest-numbered bit of each data element in the first plurality of data elements. In some embodiments, the circuit includes a second counter configured to output a second select signal to a second select circuit, wherein the second select circuit is configured to output a first of the complementary signals as the first select signal in response to the second select signal having a first logic level, and to output a second of the complementary signals as the first select signal in response to the second select signal having a second logic level. In some embodiments, the first select circuit is configured to output a plurality of bits of a data element of the first signal to a multiplier of the CIM circuit, and the second select circuit is configured to output the second select signal to an accumulator of the CIM circuit. In some embodiments, the first counter and the second counter are configured such that the second counter generates the second select signal having a transition between the first logic level and the second logic level in synchronization with the first counter restarting a cycle of the complementary signal values. In some embodiments, the circuit includes: a second data register configured to receive a second signal including a second plurality of data elements; and a third selection circuit coupled to the second data register and configured to receive the first selection signal, the second data register configured to output a plurality of bits of each data element in the second plurality of data elements to the third selection circuit, and the third selection circuit configured to output the plurality of bits of the data elements of the second plurality of data elements in an alternating sequence order in response to the first selection signal. In some embodiments, the first data register includes a plurality of flip-flops configured to sequentially store a corresponding plurality of bits of each data element in the first plurality of data elements. In some embodiments, the plurality of bits of each data element in the first plurality of data elements includes a total of four bits.

[0114] In some embodiments, a memory circuit includes input circuitry including a first selection circuit configured to receive a first selection signal and a first signal including a first plurality of data elements, and first and second counters coupled to a second selection circuit, wherein the first counter and the second counter and the second selection circuit are configured to generate the first selection signal and the second selection signal, a first multiplier coupled to the first selection circuit, an adder coupled to the first multiplier, and an accumulator coupled to the adder and configured to receive the second selection signal. In response to the first selection signal, the first selection circuit is configured to output a plurality of bits of data elements of the first plurality of data elements in an alternating sequence to the first multiplier, and in response to the second selection signal, the accumulator is configured to perform a first accumulation operation and a second accumulation operation based on the plurality of bits of the data elements of the first plurality of data elements outputted in the alternating sequence by the first selection circuit. In some embodiments, the input circuit includes a third selection circuit configured to receive a first selection signal and a second signal including a second plurality of data elements, the memory circuit includes a second multiplier coupled to the adder, the third selection circuit configured to output a plurality of bits of data elements of the second plurality of data elements to the second multiplier in an alternating sequence order in response to the first selection signal, and the accumulator is configured to perform a first accumulation operation and a second accumulation operation further based on the third selection circuit outputting the plurality of bits of data elements of the second plurality of data elements in an alternating sequence order. In some embodiments, the memory circuit includes a storage device configured to store first stored data elements and second stored data elements, wherein the first multiplier is configured to output a first product data element to the adder by multiplying the first stored data element by each bit of the first plurality of data elements, the second multiplier is configured to output a second product data element to the adder by multiplying the second stored data element by each bit of the second plurality of data elements, and the adder is configured to output a partial sum data element to the accumulator by summing the corresponding first and second product data elements. In some embodiments, the adder is configured to further output each of a first bit having a low logic level in the LSB direction of the partial sum data element and a second bit having a low logic level in the MSB direction of the partial sum data element. In some embodiments, the accumulator includes a fourth selection circuit configured to select the partial sum data element to which the first bit is appended in the first accumulation operation and the second bit is appended in the second accumulation operation in response to a second selection signal. In some embodiments, the first counter and the inverter are configured to generate complementary signals in which the sequence data elements have cyclic values ​​that step in opposite directions, the second counter is configured to generate a second selection signal including alternating logic levels, and the second selection circuit is configured to output each of the complementary signals as the first selection signal in response to the second selection signal.In some embodiments, the accumulator includes a first shifter configured to perform a right shift operation and a second shifter configured to perform a left shift operation, wherein the accumulator is configured to couple the first shifter to a first feedback path in a first accumulation operation and to couple the second shifter to a second feedback path in a second accumulation operation. In some embodiments, the accumulator is configured to perform a first accumulation operation including a right shift operation while a first selection circuit outputs a plurality of bits of data elements of a first plurality of data elements in a first sequence order that is an alternating sequence order, the first sequence order being an LSB to MSB sequence order, and to perform a second accumulation operation including a left shift operation while the first selection circuit outputs a plurality of bits of data elements of the first plurality of data elements in a second sequence order that is an alternating sequence order, the second sequence order being an MSB to LSB sequence order.

[0115] In some embodiments, a method of operating a circuit includes: receiving a first signal at an input circuit, the first signal comprising a first plurality of data elements; generating complementary signals in which sequential data elements have cyclic values ​​that step in opposite directions; generating a select signal by alternately selecting each of the complementary signals; and outputting a plurality of bits of data elements of the first plurality of data elements in an alternating sequence order in response to the select signal. In some embodiments, receiving the first signal at the input circuit includes receiving a second signal at the input circuit, the second signal comprising a second plurality of data elements, and outputting the plurality of bits of data elements of the first plurality of data elements includes outputting the plurality of bits of data elements of the second plurality of data elements in an alternating sequence order. In some embodiments, generating the complementary signals includes: using a counter to generate a first complementary signal comprising sequential data elements having values ​​that decrease from a highest-numbered bit of each data element in the first plurality of data elements to zero, and using an inverter to generate a second complementary signal comprising sequential data elements having values ​​that increase from zero to a highest-numbered bit of each data element in the first plurality of data elements. In some embodiments, the method includes using the accumulator to perform a first accumulation operation and a second accumulation operation based on the input circuit outputting a plurality of bits of data elements of the first plurality of data elements in an alternating sequence order.

[0116] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and modifications in the present invention without departing from the spirit and scope of the present invention.

Claims

1. A memory circuit comprising: a first data register configured to receive a first signal comprising a first plurality of data elements; a first selection circuit coupled to the first data register; a first counter; a second selection circuit coupled to the first counter; as well as an inverter coupled between the first counter and the second selection circuit, in the first data register being configured to output a plurality of bits of each data element of the first plurality of data elements to the first selection circuit, The first counter and the inverter are configured to generate complementary signals in which sequence data elements have cycle values ​​that step in opposite directions, The second selection circuit is configured to alternately output each of the complementary signals as a first selection signal to the first selection circuit, and The first selection circuit is configured to output the plurality of bits of the data elements of the first plurality of data elements in an alternating serial order in response to the first selection signal.

2. The memory circuit according to claim 1, wherein The first counter is configured to generate a first one of the complementary signals, the first one of the complementary signals comprising sequence data elements having values ​​counting down to zero from a highest numbered bit of each data element of the first plurality of data elements, and The inverter is configured to generate a second one of the complementary signals, the second one of the complementary signals comprising sequential data elements having values ​​incrementing from zero to a highest numbered bit of each data element of the first plurality of data elements.

3. The memory circuit according to claim 1 , further comprising a second counter configured to output a second selection signal to the second selection circuit, wherein the second selection circuit is configured to: in response to the second selection signal having a first logic level, outputting a first one of the complementary signals as the first selection signal, and In response to the second selection signal having a second logic level, a second one of the complementary signals is output as the first selection signal.

4. The memory circuit according to claim 3, wherein The first selection circuit is configured to output the plurality of bits of the data element of the first signal to a multiplier of an in-memory computation circuit, and The second selection circuit is configured to output the second selection signal to an accumulator of a calculation circuit in the memory.

5. The memory circuit according to claim 3, wherein The first counter and the second counter are configured such that the second counter generating the second select signal having a transition between the first logic level and the second logic level restarts the cycling of the cycle value of the complementary signal in synchronization with the first counter.

6. The memory circuit according to claim 1 , further comprising: a second data register configured to receive a second signal comprising a second plurality of data elements; and a third selection circuit coupled to the second data register and configured to receive the first selection signal, in The second data register is configured to output a plurality of bits of each data element of the second plurality of data elements to the third selection circuit, and The third selection circuit is configured to output the plurality of bits of the data elements of the second plurality of data elements in an alternating serial order in response to the first selection signal.

7. The memory circuit according to claim 1, wherein The first data register includes a plurality of flip-flops configured to sequentially store a corresponding plurality of bits of each data element of the first plurality of data elements.

8. The memory circuit according to claim 1, wherein The plurality of bits of each data element in the first plurality of data elements comprises a total of four bits.

9. A memory circuit comprising: Input circuit, including: a first selection circuit configured to receive a first selection signal and a first signal comprising a first plurality of data elements; and a first counter and a second counter coupled to a second selection circuit, wherein the first counter and the second counter and the second selection circuit are configured to generate the first selection signal and the second selection signal; a first multiplier coupled to the first selection circuit; an adder coupled to the first multiplier; and an accumulator coupled to the adder and configured to receive the second selection signal, in, In response to the first select signal, the first select circuit is configured to output a plurality of bits of the data elements of the first plurality of data elements in an alternating sequence order to the first multiplier, and In response to the second select signal, the accumulator is configured to perform a first accumulation operation and a second accumulation operation based on the first selection circuit outputting the plurality of bits of the data elements of the first plurality of data elements in the alternating sequence.

10. The memory circuit according to claim 9, wherein The input circuit further includes a third selection circuit configured to receive the first selection signal and a second signal including a second plurality of data elements, The memory circuit includes a second multiplier coupled to the adder, In response to the first select signal, the third selection circuit is configured to output a plurality of bits of the data elements of the second plurality of data elements to the second multiplier in the alternating sequence order, and The accumulator is configured to perform the first accumulation operation and the second accumulation operation further based on the third selection circuit outputting the plurality of bits of the data elements of the second plurality of data elements in the alternating sequence order.

11. The memory circuit of claim 10 , further comprising a storage device configured to store the first stored data element and the second stored data element, wherein the first multiplier being configured to output a first product data element to the adder by multiplying the first stored data element by each bit of the first plurality of data elements, The second multiplier is configured to output a second product data element to the adder by multiplying the second stored data element by each bit of the second plurality of data elements, and The adder is configured to output a partial sum data element to the accumulator by summing the corresponding first product data element and the second product data element.

12. The memory circuit according to claim 11, wherein The adder is configured to further output each of a first bit having a low logic level in a least significant bit direction of the partial sum data element and a second bit having a low logic level in a most significant bit direction of the partial sum data element.

13. The memory circuit according to claim 12, wherein: The accumulator includes a fourth selection circuit configured to select the partial sum data element to which the first bit is appended in the first accumulation operation and to which the second bit is appended in the second accumulation operation in response to the second selection signal.

14. The memory circuit according to claim 9, wherein: The first counter and inverter are configured to generate complementary signals in which sequence data elements have cycle values ​​that step in opposite directions, The second counter is configured to generate the second selection signal including alternating logic levels, and The second selection circuit is configured to output each of the complementary signals as the first selection signal in response to the second selection signal.

15. The memory circuit according to claim 9, wherein The accumulator comprises: a first shifter configured to perform a right shift operation; and A second shifter configured to perform a left shift operation, The accumulator is configured to couple the first shifter to a first feedback path in the first accumulation operation and to couple the second shifter to a second feedback path in the second accumulation operation.

16. The memory circuit according to claim 15, wherein The accumulator is configured as: performing a first accumulation operation including a right shift operation while the first selection circuitry outputs the plurality of bits of the data elements of the first plurality of data elements in a first sequence order of the alternating sequence order, the first sequence order being a least significant bit to most significant bit sequence order, and A second accumulate operation including a left shift operation is performed while the first select circuit outputs the plurality of bits of the data elements of the first plurality of data elements in a second sequential order of the alternating sequential order, the second sequential order being a most significant bit to least significant bit sequential order.

17. A method of operating a memory circuit, the method comprising: receiving a first signal at an input circuit, the first signal comprising a first plurality of data elements; generating a complementary signal in which sequence data elements have cyclic values ​​that step in opposite directions; generating a selection signal by alternately selecting each of the complementary signals; and In response to the select signal, a plurality of bits of the data elements of the first plurality of data elements are output in an alternating serial order.

18. The method according to claim 17, wherein Receiving the first signal at the input circuit includes receiving a second signal at the input circuit, the second signal including a second plurality of data elements, and The outputting the plurality of bits of the data elements of the first plurality of data elements includes outputting the plurality of bits of the data elements of the second plurality of data elements in the alternating sequence order.

19. The method according to claim 17, wherein Generating the complementary signal comprises: using a counter to generate a first one of the complementary signals comprising the sequence data elements having values ​​decreasing from a highest numbered bit of each data element of the first plurality of data elements to zero, and An inverter is used to generate a second one of the complementary signals comprising the sequence data elements having values ​​incrementing from zero to a highest numbered bit of each data element of the first plurality of data elements.

20. The method of claim 17, further comprising: A first accumulate operation and a second accumulate operation are performed using an accumulator to output the plurality of bits of the data elements of the first plurality of data elements in the alternating sequence order based on the input circuitry.

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