A reconfigurable ternary content addressable memory cell

Abstract

The application discloses a reconfigurable ternary content addressable memory unit, the memory unit utilizes the combination of three or more than three different states of the ternary content addressable memory and applies different gate control voltages to the memory unit to realize the reconfiguration of the unit, so as to realize the switching and working of the ternary content addressable memory unit between the parallel type and the serial type. The different states of the ternary content addressable memory refer to the states of the flash memory unit whose threshold voltage is controlled to different ranges. The application combines the advantages of the parallel type content addressable memory and the serial type content addressable memory, realizes the reconfigurable content addressable memory at a low area cost, and the array composed of the reconfigurable unit not only can realize the functions of the arrays composed of the above two types, but also provides the possibility of mixing the two types in the same array.

Description

Technical Field

[0001] This invention relates to the field of content-addressable memory, specifically a reconfigurable tri-state content-addressable memory cell. Background Technology

[0002] TCAM (Ternary Content Addressable Memory) is a memory cell structure developed based on CAM (Content Addressable Memory). In applications, the input is connected to the TCAM cell via the data line (DL), and the search line is connected to the gate of the memory cell within the cell. The input is applied to the TCAM in the form of a gate voltage. Simultaneously, each TCAM cell has a small bias voltage applied through the source of the flash memory cell. The main function of currently used TCAM cells is to compare the state represented by the input with the state stored in the TCAM cell, ultimately evaluating the matching degree on the match line (ML) in the form of current magnitude. For a single TCAM cell, if the input matches the state stored in the TCAM cell (i.e., the input matches the TCAM stored state), the TCAM cell is not conducting, and there is no current output on the match line. Conversely, if the states do not match, the TCAM cell is conducting, and there is current output on the match line. Compared to CAM, the main characteristic of TCAM cells is that each bit has an "X" state in addition to the common "0" and "1" states. For the "X" state, a matching output will be obtained regardless of whether the input is "0" or "1". The existence of the "X" state allows the TCAM unit to perform variable-length searches of arbitrary length.

[0003] Currently, TCAM units have two structures: parallel structure and series structure. Figure 1 and Figure 2 Schematic diagrams and coding settings for these two structures are given respectively. Figure 1 a) is a schematic diagram of a parallel TCAM structure; 1b) and 1c) show the input and search input for the stored state under this structure. Figure 2 a) is a schematic diagram of a series-connected TCAM structure. 2b) and 2c) show the input and search input for the stored state under this structure. Here, Vt0 and Vt1 are the threshold voltages of two different states of the flash memory cell, where Vt0 > Vt1. SL This is the bias voltage.

[0004] The parallel TCAM structure, mentioned above, is the mainstream TCAM structure, and its functionality and output format are well-known to most researchers. In this mode, users can evaluate the matching degree of an array by utilizing the current output from the matching line, making it widely applicable in fields such as one-time learning, sparse coding, IP routing, and approximate computation. However, since mismatch is the norm, the energy consumption of this structure is not negligible in large array applications. The main advantage of the series TCAM is that it only outputs current on the matching line during matching; there is no current output during mismatch. Therefore, for operations that only require content matching judgment, this structure can significantly reduce energy consumption. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a reconfigurable three-state content addressable memory cell that combines the advantages of parallel content addressable memory and serial content addressable memory. It provides a reconfigurable content addressable memory with low area cost. The array composed of this reconfigurable cell can not only realize the functions that the array composed of the above two types can originally realize, but also provide the possibility of using the two types in the same array.

[0006] To solve the aforementioned technical problem, the present invention adopts the following technical solution: a reconfigurable tri-state content-addressable memory cell. This memory cell utilizes a combination of three or more different states of the tri-state content-addressable memory and applies different gate control voltages to the control memory cell to achieve cell reconfiguration, thereby achieving the purpose of switching and operating the tri-state content-addressable memory cell between parallel and series functional modes. The different states of the tri-state content-addressable memory refer to the states of flash memory cells where the memory threshold voltage is controlled to different ranges.

[0007] Furthermore, this memory cell includes three tri-state content-addressable memories M1, M2, and M3. The tri-state content-addressable memories M1 and M3 are connected in series, and the series-connected M1 and M3 are connected in parallel with M2. When the memory cell needs to be switched to parallel mode, a voltage V0 is applied to the gate of M3. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down. Vt2 is the threshold voltage corresponding to the X state. V0 acts as an overvoltage to reduce the resistance of M3, thereby reducing the voltage drop across M1 caused by M3, and thus reducing the impact of the presence of M3 on the output of this memory cell. When the memory cell needs to be switched to series mode, a voltage V1 is applied to the gate of M2. V1 is a voltage less than Vt2 that prevents M2 from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M2 is not conducting, thus enabling the memory cell to operate normally in a series structure.

[0008] Furthermore, this memory unit includes four tri-state addressable memories M1, M2, M3, and M4. M1 and M2 are connected in series, and M3 and M4 are connected in series. The series-connected M1 and M2 are connected in parallel with the series-connected M3 and M4. When the memory unit needs to be switched to parallel mode, a voltage V0 is applied to the gates of M2 and M4. V0 is a voltage much greater than Vt2 but not enough to cause M2 and M4 to break down. Vt2 is the threshold voltage corresponding to state X. V0 acts as an overvoltage to reduce the resistance of M2 and M4, thereby reducing the voltage division between M2 and M1 and between M4 and M3. To reduce the impact of the presence of M2 and M4 on the output of this memory cell, when the memory cell needs to be adjusted to series mode, a voltage V1 is applied to the gates of M1, M2 or M3, M4. V1 is a voltage less than Vt2 that prevents the three-state addressable memory from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 and M2 are not conducting, and M3 and M4 connected in series form a series mode. Alternatively, applying V1 ensures that M3 and M4 are not conducting, and M1 and M4 connected in series form a series mode, thereby enabling the memory cell to work normally in a series structure.

[0009] Furthermore, this memory cell includes three tri-state content-addressable memories M1, M2, and M3. The tri-state content-addressable memories M1 and M2 are connected in parallel, and the parallel connection of M1, M2, and M3 is also connected in parallel. When the memory cell needs to be switched to parallel mode, a voltage V0 is applied to the gate of M3. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down. Vt2 is the threshold voltage corresponding to state X. V0 acts as an overvoltage to reduce the resistance of M3, thereby reducing the voltage drop across M1 or M2 caused by M3. This reduces the impact of M3's presence on the output of the memory cell. When the memory cell needs to be switched to series mode, a voltage V1 is applied to the gate of M1 or M2. V1 is a voltage less than Vt2 that prevents M2 from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 or M2 is not conducting. When M1 is not conducting, M2 and M3 are connected in series to form a series mode. When M2 is not conducting, M1 and M3 are connected in series to form a series mode, thus enabling the memory cell to work normally in a series structure.

[0010] Furthermore, the memory cells are implemented in an array by connecting each memory cell in parallel to the same matching line, repeating this operation to obtain multiple matching lines, and connecting multiple matching lines in parallel to obtain a memory cell array.

[0011] Furthermore, at the same time, the application of a single parallel tri-state content-addressable memory array, a single serial tri-state content-addressable memory array, or a combination of both can be realized; at different times, the application of parallel, serial, or hybrid tri-state content-addressable memory arrays can be realized sequentially.

[0012] Furthermore, this memory unit is used for one-time learning, sparse coding, IP routing, and approximate computation.

[0013] Furthermore, this memory unit implements coarse and fine screening in terms of time sequence logic. Coarse screening is implemented using parallel memory units, while fine screening is implemented using serial memory units.

[0014] The beneficial effects of this invention are as follows: This invention provides a reconfigurable tri-state content-addressable memory (NTM) cell that combines the advantages of parallel tri-state NTM cells (which can calculate the number or degree of matching based on the current on the matching line) with the advantages of series tri-state NTM cells (which can greatly reduce circuit power consumption). Users can freely adjust the types of NTM cells in the array as needed to achieve efficient and low-power search and matching.

[0015] This invention enables users to perform coarse and fine screening functions within the same array by switching between parallel tri-state content-addressable memory cells and serial tri-state content-addressable memory cells, thereby achieving array reuse and enabling more efficient searching and matching within a smaller application area.

[0016] This invention utilizes the concept of cell reconfiguration to combine the advantages of parallel content-addressable memory (CNTM) cells and serial CNTM cells into a single CNTM cell, greatly reducing the memory area required to achieve the same function. Attached Figure Description

[0017] Figure 1 a) is a schematic diagram of the parallel TCAM structure, and 1b) and 1c) show the input and search input of the stored state under this structure;

[0018] Figure 2 a) is a schematic diagram of a serial TCAM structure, and 2b) and 2c) show the input and search input of the stored state under this structure;

[0019] Figure 3 These are schematic diagrams of the three reconfigurable TCAMs proposed in this invention;

[0020] Figure 4 a) is Figure 3 a) shows the storage state of the reconfigurable TCAM in parallel operation mode, and b) shows the search input in this mode;

[0021] Figure 5 This is a performance comparison between a reconfigurable TCAM unit and a traditional parallel TCAM unit, verified by simulation in parallel mode.

[0022] Figure 6 a) is Figure 3 6a) shows the storage state of the reconfigurable TCAM in serial operation mode, and 6b) gives the search input in this state;

[0023] Figure 7 This is a performance comparison between a reconfigurable TCAM unit in series mode and a traditional series TCAM unit, verified by simulation. Detailed Implementation

[0024] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0025] Example 1

[0026] This embodiment discloses a reconfigurable tri-state content-addressable memory cell. This memory cell utilizes a combination of three or more different states of the tri-state content-addressable memory and applies different gate control voltages to the control memory cell to achieve cell reconfiguration, thereby achieving the purpose of switching and operating the tri-state content-addressable memory cell between parallel and series functional modes. The different states of the tri-state content-addressable memory refer to the states of flash memory cells where the memory threshold voltage is controlled to different ranges.

[0027] Figure 3 Schematic diagrams of three reconfigurable TCAM structures are given. For example... Figure 3 As shown in a), this memory unit includes three tri-state content addressable memories M1, M2, and M3. The tri-state content addressable memories M1 and M3 are connected in series, and the series-connected M1 and M3 are connected in parallel with M2.

[0028] Figure 4 and Figure 6 They respectively gave Figure 3 The specific operations of the structure proposed in section a) in parallel and series modes are as follows. Here, Vt0, Vt1, and Vt2 are the threshold voltages for three different states of the flash memory, with Vt0 > Vt1 ≫ Vt2. In actual operation, corresponding voltages are applied through DL, CL, and DL' connecting the gates of M1, M2, and M3, respectively. For transistor M3, two different voltages—V0 and V1—are applied according to the different modes required by TCAM. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down, while V1 is a voltage less than Vt2 that prevents M2 from conducting. VSL in the structure is the bias voltage.

[0029] When the reconfigurable content-addressable memory (TCAM) cell needs to be switched to parallel mode, a voltage V0 needs to be applied to the gate of M3. This is to minimize the resistance of M3 with a sufficiently large overdrive voltage, thereby reducing the voltage division of M3 onto M1, and consequently reducing the impact of M3's presence on the output of the reconfigurable TCAM cell. The data stored in the TCAM cell is then determined according to application requirements, referencing... Figure 4 a) Program flash memory cells M1 and M2. During data search, a voltage reference is applied to the gates of M1 and M2. Figure 4 b). Through multiple simulation comparisons, the output performance of the reconfigurable content-addressable memory cell proposed in this invention is basically consistent with that of the traditional parallel content-addressable memory cell. Figure 5 The simulation results show that the outputs of the two are basically the same.

[0030] When switching the reconfigurable content-addressable memory (TCAM) cell to serial mode, a voltage V1 needs to be applied to the gate of M2 to ensure that M2 is not turned on, thus allowing the reconfigurable TCAM cell to operate normally in serial configuration. The data stored in the TCAM cell is determined according to application requirements, referencing... Figure 6 a) Program flash memory cells M1 and M2. During data search, a voltage reference is applied to the gates of M1 and M2. Figure 6 b). Through multiple simulation comparisons, the output performance of the reconfigurable content-addressable memory cell proposed in this invention is basically consistent with that of the traditional serial content-addressable memory cell. Figure 7 The simulation results show that the outputs of the two are basically the same.

[0031] Figure 3 Structure b) is derived from a), and it can further save array area compared to a) when implementing serial TCAM operation. Specifically, the memory cell includes four tri-state content-addressable memories M1, M2, M3, and M4. M1 and M2 are connected in series, M3 and M4 are connected in series, and the series-connected M1 and M2 are connected in parallel with the series-connected M3 and M4. When the memory cell needs to be adjusted to parallel mode, M1 and M3 are data storage units, and their programmed states are determined according to the data to be written. M2 and M4 are control units. A voltage V0 is applied to the gates of M2 and M4. V0 is a voltage much greater than Vt2 but not enough to cause M2 and M4 to break down. Vt2 is the threshold voltage corresponding to the X state. V0 acts as an overvoltage to reduce the resistance of M2 and M4, thereby reducing the voltage division of M2 to M1 and M4 to M3, and thus reducing the impact of the presence of M2 and M4 on the output of this memory cell. This state corresponds to the data and the flash memory cell state. Figure 3 a).

[0032] When it is necessary to switch the memory unit to serial mode, the combination of M1 and M2 and the combination of M3 and M4 can be regarded as two serial TCAM units and applied directly. In this case, this structure is more efficient than... Figure 3 a) This method achieves higher area utilization. Specifically, a voltage V1 is applied to the gates of M1, M2, or M3, M4. V1 is a voltage less than Vt2 that prevents the three-state addressable memory from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 and M2 are not conducting, and M3 and M4, which are connected in series, form a series mode. Alternatively, applying V1 ensures that M3 and M4 are not conducting, and M1 and M4, which are connected in series, form a series mode, thereby enabling the memory cells to operate normally in a series structure.

[0033] Figure 3 c) Compared to a), the only change is that M3 is moved to the original SL, and the power supply changes from CL to SL. While achieving the same function as a), M3 can also be used to shut down the entire TCAM unit, thus reducing power consumption. This structure's series-parallel control and... Figure 3 a) They are completely identical, but when controlled in series mode, M2 can be combined with M1 to form a series TCAM unit, or it can be combined with M2. Therefore, OR and AND logic operations can be implemented through this unit. Figure 3 c) The specific control method of the storage unit is as follows:

[0034] When the memory cell needs to be switched to parallel mode, a voltage V0 is applied to the gate of M3. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down. Vt2 is the threshold voltage corresponding to the X state. V0 acts as an overvoltage to reduce the resistance of M3, thereby reducing the voltage drop of M3 on M1 or M2, and thus reducing the impact of the presence of M3 on the output of this memory cell. When the memory cell needs to be switched to series mode, a voltage V1 is applied to the gate of M1 or M2. V1 is a voltage less than Vt2 that prevents M2 from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 or M2 is not conducting. When M1 is not conducting, M2 and M3 are connected in series to form a series mode. When M2 is not conducting, M1 and M3 are connected in series to form a series mode, thus enabling the memory cell to work normally in a series structure.

[0035] The above describes the control method for a single reconfigurable content-addressable memory (MAP) cell. When this invention is applied to an array, each MAP cell only needs to be connected in parallel to the same matching line to obtain one matching line. For multiple matching lines, simply connect the resulting matching lines in parallel as needed. The method of assembling MAP cells into an array is the same as the method of assembling traditional parallel MAP cells into an array.

[0036] Simultaneously, it is possible to implement a single parallel-type large array of tri-state content-addressable memory, a single serial-type large array of tri-state content-addressable memory, or a hybrid application of both. Alternatively, parallel, serial, or hybrid applications of large arrays of tri-state content-addressable memory can be implemented sequentially at different times.

[0037] The memory unit described in this embodiment can be widely used in one-time learning, sparse coding, IP routing, and approximate computation. It can also be used to implement coarse and fine screening based on temporal logic. Coarse screening is a screening process with relatively broad requirements and can be implemented using parallel TCAM units. Fine screening has more stringent conditions and is generally implemented using serial TCAM units.

[0038] The above description only illustrates the basic principles and preferred embodiments of the present invention. Improvements and substitutions made by those skilled in the art based on the present invention are within the scope of protection of the present invention.

Claims

1. A reconfigurable ternary content addressable memory cell, characterized by: This memory cell utilizes a combination of three or more different states of a three-state addressable memory and applies different gate control voltages to the control memory cell to achieve cell reconfiguration; If a memory cell includes three tri-state addressable memories M1, M2, and M3, the tri-state addressable memories M1 and M3 are connected in series, and the series-connected M1 and M3 are connected in parallel with M2. The cell reconfiguration process is as follows: When the memory cell needs to be switched to parallel mode, a voltage V0 is applied to the gate of M3. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down. Vt2 is the threshold voltage corresponding to state X. V0 acts as an overvoltage to reduce the resistance of M3, thereby reducing the voltage drop of M3 on M1, and thus reducing the impact of the presence of M3 on the output of this memory cell. When the memory cell needs to be switched to series mode, a voltage V1 is applied to the gate of M2. V1 is a voltage less than Vt2 that prevents M2 from conducting. Vt2 is the threshold voltage corresponding to state X. Applying V1 ensures that M2 is not conducting, thus enabling the memory cell to work normally in the series structure.

2. The reconfigurable ternary content addressable memory cell of claim 1, wherein: If a memory cell comprises four tri-state addressable memories M1, M2, M3, and M4, with M1 and M2 connected in series, and M3 and M4 connected in series, and the series-connected M1 and M2 connected in parallel with the series-connected M3 and M4, the cell reconfiguration process is as follows: When the memory cell needs to be switched to parallel mode, a voltage V0 is applied to the gates of both M2 and M4. V0 is a voltage much greater than Vt2 but not enough to cause M2 and M4 to break down. Vt2 is the threshold voltage corresponding to state X. V0 acts as an overvoltage to reduce the resistance of M2 and M4, thereby reducing the voltage drop across M1 from M2 and across M3 from M4. The voltage is applied to reduce the impact of the presence of M2 and M4 on the output of this memory cell. When it is necessary to adjust the memory cell to series mode, a voltage V1 is applied to the gate of M1, M2 or M3 and M4. V1 is a voltage less than Vt2 that makes the three-state addressable memory non-conductive. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 and M2 are not conductive, and M3 and M4 connected in series form a series mode. Alternatively, applying V1 ensures that M3 and M4 are not conductive, and M1 and M4 connected in series form a series mode, thereby enabling the memory cell to work normally in a series structure.

3. The reconfigurable ternary content addressable memory cell of claim 1, wherein: If a memory cell comprises three tri-state addressable memories M1, M2, and M3, and the tri-state addressable memories M1 and M2 are connected in parallel, and then M1, M2, and M3 are connected in parallel, the cell reconfiguration process is as follows: When it is necessary to adjust the memory cell to parallel mode, a voltage V0 is applied to the gate of M3. V0 is a voltage much greater than Vt2 but not enough to cause M3 to break down. Vt2 is the threshold voltage corresponding to state X. V0 acts as an overvoltage to reduce the resistance of M3, thereby reducing the load on M1 or M2 by M3. The voltage is applied to reduce the impact of the presence of M3 on the output of this memory cell. When it is necessary to adjust the memory cell to series mode, a voltage V1 is applied to the gate of M1 or M2. V1 is a voltage less than Vt2 that prevents M2 from conducting. Vt2 is the threshold voltage corresponding to the X state. Applying V1 ensures that M1 or M2 is not conducting. When M1 is not conducting, M2 and M3 are connected in series to form a series mode. When M2 is not conducting, M1 and M3 are connected in series to form a series mode, so that the memory cell works normally in the series structure.

4. The reconfigurable ternary content addressable memory cell of any of claims 1-3, wherein: The implementation of memory cells in an array is as follows: each memory cell is connected in parallel to the same matching line, and this operation is repeated to obtain multiple matching lines. Connecting multiple matching lines in parallel yields a memory cell array.

5. The reconfigurable ternary content addressable memory cell of claim 4, wherein: At the same time, implement the application of a single parallel tri-state content-addressable memory array, a single serial tri-state content-addressable memory array, or a combination of both; at different times, implement parallel, serial, or hybrid tri-state content-addressable memory array applications sequentially.

6. The reconfigurable ternary content addressable memory cell of claim 1, wherein: This memory is used for one-time learning, sparse coding, IP routing, and approximate computation.

7. The reconfigurable ternary content addressable memory cell of claim 1, wherein: This memory unit implements coarse and fine screening based on time sequence logic. Coarse screening is implemented using parallel memory units, while fine screening is implemented using serial memory units.

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