Multilayer Ceramic Capacitors

Abstract

The present invention provides a laminated ceramic capacitor capable of suppressing a decrease in reliability. The laminated ceramic capacitor (1) is a laminated ceramic capacitor in which a plurality of dielectric layers (20) containing ceramic materials and a plurality of internal electrode layers (30) are laminated, a plurality of dielectric columns (30A) are formed on each of the plurality of internal electrode layers (30), and a solid solution layer (30B) in which sulfur is dissolved is formed at the interface between the dielectric columns (30A) and the internal electrode layers (30). Thus, a decrease in the life of the laminated ceramic capacitor (1) can be suppressed, that is, a decrease in reliability can be suppressed.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] A laminated ceramic capacitor is known in which a plurality of dielectric layers and a plurality of internal electrode layers made of ceramic materials are laminated. In such a laminated ceramic capacitor, further miniaturization, higher capacitance, and improved reliability are required. Therefore, attempts have been made to reduce the thickness of the dielectric layer, reduce the thickness of the internal electrode layer, and increase the number of layers laminated.

[0003] Patent Document 1 discloses a problem that short circuit failure occurs between internal electrode layers when the dielectric layer is thinned, and discloses an invention that solves this problem and suppresses a decrease in reliability by including a conductive layer between internal electrode layers.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2013-42110

[0007] However, if the internal electrode layer is thinned, a plurality of through holes (dielectric pillars) are formed in the internal electrode layer. Each of the plurality of through holes fills a portion of the adjacent dielectric layer, so in this application, the through holes formed in the internal electrode layer are referred to as dielectric pillars. In addition, if the internal electrode layer is thinned, the life of the multilayer ceramic capacitor may be reduced, that is, the reliability may be reduced. Summary of the invention

[0008] Problem that the invention aims to solve

[0009] An object of the present invention is to provide a multilayer ceramic capacitor that suppresses a decrease in reliability.

[0010] Technical solutions to solve problems

[0011] As a result of intensive research, the inventors of the present application have obtained the following new insights: that is, if the internal electrode layer is thinned, the electric field strength will increase locally in the dielectric layer due to the spheroidization of the main component metal particles of the internal electrode layer, resulting in a decrease in the life of the multilayer ceramic capacitor, that is, a decrease in reliability. Moreover, as a result of intensive research, the inventors of the present application have obtained the following new insights: that is, by coating the main component metal of the internal electrode layer with S, the spheroidization of the main component metal of the internal electrode layer can be suppressed, and the local increase of the electric field strength can be suppressed in the dielectric layer, as a result, the decrease in the life of the multilayer ceramic capacitor can be suppressed, that is, the decrease in reliability can be suppressed. In this way, if the main component metal of the internal electrode layer is coated with S, a multilayer ceramic capacitor can be obtained, that is, a solid solution layer in which S is dissolved is formed at the interface between the dielectric column formed in the internal electrode layer and the internal electrode layer.

[0012] Therefore, the multilayer ceramic capacitor involved in the present invention is a multilayer ceramic capacitor in which multiple dielectric layers and multiple internal electrode layers containing ceramic materials are stacked, multiple dielectric columns are formed in each of the multiple internal electrode layers, and a dielectric column interface solid solution layer in which S is solid-dissolved is formed at the interface between the dielectric column and the internal electrode layer.

[0013] Effects of the Invention

[0014] According to the present invention, it is possible to suppress a decrease in the reliability of a multilayer ceramic capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a perspective view showing a multilayer ceramic capacitor according to the present embodiment.

[0016] Figure 2 yes Figure 1 FIG. 1 is a cross-sectional view taken along line II-II (LT cross-section) of the multilayer ceramic capacitor shown.

[0017] Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view (WT cross-sectional view) taken along line III-III of the multilayer ceramic capacitor shown.

[0018] Figure 4 yes Figure 2 An enlarged cross-sectional view of the IV portion of the multilayer ceramic capacitor shown.

[0019] Figure 5 yes Figure 4 An example of a photographic image of the internal electrode layer of the V portion of the multilayer ceramic capacitor shown.

[0020] Figure 6 yes Figure 5 An example of an S component image in .

[0021] Description of Reference Numerals

[0022] 1: Multilayer ceramic capacitor;

[0023] 10: laminate;

[0024] 20: dielectric layer;

[0025] 30: internal electrode layer;

[0026] 30A: dielectric column (through hole);

[0027] 30B: solid solution layer (solid solution layer at the interface of dielectric column);

[0028] 30C: solid solution layer (solid solution layer at the interface of dielectric layer);

[0029] 30D: Festival;

[0030] 30BD: the location of the solid solution layer corresponding to the node;

[0031] 31: first internal electrode layer;

[0032] 311: first opposing electrode portion;

[0033] 312: first lead electrode portion;

[0034] 32: second internal electrode layer;

[0035] 321: second opposing electrode portion;

[0036] 322: second lead electrode portion;

[0037] 40: external electrode;

[0038] 41: 1st external electrode;

[0039] 415: first base electrode layer;

[0040] 416: 1st plating layer;

[0041] 42: second external electrode;

[0042] 425: second base electrode layer;

[0043] 426: second plating layer;

[0044] 100: inner layer;

[0045] 101: 1st outer layer;

[0046] 102: 2nd outer part;

[0047] L30: electrode opposing part;

[0048] LG1: 1st end spacer;

[0049] LG2: 2nd end spacer;

[0050] W30: electrode opposing part;

[0051] WG1: 1st lateral spacer;

[0052] WG2: lateral septum 2;

[0053] L: length direction;

[0054] T: stacking direction;

[0055] W: width direction;

[0056] LS1: 1st end face;

[0057] LS2: 2nd end face;

[0058] TS1: 1st main surface;

[0059] TS2: 2nd main surface;

[0060] WS1: side 1;

[0061] WS2: Side 2. DETAILED DESCRIPTION

[0062] Hereinafter, an example of an embodiment of the present invention will be described with reference to the accompanying drawings. In addition, in each figure, the same reference numerals are attached to the same or corresponding parts.

[0063] <Multilayer Ceramic Capacitors>

[0064] Figure 1 1 is a perspective view showing a multilayer ceramic capacitor according to the present embodiment. Figure 2 yes Figure 1 The II-II line cross-sectional view of the multilayer ceramic capacitor shown in FIG. Figure 3 yes Figure 1 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line III-III shown in FIG. Figure 1 to Figure 3 The illustrated multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 . The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0065] exist Figure 1 to Figure 3 The XYZ orthogonal coordinate system is shown. The X direction is the length direction L of the laminated ceramic capacitor 1 and the laminated body 10, the Y direction is the width direction W of the laminated ceramic capacitor 1 and the laminated body 10, and the Z direction is the stacking direction T of the laminated ceramic capacitor 1 and the laminated body 10. Thus, Figure 2The section shown is also called the LT section. Figure 3 The section shown is also referred to as the WT section.

[0066] In addition, the longitudinal direction L, the width direction W, and the stacking direction T are not necessarily necessarily in a mutually orthogonal relationship, and may be in a mutually intersecting relationship.

[0067] The stacked body 10 is substantially in the shape of a rectangular parallelepiped and has a first main surface TS1 and a second main surface TS2 opposing in the stacking direction T, a first side surface WS1 and a second side surface WS2 opposing in the width direction W, and a first end surface LS1 and a second end surface LS2 opposing in the longitudinal direction L.

[0068] It is preferable that the corners and ridges of the laminate 10 are rounded. The corner is a portion where three surfaces of the laminate 10 intersect, and the ridge is a portion where two surfaces of the laminate 10 intersect.

[0069] like Figure 2 as well as Figure 3 As shown, the laminate 10 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 laminated in the lamination direction T. In addition, the laminate 10 includes an inner layer portion 100 in the lamination direction T and a first outer layer portion 101 and a second outer layer portion 102 disposed to sandwich the inner layer portion 100 .

[0070] The inner layer portion 100 includes a part of the plurality of dielectric layers 20 and the plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged to face each other via the dielectric layer 20. The inner layer portion 100 is a portion that generates electrostatic capacitance and substantially functions as a capacitor.

[0071] The first outer layer portion 101 is arranged on the first main surface TS1 side of the stacked body 10, and the second outer layer portion 102 is arranged on the second main surface TS2 side of the stacked body 10. More specifically, the first outer layer portion 101 is arranged between the internal electrode layer 30 closest to the first main surface TS1 among the plurality of internal electrode layers 30 and the first main surface TS1, and the second outer layer portion 102 is arranged between the internal electrode layer 30 closest to the second main surface TS2 among the plurality of internal electrode layers 30 and the second main surface TS2. The first outer layer portion 101 and the second outer layer portion 102 do not include the internal electrode layer 30, and each include a portion other than a portion for the internal layer portion 100 among the plurality of dielectric layers 20. The first outer layer portion 101 and the second outer layer portion 102 are portions that function as protective layers for the internal layer portion 100.

[0072] As the material of the dielectric layer 20, for example, a dielectric ceramic containing BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component can be used. In addition, as the material of the dielectric layer 20, Mn compounds, Fe compounds, Cr compounds, Co compounds, or Ni compounds can also be added as subcomponents.

[0073] More specifically, the dielectric layer 20 includes a plurality of dielectric particles. The dielectric particles are barium titanate-based ceramics such as perovskite compounds containing Ba and Ti. The dielectric particles may also contain at least one of La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu, and Y as a minor component.

[0074] The thickness of the dielectric layer 20 is not particularly limited, but is preferably 0.40 μm or more and 0.50 μm or less, and more preferably 0.40 μm or more and 0.45 μm or less. The number of dielectric layers 20 is not particularly limited, but is preferably 100 or more and 2000 or less, for example. The number of dielectric layers 20 is the sum of the number of dielectric layers in the inner layer and the number of dielectric layers in the outer layer.

[0075] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the stacking direction T of the stacked body 10.

[0076] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0077] The opposing electrode portion 311 and the opposing electrode portion 321 are opposed to each other via the dielectric layer 20 in the stacking direction T of the stacked body 10. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited, and for example, they can be roughly rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and substantially function as capacitors.

[0078] The lead electrode portion 312 extends from the counter electrode portion 311 toward the first end surface LS1 of the stacked body 10 and is exposed at the first end surface LS1. The lead electrode portion 322 extends from the counter electrode portion 321 toward the second end surface LS2 of the stacked body 10 and is exposed at the second end surface LS2. The shapes of the lead electrode portions 312 and 322 are not particularly limited, and may be, for example, substantially rectangular.

[0079] Thus, the first internal electrode layer 31 is connected to the first external electrode 41, and there is a gap between the first internal electrode layer 31 and the second end surface LS2 of the stack 10, that is, between the first internal electrode layer 31 and the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and there is a gap between the second internal electrode layer 32 and the first end surface LS1 of the stack 10, that is, between the second internal electrode layer 32 and the first external electrode 41.

[0080] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. In addition, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, for example, at least one selected from metals such as Cu, Ag, Pd, or Au, or alloys containing at least one of these metals such as Ag-Pd alloy as a main component, and may also contain at least one selected from them as a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may also contain particles of a dielectric having the same composition system as the ceramic contained in the dielectric layer 20 as a component other than the main component. In addition, in this specification, the so-called main component metal is defined as the metal component with the highest weight %.

[0081] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 0.30 μm or more and 0.40 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably, for example, 10 or more and 1000 or less.

[0082] like Figure 3 As shown, the stack 10 has an electrode opposing portion W30 in which the internal electrode layer 30 is opposed in the width direction W, and a first side spacer WG1 and a second side spacer WG2 configured to sandwich the electrode opposing portion W30. The first side spacer WG1 is located between the electrode opposing portion W30 and the first side surface WS1, and the second side spacer WG2 is located between the electrode opposing portion W30 and the second side surface WS2. More specifically, the first side spacer WG1 is located between the end of the first side surface WS1 side of the internal electrode layer 30 and the first side surface WS1, and the second side spacer WG2 is located between the end of the second side surface WS2 side of the internal electrode layer 30 and the second side surface WS2. The first side spacer WG1 and the second side spacer WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side spacer WG1 and the second side spacer WG2 are portions that function as protective layers for the internal electrode layer 30. In addition, the first side spacer WG1 and the second side spacer WG2 are also referred to as W spaces.

[0083] like Figure 2As shown, the laminate 10 has an electrode opposing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 are opposed to each other in the longitudinal direction L, a first end spacer LG1, and a second end spacer LG2. The first end spacer LG1 is located between the electrode opposing portion L30 and the first end surface LS1, and the second end spacer LG2 is located between the electrode opposing portion L30 and the second end surface LS2. More specifically, the first end spacer LG1 is located between the end of the second internal electrode layer 32 on the first end surface LS1 side and the first end surface LS1, and the second end spacer LG2 is located between the end of the first internal electrode layer 31 on the second end surface LS2 side and the second end surface LS2. The first end spacer LG1 does not include the second internal electrode layer 32, but includes the first internal electrode layer 31 and the dielectric layer 20, and the second end spacer LG2 does not include the first internal electrode layer 31, but includes the second internal electrode layer 32 and the dielectric layer 20. The first end spacer LG1 is a portion that functions as an electrode portion extending toward the first end surface LS1 of the first internal electrode layer 31, and the second end spacer LG2 is a portion that functions as an electrode portion extending toward the second end surface LS2 of the second internal electrode layer 32. The first end spacer LG1 and the second end spacer LG2 are also referred to as L-spaces.

[0084] In addition, the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32 are located at the electrode opposing portion L30. In addition, the lead electrode portion 312 of the first internal electrode layer 31 is located at the first end spacer LG1, and the lead electrode portion 322 of the second internal electrode layer 32 is located at the second end spacer LG2.

[0085] The dimensions of the stacked body 10 are not particularly limited, but preferably, for example, the length in the longitudinal direction L is 0.05 mm to 1.00 mm, the width in the width direction W is 0.10 mm to 0.50 mm, and the thickness in the stacking direction T is 0.10 mm to 0.50 mm.

[0086] In addition, as a method for measuring the thickness of the dielectric layer 20 and the internal electrode layer 30, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding with a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the longitudinal direction, and further, may be an average value of the measured values ​​at multiple locations in the stacking direction.

[0087] Similarly, as a method for measuring the thickness of the laminate 10, for example, a method of observing the LT cross section near the center of the width direction of the laminate exposed by grinding, or the WT cross section near the center of the length direction of the laminate exposed by grinding with a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the length direction or the width direction.

[0088] Similarly, as a method for measuring the length of the laminate 10, for example, a method of observing the LT cross section near the center in the width direction of the laminate exposed by grinding with a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at a plurality of locations in the lamination direction.

[0089] Similarly, as a method for measuring the width of the laminate 10, for example, a method of observing the WT cross section near the longitudinal center of the laminate exposed by grinding with a scanning electron microscope can be cited. In addition, each value may be an average value of the measured values ​​at multiple locations in the lamination direction.

[0090] The external electrode 40 includes a first external electrode 41 and a second external electrode 42 .

[0091] The first external electrode 41 is disposed on the first end surface LS1 of the stacked body 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end surface LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2. In addition, the first external electrode 41 may extend from the first end surface LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0092] The second external electrode 42 is arranged on the second end surface LS2 of the stacked body 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may also extend from the second end surface LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2. In addition, the second external electrode 42 may also extend from the second end surface LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0093] The first external electrode 41 includes a first base electrode layer 415 and a first plating layer 416, and the second external electrode 42 includes a second base electrode layer 425 and a second plating layer 426. Alternatively, the first external electrode 41 may be composed of only the first plating layer 416, and the second external electrode 42 may be composed of only the second plating layer 426.

[0094] The first base electrode layer 415 and the second base electrode layer 425 may also be a sintered layer containing metal and glass. As glass, a glass component containing at least one selected from B, Si, Ba, Mg, Al, or Li can be cited. As a specific example, borosilicate glass can be used. As metal, Cu is included as a main component. In addition, as metal, for example, at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys may be included as a main component, and at least one selected from them may be included as a component other than the main component.

[0095] The fired layer is a layer obtained by applying a conductive paste containing metal and glass to the laminate by dipping and firing. In addition, the fired layer may be fired after the internal electrode layer is fired, or may be fired simultaneously with the internal electrode layer. In addition, the fired layer may also be a plurality of layers.

[0096] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be resin layers containing conductive particles and a thermosetting resin. The resin layer may be formed on the above-mentioned fired layer, or may be formed directly on the laminate without forming a fired layer.

[0097] The resin layer is a layer obtained by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing it. In addition, the resin layer can be fired after the internal electrode layer is fired, or it can be fired simultaneously with the internal electrode layer. In addition, the resin layer can also be a plurality of layers.

[0098] The thickness of each of the first foundation electrode layer 415 and the second foundation electrode layer 425 which are fired layers or resin layers is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0099] Alternatively, the first foundation electrode layer 415 and the second foundation electrode layer 425 may be thin film layers of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition and in which metal particles are deposited.

[0100] The first plating layer 416 covers at least a portion of the first base electrode layer 415, and the second plating layer 426 covers at least a portion of the second base electrode layer 425. The first plating layer 416 and the second plating layer 426 include, for example, at least one selected from metals such as Cu, Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys.

[0101] The first plating layer 416 and the second plating layer 426 may each be formed of a plurality of layers. Preferably, the two-layer structure is Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being corroded by the solder when mounting the ceramic electronic component, and the Sn plating layer can improve the wettability of the solder when mounting the ceramic electronic component, thereby facilitating mounting.

[0102] The thickness of each of the first plating layer 416 and the second plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0103] <<Internal electrode layer>>

[0104] Next, the internal electrode layers 30 , that is, the first internal electrode layers 31 and the second internal electrode layers 32 will be further described. Figure 4 yes Figure 2 An enlarged cross-sectional view of the IV portion of the multilayer ceramic capacitor shown. Figure 5 yes Figure 4 An example of a photographic image of the internal electrode layer of the V portion of a multilayer ceramic capacitor is shown. Figure 6 yes Figure 5 An example of an S component image in . Figure 5 The captured images and Figure 6 The method of acquiring the S component image may include, for example, the use of wavelength dispersive X-ray analysis (WDX) or energy dispersive X-ray analysis (EDX) and a scanning electron microscope (SEM) or a transmission electron microscope (TEM).

[0105] For example, by thinning the internal electrode layer 30, Figure 4 As shown, a plurality of through holes 30A penetrating in the stacking direction are formed in each of the internal electrode layers 30, that is, the first internal electrode layer 31 and the second internal electrode layer 32. The through holes 30A are filled with a portion of the adjacent dielectric layers 20 and 20, so in the present application, the through holes formed in the internal electrode layers 30 are referred to as dielectric pillars 30A. In other words, a plurality of dielectric pillars 30A are formed in each of the internal electrode layers 30.

[0106] Here, if the dielectric column 30A is formed in the internal electrode layer 30 , electric field concentration occurs in the dielectric column 30A, and the life of the multilayer ceramic capacitor 1 may be shortened, that is, the reliability may be reduced.

[0107] Regarding this, Figures 4 to 6 As shown, a solid solution layer (dielectric column interface solid solution layer) 30B in which S is segregated and dissolved is formed at the interface between the dielectric column 30A and the internal electrode layer 30. Specifically, a solid solution layer 30B of S is formed at the interface between the internal electrode layer 30 and the dielectric column 30A.

[0108] according to Figure 6 In the dielectric column 30A, a plurality of nodes 30D are formed in the stacking direction T, and S is segregated and dissolved in the nodes 30D. In the solid solution layer 30B at the interface between the dielectric column 30A and the internal electrode layer 30, the S content is also high in the portion 30BD corresponding to the node 30D.

[0109] If a solid solution layer 30B of S is formed at the interface with the dielectric column 30A, the insulation near the edge of the dielectric column 30A where the solid solution layer 30B is formed is improved, and the concentration of the electric field in the dielectric column 30A can be suppressed. Therefore, the reduction in the life of the multilayer ceramic capacitor 1, that is, the reduction in reliability can be suppressed.

[0110] Furthermore, for example, due to the thinning of the dielectric layer 20 , the electric field intensity applied to each layer increases, and the life of the multilayer ceramic capacitor 1 may be shortened, that is, the reliability may be reduced.

[0111] Regarding this, Figure 4 As shown, a solid solution layer (dielectric layer interface solid solution layer) 30C in which S is segregated and dissolved may also be formed at the boundary between the dielectric layer 20 and the internal electrode layer 30. Specifically, a solid solution layer 30C of S may also be formed at the interface between the internal electrode layer 30 and the dielectric layer 20. In addition, the S content in the solid solution layer 30B is higher than the S content in the solid solution layer 30C.

[0112] If a solid solution layer 30C of S is formed at the interface with the dielectric layer 20, the insulation at the interface with the dielectric layer 20 where the solid solution layer 30C is formed is improved, and an increase in electric field intensity can be suppressed in the dielectric layer 20. Therefore, a decrease in the life of the multilayer ceramic capacitor 1, that is, a decrease in reliability can be suppressed.

[0113] Furthermore, S may be segregated and dissolved in the crystal interface of the main component metal Ni in the internal electrode layer 30. For example, as described later, the main component metal Ni may be coated with S in the conductive paste for the internal electrode layer 30.

[0114] By coating the main metal Ni with S, it is possible to suppress the necking of the metal particles Ni of the internal electrode layer 30 generated during degreasing, in other words, to suppress spheroidization, and to improve the smoothness of the internal electrode layer 30. Specifically, it is possible to suppress the local thickening of the internal electrode layer 30 and the local thinning of the dielectric layer 20. Thus, it is possible to suppress the local increase in the electric field intensity in the dielectric layer 20. Therefore, it is possible to suppress the reduction in the life of the multilayer ceramic capacitor 1, that is, it is possible to suppress the reduction in reliability.

[0115] Furthermore, by coating the main component metal Ni with S, the generation of Ni3C can be suppressed during degreasing, and as a result, the volume expansion of the internal electrode layer 30 due to the generation of Ni3C can be suppressed, and structural defects such as cracking of the internal electrode layer 30 and interlayer delamination of the internal electrode layer 30 and the dielectric layer 20 can be prevented. Therefore, the reduction in the life of the multilayer ceramic capacitor 1 can be suppressed, that is, the reduction in reliability can be suppressed.

[0116] The content (molar ratio) of S in the internal electrode layer 30, that is, the total of the content (molar ratio) of S in the solid solution layer 30B at the interface with the dielectric column 30S, the content (molar ratio) of S in the solid solution layer 30C at the interface with the dielectric layer 20, and the content (molar ratio) of S at the crystal interface of Ni, is 0.06 mol% or more and 0.18 mol% or less, preferably 0.10 mol% or more and 0.13 mol% or less, in the central part in the width direction of the internal electrode, relative to 100 mol of the main component metal Ni of the internal electrode layer 30. In addition, the content is 0.4 mol% or more and 0.7 mol% or less, preferably 0.5 mol% or more and 0.6 mol% or less in the region 5 μm inside from the end portion in the width direction of the internal electrode. By making the amount of S near the end portion of the internal electrode larger than the amount of S in the central part in the width direction of the internal electrode, it is possible to effectively prevent peeling near the end portion of the internal electrode.

[0117] If the content of S in the internal electrode layer 30 is less than 0.06 mol%, the main component metal Ni will be necked, in other words, sphericalization will occur, the smoothness of the internal electrode layer 30 will be easily reduced, or structural defects such as interlayer delamination will be easily generated. On the other hand, if the content of S in the internal electrode layer 30 exceeds 0.18 mol%, there is a disadvantage that the coverage of the main component metal Ni of the internal electrode layer 30 is reduced during annealing.

[0118] The content mol% (molar ratio) of S in the internal electrode layer 30 relative to 100 mol of the main component metal Ni can be measured by EDX mapping. The viewing angle is set to about 1000 μm×1000 μm.

[0119] In addition, Sn may be segregated and dissolved in the interface between the internal electrode layer 30 and the dielectric layer 20. Sn may exist in a layered state or may be dispersed. Sn may be dissolved in the internal electrode layer side or in the dielectric layer side. In addition, Sn may be dissolved in the interface of the dielectric particles in the dielectric layer.

[0120] When Sn is segregated and dissolved in the interface between the internal electrode layer 30 and the dielectric layer 20 , the insulation at the interface is improved and an increase in electric field intensity can be suppressed. Therefore, a reduction in the life of the multilayer ceramic capacitor 1 , that is, a reduction in reliability can be suppressed.

[0121] <Manufacturing method>

[0122] Next, a method for manufacturing the above-mentioned laminated ceramic capacitor 1 is described. First, a dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste contains S. For example, a conductive paste containing metal particles Ni whose surfaces are coated with S is used. In addition, Sn may also be contained in the dielectric sheet. In addition, a binder and a solvent are contained in the dielectric sheet and the conductive paste. As the binder and the solvent, known materials can be used.

[0123] Next, conductive paste is printed on the dielectric sheet in a predetermined pattern, for example, to form an internal electrode pattern on the dielectric sheet. Screen printing, gravure printing, or the like can be used as a method for forming the internal electrode pattern.

[0124] Next, a predetermined number of dielectric sheets for the second outer layer 102 without an internal electrode pattern printed thereon are stacked. Dielectric sheets for the inner layer 100 with an internal electrode pattern printed thereon are sequentially stacked. A predetermined number of dielectric sheets for the first outer layer 101 without an internal electrode pattern printed thereon are stacked. Thus, a laminated sheet is produced.

[0125] Next, the laminated sheets are pressed in the stacking direction by isostatic pressing or the like to produce a laminated block. Next, the laminated block is cut into a given size to cut out laminated small pieces. At this time, the corners and ridges of the laminated small pieces are rounded by roller grinding or the like.

[0126] Next, the stacked small pieces are heated and degreased. Although the degreasing temperature depends on the materials of the dielectric layer and the internal electrode layer, a low temperature of about 600° C. is preferred. In addition, the atmosphere is preferably a reducing atmosphere. This makes it easier for S to remain in the internal electrode layer.

[0127] At this time, as described above, by using a conductive paste containing metal particles Ni whose surfaces are coated with S, it is possible to suppress the necking of the metal particles Ni of the internal electrode layer generated during degreasing, in other words, to suppress sphericalization, to improve the smoothness of the internal electrode layer, and to suppress the local increase of the electric field intensity in the dielectric layer. Therefore, it is possible to suppress the reduction of the life of the multilayer ceramic capacitor 1, that is, to suppress the reduction of the reliability.

[0128] Furthermore, as described above, by using a conductive paste containing metal particles Ni whose surfaces are coated with S, the generation of Ni3C can be suppressed during degreasing, and as a result, the volume expansion of the internal electrode layer due to the generation of Ni3C can be suppressed, and structural defects such as cracking of the internal electrode layer and interlayer delamination of the internal electrode layer and the dielectric layer can be prevented. Therefore, the reduction in the life of the multilayer ceramic capacitor 1 can be suppressed, that is, the reduction in reliability can be suppressed.

[0129] Next, the stacked small pieces are fired to produce the stacked body 10. The firing temperature depends on the materials of the dielectric and the internal electrodes, but is preferably 900°C or higher and 1400°C or lower.

[0130] At this time, a plurality of dielectric pillars 30A are formed in the internal electrode layer 30, and a solid solution layer 30B in which S is segregated and dissolved is formed at the interface between the dielectric pillars 30A and the internal electrode layer 30. In addition, a solid solution layer 30C in which S is segregated and dissolved may also be formed between the dielectric layer 20 and the internal electrode layer 30. In addition, S may remain at the crystal interface of the main component metal Ni in the internal electrode layer 30, that is, S may also be segregated and dissolved at the crystal interface. In addition, Sn may also be segregated and dissolved at the interface between the internal electrode layer 30 and the dielectric layer 20.

[0131] Next, the first end surface LS1 of the stacked body 10 is dipped in a conductive paste as an electrode material for the base electrode layer by a dipping method, thereby applying a conductive paste for the first base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the stacked body 10 is dipped in a conductive paste as an electrode material for the base electrode layer by a dipping method, thereby applying a conductive paste for the second base electrode layer 425 to the second end surface LS2. Then, by firing these conductive pastes, the first base electrode layer 415 and the second base electrode layer 425 as fired layers are formed. The firing temperature is preferably 600° C. or higher and 900° C. or lower.

[0132] In addition, as described above, a conductive paste containing conductive particles and a thermosetting resin can be applied by a coating method and fired to form the first base electrode layer 415 and the second base electrode layer 425 as resin layers, or the first base electrode layer 415 and the second base electrode layer 425 can be formed as thin films by a thin film forming method such as sputtering or evaporation.

[0133] Then, the first plating layer 416 is formed on the surface of the first foundation electrode layer 415 to form the first external electrode 41, and the second plating layer 426 is formed on the surface of the second foundation electrode layer 425 to form the second external electrode 42. Through the above steps, the above-mentioned multilayer ceramic capacitor 1 is obtained.

[0134] As described above, according to the multilayer ceramic capacitor 1 of the present embodiment, for example, due to the thinning of the internal electrode layer 30, a plurality of dielectric columns 30A are formed in the internal electrode layer 30, and a solid solution layer 30B in which S is dissolved is formed at the interface between the dielectric column 30A and the internal electrode layer 30. As a result, the insulation is improved near the edge of the dielectric column 30A where the solid solution layer 30B is formed, and the concentration of the electric field in the dielectric column 30A can be suppressed. Therefore, the reduction in the life of the multilayer ceramic capacitor 1 can be suppressed, that is, the reduction in reliability can be suppressed.

[0135] Furthermore, according to the multilayer ceramic capacitor 1 of the present embodiment, a solid solution layer 30C in which S is dissolved may be formed at the interface between the internal electrode layer 30 and the dielectric layer 20. In addition, the content of S in the solid solution layer 30B is higher than the content of S in the solid solution layer 30C. As a result, the insulation is improved at the interface with the dielectric layer 20 where the solid solution layer 30C is formed, and the increase in the electric field intensity caused by, for example, the thinning of the dielectric layer 20 can be suppressed. Therefore, the reduction in the life of the multilayer ceramic capacitor 1 can be suppressed, that is, the reduction in reliability can be suppressed.

[0136] Furthermore, according to the multilayer ceramic capacitor 1 of the present embodiment, S can also be dissolved in the crystal interface of the main component metal Ni of the internal electrode layer 30. For example, in the conductive paste for the internal electrode layer 30, the main component metal Ni can also be coated with S. As a result, the necking of the metal particles Ni of the internal electrode layer 30 generated during degreasing can be suppressed, in other words, sphericalization can be suppressed, the smoothness of the internal electrode layer 30 can be improved, and the local increase of the electric field intensity in the dielectric layer 20 can be suppressed. In addition, the generation of Ni3C can be suppressed during degreasing, and as a result, the volume expansion of the internal electrode layer 30 caused by the generation of Ni3C can be suppressed, and the cracking of the internal electrode layer 30 and the structural defects such as interlayer delamination of the internal electrode layer 30 and the dielectric layer 20 can be prevented. Therefore, the reduction in the life of the multilayer ceramic capacitor 1 can be suppressed, that is, the reduction in reliability can be suppressed.

[0137] The above describes the embodiment of the present invention, but the present invention is not limited to the above embodiment, and various changes and deformations can be made. For example, as a method for manufacturing a laminated ceramic capacitor, the following method can also be applied, that is, a dielectric with side spacing at the side surfaces WS1 and WS2 in the width direction W of the laminate 10 is subsequently given. In this case, the ends of both sides of the internal electrode layer in the width direction W are aligned (for example, aligned with an error of 5 μm).

Claims

1. A laminated ceramic capacitor comprising a plurality of dielectric layers and a plurality of internal electrode layers made of a ceramic material, wherein: A plurality of dielectric pillars are formed on each of the plurality of internal electrode layers, At the interface between the dielectric column and the internal electrode layer, a dielectric column interface solid solution layer in which S is solid-dissolved is formed. At the interface between the internal electrode layer and the dielectric layer, a dielectric layer interface solid solution layer in which S is solid-dissolved is formed. The S content in the dielectric column interface solid solution layer is higher than the S content in the dielectric layer interface solid solution layer.

2. The multilayer ceramic capacitor according to claim 1, wherein Each of the plurality of internal electrode layers contains Ni as a main component, S is dissolved in the crystal interface of Ni.

3. The multilayer ceramic capacitor according to claim 2, wherein: In a widthwise central portion of the multilayer ceramic capacitor, a content of S in the internal electrode layer is 0.06 mol % or more and 0.18 mol % or less relative to 100 mol of Ni in the internal electrode layer.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The thickness of the internal electrode layer is 0.3 μm or more and 0.4 μm or less, The dielectric layer has a thickness of 0.4 μm or more and 0.5 μm or less.

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