Method of reducing erosion of active area shallow trench isolation structure formation and semiconductor structure thereof

Abstract

The present invention provides a method for reducing active area erosion in shallow trench isolation structure formation and a semiconductor structure thereof. A shallow trench isolation structure is formed by two separate shallow trench isolation etching processes. A first STI process forms a first trench having one or more dimensions in a silicon substrate along a first dimension. After a first liner oxide layer is formed around the first trench in a first thermal oxidation process, the first trench is filled with a first dielectric material. A second STI process forms a second trench having one or more dimensions along a second dimension to define an active area separated by the first trench and the second trench filled with the first dielectric material. After a second liner oxide layer is formed around the second trench in a second thermal oxidation process, the second trench is filled with a second dielectric material. Active area erosion caused by the first thermal oxidation and the second thermal oxidation processes is reduced by the two separate STI etching processes.

Description

Technical Field

[0001] This invention relates to semiconductor processes, and more specifically, to a method for forming a shallow trench isolation structure that can reduce the consumption or erosion of the source / drain or active region, and the semiconductor structure thereof. Background Technology

[0002] Shallow trench isolation (STI) structures provide electrical insulation between semiconductor devices. As device sizes continue to shrink, shallow trench isolation technology becomes increasingly important, and also faces more challenges. Figure 1A A top view schematic diagram of a prior art semiconductor substrate structure is shown, and Figure 1B A schematic cross-sectional view of a prior art semiconductor substrate structure along a tangent line I-I' is shown. The prior art semiconductor substrate structure includes a silicon substrate 10 with a plurality of active regions 12, which are separated from each other by a shallow trench isolation structure formed by trenches 14. The active regions 12 are elliptical in shape with rounded corners A, which are caused by silicon ablation. During a thermal oxidation process, a pad oxide layer is formed along the sidewalls and bottom of the trenches 14 before depositing an interlayer oxide dielectric material 16 to fill the trenches 14 and cover the silicon substrate 10. The formation of the pad oxide layer consumes silicon material from the silicon substrate 10 adjacent to the trenches 14, causing the active regions 12 to become elliptical with rounded corners A, thereby reducing the area at both ends of the active regions 12. The active regions 12 can be transistor regions of a semiconductor substrate structure having source / drain electrodes formed at both ends of the active regions 12. Contacts 18 filled with conductive material penetrate the interlayer oxide dielectric material 16 and occupy the source / drain electrodes. Figure 1A and Figure 1B As shown, the silicon etch-off or consumption during the formation of the pad oxide layer of trench 14 creates rounded corners A, reducing the contact area 18a of contact 18 in conventional shallow trench isolation processes. The smaller contact area 18a results in high contact resistance and limits the ability to further miniaturize semiconductor devices.

[0003] The following describes a known method for forming active regions and shallow trench isolation (STI) structures that electrically insulate the active regions from each other. First, a semiconductor substrate structure is provided, comprising a silicon substrate 200 having a silicon oxide layer 202 as a pad oxide, a silicon nitride layer 204, and a photoresist layer or hard mask 206, sequentially stacked on the silicon substrate 200, such as... Figure 2A , Figure 2B and Figure 2C As shown. Figure 2A This is a top view of the semiconductor substrate structure. Figure 2B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 2C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, a shallow trench isolation process is performed to form a linear pattern on the semiconductor substrate structure, such as... Figure 3A , Figure 3B and Figure 3C As shown. Figure 3A This is a top view of the semiconductor substrate structure. Figure 3B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 3C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, active region-cut patterning is performed to form island-shaped active region patterns, such as... Figure 4A , Figure 4B and Figure 4C As shown. Figure 4A This is a top view of the semiconductor substrate structure. Figure 4B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 4C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, a trench etching process is performed to form a shallow trench isolation structure with multiple intersecting trenches 208 in the semiconductor substrate structure, and the photoresist layer or hard mask 206 is removed, as shown below. Figure 5A , Figure 5B and Figure 5C As shown. Figure 5A This is a top view of the semiconductor substrate structure. Figure 5B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 5C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. The shallow trench isolation structure defines active regions 200a and 200b adjacent to each trench 208 in the silicon substrate 200. Active regions 200a and 200b can be field-effect transistors, with their source and drain located at opposite ends of the active regions 200a and 200b, respectively. Subsequently, a thermal oxidation process is performed to form a pad oxide layer 210 along the sidewalls and bottom of the trench 208. During the thermal oxidation process, the rectangular apex corners of active regions 200a and 200b are exposed to or attacked by more oxygen-containing substances than other portions of active regions 200a and 200b; for example, the rectangular apex corners of active regions 200a and 200b are exposed to or attacked by oxygen-containing substances from at least two directions. Therefore, silicon etching is enhanced at the rounded corners of active regions 200a and 200b, resulting in elliptical active regions 200a and 200b with rounded corners A, as shown below. Figure 6A, Figure 6B and Figure 6C As shown. Figure 6A This is a top view of the semiconductor substrate structure. Figure 6B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 6C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, trenches 208 are filled with oxide dielectric material 212, followed by a chemical mechanical polishing (CMP) process to remove excess oxide dielectric material 212, such as... Figure 7A , Figure 7B and Figure 7C As shown. Figure 7A This is a top view of the semiconductor substrate structure. Figure 7B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 7C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, the silicon nitride layer 204 is removed from the semiconductor substrate structure, as shown... Figure 8A , Figure 8B and Figure 8C As shown. Figure 8A This is a top view of the semiconductor substrate structure. Figure 8B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 8C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Due to silicon etch, active regions 200a and 200b become smaller and rounded at their ends. Contacts 216, filled with conductive material, penetrate the oxide dielectric material 214 and occupy each end of active regions 200a and 200b, where each end of active regions 200a and 200b can form the source / drain of a transistor. Due to the silicon etch at the ends of active regions 200a and 200b, the occupied area B of contact 216 decreases, as shown... Figure 9A and Figure 9B As shown. Figure 9A This is a top view of the semiconductor substrate structure. Figure 9B This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Summary of the Invention

[0004] This invention aims to reduce the area reduction of active regions caused by silicon erosion or consumption of active regions during the fabrication of shallow trench isolation structures by using two separate shallow trench isolation etching processes. A first shallow trench isolation etching process is performed to linearly form a first trench having one or more dimensions along a first dimension in a silicon substrate. After a first thermal oxidation process forming a first pad oxide layer along the sidewalls and bottom of the first trench, a first dielectric material is filled into the first trench. A second shallow trench isolation etching process is performed to form a second trench having one or more dimensions along a second dimension in the silicon substrate to define island-shaped active regions having one or more dimensions and spaced apart from each other by the first and second trenches. After a second thermal oxidation process forming a second pad oxide layer along the sidewalls and bottom of the second trench, a second dielectric material is filled into the second trench. By performing two separate shallow trench isolation etching processes at different stages of fabrication of the shallow trench isolation structure, a reduction in silicon erosion or consumption of the active regions of adjacent first and second trenches caused by the first and second thermal oxidation processes is achieved. Therefore, this invention provides an island-shaped active region with fewer rounded corners than conventional shallow trench isolation processes. The ends of the island-shaped active region provide more area for subsequent contact, and the contact occupying the ends of the island-shaped active region reduces contact resistance. The two separate shallow trench isolation etching process parameters can be adjusted independently, providing greater flexibility in the process space for etching selectivity, critical dimension (CD), and pattern density.

[0005] To achieve the above objective, in one embodiment, a method for forming a shallow trench isolation structure to reduce active region etching of a silicon substrate includes: providing a silicon substrate; forming a pad oxide layer on a top surface of the silicon substrate; forming a silicon nitride layer above the pad oxide layer; forming a first pattern above the silicon nitride layer, wherein the first pattern consists of lines arranged in rows along a first dimension, or the first pattern consists of a first sub-pattern and a second sub-pattern, wherein the first sub-pattern consists of lines arranged in rows along a first dimension, and the second sub-pattern includes openings of one or more sizes arranged in rows along the first dimension; using the first pattern as a mask, performing a first trench etching process to form a plurality of first trenches along the first dimension, wherein the plurality of first trenches have one or more sizes; removing the first pattern; and performing a first thermal oxidation process to form the plurality of first trenches. A first pad oxide layer is formed on the sidewalls and bottom of the trenches; the plurality of first trenches are filled with a first dielectric material; a second pattern having a plurality of active-area-defined portions is formed on the silicon substrate, wherein the plurality of active-area-defined portions have one or more dimensions; using the second pattern as a mask, a second trench etching process is performed to form a plurality of second trenches in a second dimension to define a plurality of active areas of the silicon substrate, and the plurality of active areas are separated from each other by the plurality of first trenches and the plurality of second trenches filled with the first dielectric material, wherein the plurality of active areas have one or more dimensions, and the plurality of second trenches have one or more dimensions; a second thermal oxidation process is performed to form a second pad oxide layer on the sidewalls and bottom of the plurality of second trenches; and the plurality of second trenches are filled with a second dielectric material.

[0006] In one embodiment, the shallow ditch isolation structure of this application consists of a first ditch and a second ditch arranged alternately, wherein the size of the first ditch is different from the size of the second ditch.

[0007] In one embodiment, active regions separated from each other by staggered first and second trenches are used to form memory integrated circuit (IC) transistors and logic integrated circuit transistors.

[0008] On the other hand, the present invention provides a semiconductor structure comprising: a silicon substrate; a plurality of first trenches having one or more sizes formed in the silicon substrate along a first dimension, the plurality of first trenches being filled with a first dielectric material; a plurality of second trenches having one or more sizes formed in the silicon substrate along a second dimension, the plurality of second trenches being filled with a second dielectric material; and a plurality of active regions having one or more sizes formed in the silicon substrate, wherein each of the plurality of active regions is a rectangular shape with rounded corners and is spaced apart from each other by the plurality of first trenches filled with the first dielectric material and the plurality of second trenches filled with the second dielectric material. Attached Figure Description

[0009] Other objects and advantages of the invention will become apparent from the following detailed description and with reference to the accompanying drawings, wherein:

[0010] Figure 1A A top view schematic diagram of a prior art semiconductor substrate structure is shown;

[0011] Figure 1B A schematic cross-sectional view of a prior art semiconductor substrate structure along the tangent line I-I' is shown;

[0012] Figures 2A to 9A These are top-view schematic diagrams of the various stages of the conventional semiconductor substrate structure formation method, representing the prior art semiconductor substrate structure.

[0013] Figure 2B Image to Figure 8B For example, the semiconductor substrate of the prior art along Figures 2A to 8A A cross-sectional view of the CC tangent;

[0014] Figures 2C to 8C and Figure 9B For example, the semiconductor substrate of the prior art along Figures 2A to 9A A cross-sectional view of the DD tangent;

[0015] Figures 10A to 20A These are top views of the semiconductor substrate structure at each stage of the semiconductor substrate structure formation method according to the first embodiment of the present invention.

[0016] Figures 10B to 19B respectively along Figures 10A to 19A A cross-sectional schematic diagram of a semiconductor substrate structure with a CC tangent;

[0017] Figures 10C to 19C respectively along Figures 10A to 19A A cross-sectional schematic diagram of a semiconductor substrate structure with a DD tangent;

[0018] Figure 20B For along Figure 20AA cross-sectional schematic diagram of a semiconductor substrate structure with a DD tangent;

[0019] Figures 21A to 21C These are top views of the semiconductor substrate structure at each stage of the method for forming a semiconductor substrate structure according to the second embodiment of the present invention.

[0020] Icon labels:

[0021] 10: Silicon substrate;

[0022] 12: Active region;

[0023] 14: Ditch;

[0024] 16: Interlayer oxide dielectric materials;

[0025] 18: Contact;

[0026] 18a: Area occupied by contact;

[0027] 200: Silicon substrate;

[0028] 200a: Active region;

[0029] 200b: Active region;

[0030] 202: Silicon oxide layer;

[0031] 204: Silicon nitride layer;

[0032] 206: Photoresist layer or hard mask;

[0033] 208: Ditch;

[0034] 210: Gasket oxide layer;

[0035] 212: Oxide dielectric materials;

[0036] 214: Oxide dielectric materials;

[0037] 216: Contact;

[0038] 300: Silicon substrate;

[0039] 300a: Active region;

[0040] 300b: Active region;

[0041] 300c: Active region;

[0042] 302: Silicon oxide layer;

[0043] 304: Silicon nitride layer;

[0044] 306: Photoresist layer or hard mask;

[0045] 307: The First Ditch;

[0046] 308: First gasket oxide layer;

[0047] 310: First dielectric material;

[0048] 312: Second photoresist layer or second hard mask;

[0049] 314: The Second Ditch;

[0050] 318: Contact;

[0051] 320: Second dielectric material;

[0052] 330: Interlayer dielectric material;

[0053] A: Rounded corners;

[0054] B: Area;

[0055] F: Area. Detailed Implementation

[0056] The invention will now be described by way of preferred embodiment with reference to the accompanying drawings. The same reference numerals refer to corresponding portions of the various drawings. Note that known circuits, structures, and techniques may not be listed in detail to avoid obscuring aspects of this disclosure. Various embodiments will be disclosed herein; however, it should be understood that the disclosed embodiments are used only as examples that can be embodied in various forms. Furthermore, each example given connecting the various embodiments is intended as illustrative and not as limiting. Moreover, the drawings in this application are not necessarily to scale, and some features are enlarged to show details of specific devices (and any dimensions, materials, and similar details shown in the drawings are intended as illustrative and not limiting). Therefore, the specific structural and functional details disclosed herein are not to be construed as limiting, but are merely intended to teach those skilled in the art the basis for implementing the disclosed embodiments.

[0057] Figures 10A to 20B The process steps of a shallow trench isolation structure for reducing the etching or consumption of active regions of a semiconductor substrate during the semiconductor process according to a first embodiment of the present invention are described. First, a semiconductor substrate structure comprising a silicon substrate 300 is provided, for example, by sequentially stacking a silicon oxide layer 302, a silicon nitride layer 304, and a photoresist layer or hard mask 306 on the silicon substrate 300 using known methods, such as... Figure 10A , Figure 10B and Figure 10C As shown. Figure 10A This is a top view of the semiconductor substrate structure. Figure 10B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 10CThis is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. The silicon oxide layer 302 can serve as a pad oxide, preventing chemical contamination of the subsequently formed active regions during the subsequent steps of forming the semiconductor substrate structure of the present invention, wherein the active regions are separated from each other by the shallow trench isolation structure of the present invention. The silicon nitride layer 304 can serve as a hard mask to protect the active regions during the deposition of interlayer dielectric material to fill trenches adjacent to the active regions in subsequent process steps. The silicon nitride layer 304 can also serve as a polishing stop layer when a chemical mechanical polishing process is performed to remove excess interlayer dielectric material from the semiconductor substrate structure. Next, a first shallow trench isolation patterning process is performed to form a line pattern on the silicon nitride layer 304. In one embodiment, a first pattern consisting of a plurality of patterned photoresist layers or hard masks 306 in a first dimension is formed on the silicon nitride layer 304, such as... Figure 11A , Figure 11B and Figure 11C As shown. Figure 11A This is a top view of the semiconductor substrate structure. Figure 11B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 11C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, a first trench etching process is performed to form multiple first trenches 307 in the first dimension of the silicon substrate 300, and then the first pattern is removed, as shown below. Figure 12A , Figure 12B and Figure 12C As shown. Figure 12A This is a top view of the semiconductor substrate structure. Figure 12B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 12C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. The etching depth and critical dimension (CD) of the first trench 307 can be adjusted as needed. Next, a first thermal oxidation process is performed to form a first pad oxide layer 308 on the sidewalls and bottom of the first trench 307. In one embodiment, the first thermal oxidation process is performed in an oxidation chamber, wherein the internal environment of the oxidation chamber contains an oxygen-containing substance. During the first thermal oxidation process, only the portion of the silicon substrate 300 defining the sidewalls and bottom of the first trench 307 in the first dimension is exposed to the oxygen-containing substance, while the first pad oxide layer 308 is formed along the sidewalls and bottom of the first trench 307, as shown below. Figure 13A , Figure 13B and Figure 13C As shown. Figure 13A This is a top view of the semiconductor substrate structure. Figure 13B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 13CThis is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Therefore, the silicon etch of the silicon substrate 300 caused by the first thermal oxidation process occurs only in one direction along the first dimension. Please refer to... Figure 14A , Figure 14B and Figure 14C As shown, Figure 14A This is a top view of the semiconductor substrate structure. Figure 14B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 14C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, the first trench 307 is filled with a first dielectric material 310. In one embodiment, the first trench 307 may be filled with an oxide dielectric material, such as silicon dioxide. Silicon dioxide can be deposited in the first trench 307 by chemical vapor deposition (CVD). Next, a first chemical mechanical polishing (CMP) process is performed to remove excess first dielectric material 310, with a silicon nitride layer 304 serving as a polishing stop layer.

[0058] Subsequently, a second photoresist layer or a second hard mask 312 is formed on the silicon nitride layer 304 of the semiconductor substrate structure, such as... Figure 15A , Figure 15B and Figure 15C As shown. Figure 15A This is a top view of the semiconductor substrate structure. Figure 15B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 15C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Next, the second photoresist layer or second hard mask 312 is patterned to form a second pattern as an active-region-defined pattern, so that the active region of the silicon substrate 300 can be diced in subsequent steps, such as... Figure 16A , Figure 16B and Figure 16C As shown. Figure 16A This is a top view of the semiconductor substrate structure. Figure 16B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 16C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. A second trench etching process is performed to form multiple second trenches 314 in a second dimension to define multiple active regions 300a and active regions 300b of the silicon substrate 300, such as... Figure 17A , Figure 17B and Figure 17C As shown. Figure 17A This is a top view of the semiconductor substrate structure. Figure 17B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 17CThis is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. Active regions 300a and 300b are separated from each other by first trenches 307 and second trenches 314 filled with a first dielectric material 310. Next, the second pattern is removed. In one embodiment, the first trenches 307 and second trenches 314 form an interleaved structure to define active regions 300a and 300b, which is beneficial for forming memory integrated circuit (IC) transistors. Note that those skilled in the art will understand that any desired interleaved structure of the first and second trenches suitable for defining the active regions of a logic integrated circuit transistor can be derived from the teachings of this disclosure. The etching depth and critical dimensions of the second trench 314 can be adjusted to differentiate it from the first trench 307. In other words, a shallow trench isolation structure formed by the interleaved first trenches 307 and second trenches 314 can have a first depth defined by the first trench 307 and a second depth different from that defined by the second trench 314. Subsequently, a second thermal oxidation process is performed to form a second liner oxide layer 316 on the sidewalls and bottom of the second trench 314, such as Figure 18A , Figure 18B and Figure 18C As shown. Figure 18A This is a top view of the semiconductor substrate structure. Figure 18B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 18C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. In one embodiment, the second thermal oxidation process is performed in an oxidation chamber, wherein the internal environment of the oxidation chamber contains an oxygen-containing substance. During the second thermal oxidation process, only portions of the silicon substrate 300 defining the sidewalls and bottom of the second trench 314 in the second dimension are exposed to the oxygen-containing substance, while the first trench 307 is filled with a first dielectric material 310, thus preventing the first trench 307 from being exposed to the oxygen-containing substance. The silicon etch of the silicon substrate 300 caused by the second thermal oxidation process occurs only in one direction along the second dimension. Silicon etch will not be as... Figures 2A to 9B The traditional method shown is not as severe. Therefore, active regions 300a and 300b can be obtained with ends larger than the ends of active regions 200a and 200b. In other words, active regions 300a and 300b become rectangular shapes with slightly rounded corners. Active regions 300a and 300b can function as transistors, with their source / drain occupying both ends of active regions 300a and 300b. Figure 9A and Figure 9B Compared to the contact area B of the prior art semiconductor substrate structure shown, the active regions 300a and 300b of the semiconductor substrate structure of the present invention will provide a larger contact area at both ends. See also... Figure 19A , Figure 19B and Figure 19C As shown, Figure 19A This is a top view of the semiconductor substrate structure. Figure 19B This is a schematic cross-sectional view of the semiconductor substrate structure along the CC tangent. Figure 19C This is a schematic cross-sectional view of the semiconductor substrate structure along the DD tangent. The second trench 314 is filled with a second dielectric material 320. In one embodiment, the second trench 314 may be filled with an oxide dielectric material, such as silicon dioxide. Silicon dioxide can be deposited in the second trench 314 by chemical vapor deposition (CVD). Next, a second chemical mechanical polishing process is performed to remove excess second dielectric material 320. Then, the silicon nitride layer 304 is removed.

[0059] Figure 20A This is a top view of the semiconductor substrate structure of the present invention, with contacts occupying active regions 300a and 300b. Figure 20B This is a schematic cross-sectional view of the semiconductor substrate structure of the present invention along the DD tangent, with contacts occupying active regions 300a and 300b. Interlayer dielectric material 330 is deposited on the semiconductor substrate structure. In one embodiment, the interlayer dielectric material 330 may be an oxide dielectric material, such as silicon dioxide. Silicon dioxide can be provided by chemical vapor deposition. Next, a contact opening process is performed to form a plurality of contact openings passing through the interlayer dielectric material 330 and occupying both ends of active regions 300a and 300b. Contact conductive material is deposited in the contact openings to form contacts 318 occupying both ends of active regions 300a and 300b, providing external electrical connection to the source / drain regions occupying both ends of active regions 300a and 300b. This is in contrast to materials manufactured using known methods. Figure 9A and Figure 9B Compared to the prior art semiconductor substrate structure shown, the contact area F at both ends of the active regions 300a and 300b is larger, providing a better process window. The contact 318 can occupy sufficient area at the ends of the active regions 300a and 300b, reducing contact resistance and facilitating further miniaturization of the semiconductor device.

[0060] To increase the design flexibility of the shallow ditch isolation structure of this invention, and at the same time... Figure 9A and Figure 9B Compared to the prior art shown, the contact area occupied by the active region is still increased. According to the second embodiment, as... Figure 21AAs shown, the present invention provides a first pattern comprising a first sub-pattern and a second sub-pattern for forming a first trench. The first sub-pattern consists of lines arranged in rows along a first dimension, and the second sub-pattern includes openings of one or more sizes arranged in rows along the first dimension. The first sub-pattern is formed by a linear photoresist layer or hard mask 306, and the second sub-pattern is formed by a photoresist layer or hard mask 306, having openings that expose portions of a silicon nitride layer 304. (The last sentence appears to be incomplete and possibly refers to a different invention.) Figures 11A to 11C Apart from the first pattern shown, the remaining steps for filling the first trench with the first dielectric material are similar to those in the first embodiment, i.e., forming a first trench 307 filled with the first dielectric material and having one or more dimensions along a first dimension. Furthermore, in the second embodiment, the invention utilizes a second pattern with an active region defining portion having one or more dimensions to define the active region in the silicon substrate, such as... Figure 21B As shown. The second pattern is formed by a patterned photoresist layer or a second hard mask 312, having openings of one or more sizes to expose portions of the silicon nitride layer 304, such that the active region defining portion is separated from the openings of the first trench 307 filled with the first dielectric material and the exposed portion of the silicon nitride layer 304. The remaining steps of forming the second pattern on the silicon substrate are similar to those in the first embodiment. According to the second embodiment, a second trench filled with a second dielectric material and having one or more sizes is provided, and the active regions having one or more sizes are spaced apart from the first trench filled with the first dielectric material and the second trench filled with the second dielectric material.

[0061] Similar to the first embodiment, during the second thermal oxidation process to form a second liner oxide layer on the sidewalls and bottom of the second trench, the active region adjacent to the second trench is exposed to and attacked by oxygen-containing substances only in one direction along the second dimension, while the first trench 307 filled with the first dielectric material protects the active region from oxygen-containing substance attack in the first dimension direction. Therefore, as Figure 21C As shown, according to the second embodiment, an active region 300c with a rectangular shape having one or more dimensions and slightly rounded corners can be obtained. Those skilled in the art will understand that, according to this disclosure, a shallow trench isolation structure in which a first trench with one or more dimensions and a second trench with one or more dimensions are staggered together can be obtained.

[0062] The above embodiments of the present invention are exemplary and are not intended to limit the scope of the invention. Various changes or modifications made without departing from the spirit of the invention to achieve equivalent effects should be included within the scope of the claims of the present invention.

Claims

1. A method for forming a shallow ditch isolation structure to reduce active zone erosion, characterized in that, Include: Provide a silicon substrate; A pad oxide layer is formed on a top surface of the silicon substrate; A silicon nitride layer is formed on top of the pad oxide layer; A first pattern is formed over the silicon nitride layer, wherein the first pattern consists of lines arranged in rows along a first dimension, or the first pattern consists of a first sub-pattern and a second sub-pattern, wherein the first sub-pattern consists of lines arranged in rows along a first dimension, and the second sub-pattern includes one or more openings of different sizes arranged in rows along the first dimension. Using the first pattern as a mask, a first trench etching process is performed to form a plurality of first trenches along the first dimension, wherein the plurality of first trenches have one or more dimensions; Remove the first pattern; A first thermal oxidation process is performed to form a first liner oxide layer on the sidewalls and bottom of the plurality of first trenches; The plurality of first trenches are filled with a first dielectric material; A second pattern having a plurality of active region definition portions is formed on the silicon substrate, wherein the plurality of active region definition portions have one or more dimensions; Using the second pattern as a mask, a second trench etching process is performed to form a plurality of second trenches in a second dimension to define a plurality of active regions of the silicon substrate, and the plurality of active regions are separated from each other by the plurality of first trenches and the plurality of second trenches filled by the first dielectric material, wherein the plurality of active regions have one or more dimensions, and the plurality of second trenches have one or more dimensions. A second thermal oxidation process is performed to form a second liner oxide layer on the sidewalls and bottom of the plurality of second trenches; and The plurality of second trenches are filled with a second dielectric material.

2. The method as described in claim 1, characterized in that, The step of the second trench etching process is to form a second trench with a different size than the first trench.

3. The method as described in claim 1, characterized in that, The second trench etching process involves forming a plurality of second trenches that intersect with the plurality of first trenches to define active regions for forming memory integrated circuit transistors.

4. The method as described in claim 1, characterized in that, The second trench etching process involves forming a plurality of second trenches that intersect with the plurality of first trenches to define the active regions for forming logic integrated circuit transistors.

5. The method as described in claim 1, characterized in that, The first pattern is formed by a first photoresist layer or a first hard mask.

6. The method as described in claim 1, characterized in that, The first thermal oxidation process is carried out in an oxidation chamber, wherein the internal environment of the oxidation chamber contains an oxygen-containing substance.

7. The method as described in claim 1, characterized in that, The first dielectric material is an oxide dielectric material.

8. The method as described in claim 1, characterized in that, It further includes performing a first chemical mechanical polishing process, followed by the step of filling the plurality of first trenches with a first dielectric material.

9. The method as described in claim 1, characterized in that, The second pattern is formed by a second photoresist layer or a second hard mask.

10. The method as described in claim 1, characterized in that, The second thermal oxidation process is carried out in an oxidation chamber, wherein the internal environment of the oxidation chamber contains an oxygen-containing substance.

11. The method as described in claim 1, characterized in that, The second dielectric material is an oxide dielectric material.

12. The method as described in claim 1, characterized in that, It further includes performing a second mechanical polishing process, following the step of filling the plurality of second trenches with a second dielectric material.

13. A semiconductor structure, characterized in that, Include: A silicon substrate; A plurality of first trenches having one or more sizes are formed in the silicon substrate along a first dimension, the plurality of first trenches having one or more sizes being filled with a first dielectric material; A plurality of second trenches having one or more dimensions are formed in the silicon substrate along a second dimension perpendicular to the first dimension, and the plurality of second trenches having one or more dimensions are filled with a second dielectric material; as well as Multiple active regions having one or more dimensions are formed in the silicon substrate, wherein each of the multiple active regions having one or more dimensions is a rectangular shape with rounded corners and is separated from each other by multiple first trenches having one or more dimensions filled with the first dielectric material and multiple second trenches having one or more dimensions filled with the second dielectric material.

14. The semiconductor structure as described in claim 13, characterized in that, The dimensions of the first ditch are different from those of the second ditch.

15. The semiconductor structure as described in claim 13, characterized in that, The multiple first ditches and the multiple second ditches are interspersed.

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