Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure, the method comprising: providing a substrate comprising a substrate and a fin structure; performing one or more deep-width ratio adjustment processes to form a first dummy gate layer on the top and sidewall of the exposed fin structure, the first dummy gate layer on opposite sidewalls of the fin structure enclosing a V-shaped groove; the deep-width ratio adjustment process comprising: forming a dummy gate film on the top and sidewall of the exposed fin structure, the dummy gate film on opposite sidewalls of the fin structure having a gap therebetween; performing an oxidation process on the dummy gate film, adapted to convert part of the thickness of the dummy gate film into an oxide layer; removing the oxide layer; forming a second dummy gate layer on the first dummy gate layer to fill the V-shaped groove, the second dummy gate layer and the first dummy gate layer forming a dummy gate structure, the dummy gate structure spanning the fin structure. The embodiments of the present application improve the filling performance of the dummy gate structure between adjacent fin structures and the film forming quality of the dummy gate structure by changing the method of adjusting the deep-width ratio of the dummy gate film.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. BACKGROUND

[0002] For many years, field effect transistors (FETs) have been the dominant semiconductor technology for the fabrication of application specific integrated circuit (ASIC) chips, microprocessor chips, static random access memory (SRAM) chips, and the like. In particular, complementary metal oxide semiconductor (CMOS) technology has dominated the semiconductor industry.

[0003] In semiconductor manufacturing, with the development trend of very large scale integrated circuits, the feature size of integrated circuits continues to decrease, and in order to adapt to smaller feature sizes, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (FinFETs) and gate-all-around (GAA) transistors.

[0004] The structure of a fin field effect transistor generally includes a plurality of discrete fins formed on a substrate. During the formation of a fin field effect transistor, a dummy gate structure needs to be formed between fins and between fin portions, which is used to occupy a spatial position for forming a device gate.

[0005] However, the performance of the semiconductor device formed at present needs to be improved. SUMMARY

[0006] The problem solved by embodiments of the present application is to provide a method for forming a semiconductor structure, which is beneficial to improve the performance of a semiconductor device.

[0007] To solve the above problems, embodiments of the present application provide a method for forming a semiconductor structure, including: providing a substrate including a substrate and a plurality of discrete fin structures on the substrate, the fin structures being used to provide channels; performing one or more aspect ratio adjustment processes to form a first dummy gate layer on the exposed top and sidewall of the fin structure, the first dummy gate layer on the opposite sidewall of the fin structure forming a V-shaped groove; the aspect ratio adjustment process includes: forming a dummy gate film on the exposed top and sidewall of the fin structure, the dummy gate film between the opposite sidewalls of the fin structure having a gap; performing an oxidation process on the dummy gate film, which is adapted to convert part of the thickness of the dummy gate film into an oxide layer; removing the oxide layer; forming a second dummy gate layer on the first dummy gate layer, the second dummy gate layer filling the V-shaped groove, the second dummy gate layer and the first dummy gate layer forming a dummy gate structure, the dummy gate structure spanning the fin structure.

[0008] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:

[0009] The forming method of the semiconductor structure provided by the embodiment of the application comprises one or more deep-width ratio adjustment processes, and a first dummy gate layer is formed, and the deep-width ratio adjustment process comprises: forming a dummy gate film on the exposed top and sidewall of the fin structure, and the dummy gate film on the opposite sidewalls of the fin structure has a gap; performing an oxidation process on the dummy gate film, and part of the thickness of the dummy gate film is converted into an oxide layer; and removing the oxide layer. In the semiconductor field, the material of the dummy gate film usually contains dangling bonds, and in the deep-width ratio adjustment process, the dangling bonds in the dummy gate film can be fixed by performing the oxidation process on the dummy gate film, which is beneficial to reducing the probability of atomic group aggregation caused by the dangling bonds, and accordingly reducing the generation of holes in the first dummy gate layer caused by the aggregated atomic groups blocking the openings between adjacent fin structures, and further reducing the probability of defects such as the generation of holes in the dummy gate structure, and improving the filling performance of the dummy gate structure between adjacent fin structures and the film forming quality of the dummy gate structure. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1 to 4 FIG. 1 is a structure diagram corresponding to each step in a forming method of a semiconductor structure;

[0011] Figures 5 to 10 FIG. 2 is a structure diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure. DETAILED DESCRIPTION

[0012] The current formed device still has the problem of poor performance. Taking a fin field effect transistor as an example, the reason for the poor performance of the device is analyzed in combination with a forming method of a semiconductor structure.

[0013] Reference Figures 1 to 4 FIG. 1 shows a structure diagram corresponding to each step in a forming method of a semiconductor structure.

[0014] Reference Figure 1 A substrate is provided, including a substrate 7 and a plurality of fin portions 1 which are separated on the substrate 7; an isolation film 2 is formed on the substrate 7 to surround part of the sidewalls of the fin portions 1; and a dummy gate oxide layer 6 is formed on the top and sidewall of the fin portion 1 exposed by the isolation film 2.

[0015] Reference Figures 2 to 3 One or more deposition and etching processes are performed to form a first dummy gate layer 4 on the exposed top and sidewall of the fin portion 1, and the first dummy gate layer 4 on the opposite sidewalls of the fin portion 1 has a gap.

[0016] Specifically, the deposition and etching process comprises:

[0017] like Figure 2 As shown, a dummy gate film 3 is formed on the top and sidewalls of the fin 1. Specifically, the dummy gate film 3 is located on the dummy gate oxide layer 6. In the semiconductor field, the material of the dummy gate film 3 is typically amorphous silicon.

[0018] like Figure 3 As shown, the pseudo-gate film 3 of a certain thickness is etched using etching gas.

[0019] refer to Figure 4 A second pseudo-gate layer 5 is formed on the first pseudo-gate layer 4 to fill the gap. The second pseudo-gate layer 5 and the first pseudo-gate layer 4 constitute a pseudo-gate structure 8. The pseudo-gate structure 8 spans the fin 1 and covers part of the top and part of the sidewall of the fin 1.

[0020] In the semiconductor field, the material of the dummy gate film 3 is usually amorphous silicon. Amorphous silicon is an unstable thin film containing hydrogen and has a large number of dangling bonds on its surface. During the deposition and etching process, when etching the dummy gate film 3, a large number of dangling bonds are generated on the surface of the dummy gate film 3. These dangling bonds can easily induce silicon atom migration, causing silicon atoms to aggregate on the surface of the dummy gate film 3. The aggregated atomic clusters can easily block the openings between adjacent fins 1, resulting in the formation of holes in the first dummy gate layer 4. Consequently, the filling performance of the first dummy gate layer 4 between adjacent fins 1 is poor, and the film formation quality of the first dummy gate layer 4 is not good.

[0021] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of discrete fin structures located on the substrate, the fin structures being used to provide channels; performing one or more aspect ratio adjustment processes to form a first dummy gate layer on the exposed top and sidewalls of the fin structures, the first dummy gate layer located on opposite sidewalls of the fin structures forming a V-shaped trench; the aspect ratio adjustment process comprising: forming a dummy gate film on the exposed top and sidewalls of the fin structures, the dummy gate films located on opposite sidewalls of the fin structures having gaps between them; oxidizing the dummy gate film to convert a portion of the dummy gate film into an oxide layer; removing the oxide layer; forming a second dummy gate layer on the first dummy gate layer filling the V-shaped trench, the second dummy gate layer and the first dummy gate layer constituting a dummy gate structure, the dummy gate structure spanning the fin structures.

[0022] In the semiconductor structure formation method provided by this invention, one or more aspect ratio adjustment processes are performed to form a first dummy gate layer. The aspect ratio adjustment process includes: forming a dummy gate film on the exposed top and sidewalls of the fin structure, with gaps between the dummy gate films located on opposite sidewalls of the fin structure; oxidizing the dummy gate film to convert a portion of the dummy gate film into an oxide layer; and removing the oxide layer. In the semiconductor field, the material of the dummy gate film typically contains dangling bonds. In the aspect ratio adjustment process, by oxidizing the dummy gate film, the dangling bonds in the dummy gate film can be fixed, which helps to reduce the probability of atomic aggregation caused by dangling bonds. This reduces the likelihood of aggregated atomic clusters blocking the openings between adjacent fin structures, thus reducing the generation of holes in the first dummy gate layer. Consequently, it reduces the probability of defects such as holes in the dummy gate structure, improves the filling performance of the dummy gate structure between adjacent fin structures, and enhances the film formation quality of the dummy gate structure.

[0023] Figures 5 to 10 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0024] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0025] refer to Figure 5 The substrate is provided, including a substrate 10 and a plurality of discrete fin structures 11 located on the substrate 10, the fin structures 11 being used to provide channels.

[0026] The substrate is used to provide a process platform for forming semiconductor structures.

[0027] In this embodiment, the substrate 10 is a silicon substrate, that is, the material of the substrate 10 is single-crystal silicon. In other embodiments, the material of the substrate 10 may also be one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride. The substrate 10 may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0028] The fin structure 11 is used to provide a conductive channel for the field-effect transistor.

[0029] In this embodiment, the formation of a fin field-effect transistor (FinFET) is used as an example for explanation. The fin structure 11 is a fin (not shown in the figure). The fin is used to provide the conductive channel of the fin field-effect transistor.

[0030] In the semiconductor field, the sidewalls of the fin structure 11 are usually not perpendicular to the substrate 10. Along the extension direction perpendicular to the fin structure 11, the cross-section of the fin structure 11 is usually trapezoidal. That is, along the direction perpendicular to the substrate 10, the closer to the substrate 10, the larger the linewidth of the fin structure 11, and the smaller the opening linewidth between adjacent fin structures 11.

[0031] In this embodiment, the fin and the substrate 10 are an integral structure, and the material of the fin is the same as that of the substrate 10, which is silicon. In other embodiments, the material of the fin may be different from that of the substrate 10. The material of the fin may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0032] In other embodiments, other types of transistors may be formed, such as gate-all-around (GAA) transistors. When forming a gate-all-around transistor, the fin structure 11 includes protrusions on a substrate and one or more channel stacks on the protrusions, each channel stack including a sacrificial layer and a channel layer on the sacrificial layer.

[0033] The protrusions serve to support the channel stack and provide space for the subsequent formation of the isolation layer 12. As an example, the protrusions and the substrate 10 are integrally formed, and the material of the protrusions is the same as that of the substrate 10, which is silicon. In other embodiments, the material of the protrusions may differ from that of the substrate 10; the material of the protrusions may be other suitable materials, such as one or more of germanium, silicon germanide, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0034] The channel stack provides the technological basis for the subsequent formation of the channel layer with suspended spacing. Specifically, the channel layer is used to provide a conductive channel that fully surrounds the gate transistor, and the sacrificial layer is used to support the channel layer, thereby providing the technological basis for the subsequent realization of the suspended spacing of the channel layer. The sacrificial layer is also used to occupy space for the subsequent formation of the device gate structure.

[0035] When forming an NMOS transistor, the channel layer is made of Si, and the sacrificial layer is made of SiGe. During the subsequent removal of the sacrificial layer, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the sacrificial layer material to SiGe and the channel layer material to Si, the impact of the sacrificial layer removal process on the channel layer can be effectively reduced, thereby improving the quality of the channel layer and ultimately enhancing device performance.

[0036] When forming a PMOS transistor, SiGe channel technology can be used to improve its performance. The channel layer is made of SiGe, and the sacrificial layer is made of Si. In other embodiments, the channel layer material can also be one or more of germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium nitride.

[0037] Continue to refer to Figure 5 In this embodiment, the method for forming the semiconductor structure further includes: forming an isolation layer 12 surrounding the fin structure 11 on the substrate 10, wherein the top surface of the isolation layer 12 is lower than the top surface of the fin structure 11.

[0038] The isolation layer 12 is used to achieve isolation between the fin structures 11, and the isolation layer 12 is also used to isolate the substrate 10 from the subsequently formed device gate structure.

[0039] In this embodiment, the material of the isolation layer 12 is silicon oxide. Silicon oxide is a commonly used and low-cost dielectric material with high process compatibility, which helps to reduce the process difficulty and cost of forming the isolation layer 12. In addition, silicon oxide has a low dielectric constant, which also helps to improve the function of the subsequent isolation layer 12 in isolating adjacent fin structures 11. In other embodiments, the material of the isolation layer 12 may also be silicon nitride, silicon oxynitride, or other insulating materials.

[0040] Specifically, the step of forming the isolation layer 12 includes: forming an isolation material layer (not shown) on the substrate 10, the isolation material layer filling between adjacent fin structures 11 and covering the top of the fin structures 11; removing a portion of the isolation material layer to expose a portion of the sidewalls of the fin structures 11, the remaining isolation material layer serving as the isolation layer 12. In this embodiment, a flowable chemical vapor deposition (FCVD) process is used to form the isolation material layer. The FCVD process has good filling capability and is suitable for filling openings with high aspect ratios, which helps reduce the probability of forming defects such as voids within the isolation material layer, thereby improving the film quality of the isolation layer 12.

[0041] In this embodiment, chemical mechanical polishing and etching processes are used sequentially to remove a portion of the isolation material layer, which helps to improve the removal efficiency of the isolation material layer while also improving the uniformity of the top surface height of the isolation layer 12.

[0042] Continue to refer to Figure 5 A pseudo-gate oxide layer 13 is formed on the top and sidewalls of the fin structure 11 exposed by the isolation layer 12.

[0043] The dummy gate oxide layer 13 is used to isolate the fin structure 11 from the subsequently formed dummy gate structure. Furthermore, in the subsequent step of removing the dummy gate structure, the dummy gate oxide layer 13 also serves as an etching stop layer, reducing the probability of damage to the fin structure 11 caused by the dummy gate structure removal process. In this embodiment, the material of the dummy gate oxide layer 13 is silicon oxide or silicon oxynitride.

[0044] refer to Figures 6 to 8 One or more aspect ratio adjustments are performed to form a first pseudo-gate layer 14 on the top and sidewalls of the exposed fin structure 11. The first pseudo-gate layer 14 located on the opposite sidewalls of the fin structure 11 forms a V-shaped groove 16.

[0045] The aspect ratio adjustment process includes: forming a pseudo-gate film 15 on the exposed top and sidewalls of the fin structure 11, with gaps between the pseudo-gate films 15 located on opposite sidewalls of the fin structure 11; oxidizing the pseudo-gate film 15 to convert a portion of the pseudo-gate film 15 into an oxide layer 18; and removing the oxide layer 18.

[0046] The first dummy gate layer 14 provides a process basis for the subsequent formation of the dummy gate structure. Specifically, the first dummy gate layer 14 is formed on the top and sidewalls of the fin structure 11 exposed by the isolation layer 12. More specifically, the first dummy gate layer 14 is formed on the dummy gate oxide layer 13 on the top and sidewalls of the fin structure 11.

[0047] In this embodiment, the first dummy gate layer 14 is made of amorphous silicon. Amorphous silicon is an unstable thin film containing hydrogen with a large number of dangling bonds on its surface.

[0048] In other embodiments, the material of the first dummy gate layer may also be polycrystalline silicon. The surface of polycrystalline silicon also has dangling bonds.

[0049] Specifically, the aspect ratio adjustment process can reduce the formation of holes in the first pseudo-gate layer 14 caused by clustered atomic groups blocking the openings between adjacent fin structures 11. This reduces the probability of defects such as holes in the first pseudo-gate layer 14, providing a process basis for improving the filling performance of the pseudo-gate structure between adjacent fin structures 11 and the film formation quality of the pseudo-gate structure.

[0050] The aspect ratio adjustment process is used to form the first pseudo-gate layer 14, and the first pseudo-gate layer 14 located on the opposite sidewall of the fin structure 11 forms a V-shaped groove 16. The top opening of the V-shaped groove 16 is wider and the bottom opening is narrower, thereby adjusting the aspect ratio of the groove (i.e. the V-shaped groove 16) formed between adjacent fin structures 11, so as to reduce the difficulty of forming the subsequent second pseudo-gate layer between adjacent fin structures 11.

[0051] In this embodiment, the aspect ratio refers to the ratio of the depth of the V-groove 16 to the top opening of the V-groove 16.

[0052] It should be noted that the aspect ratio should not be too large, otherwise the top opening size of the V-shaped trench 16 may be too small. During the subsequent formation of the second pseudo-gate layer 17, it will be more difficult for the material of the second pseudo-gate layer 17 to fill the V-shaped trench 16, increasing the probability of voids forming in the second pseudo-gate layer 17. Therefore, in this embodiment, the aspect ratio of the V-shaped trench 16 is less than or equal to 10:1.

[0053] In specific implementations, the depth-to-width ratio of the V-shaped groove 16 can be from 2:1 to 10:1, for example: 8:1, 6:1, 4:1, etc.

[0054] The following detailed description of the aspect ratio adjustment process in this embodiment, in conjunction with the accompanying drawings, provides a clear explanation of the steps involved.

[0055] like Figure 6 As shown, a pseudo-gate film 15 is formed on the top and sidewalls of the exposed fin structure 11, and there is a gap 21 between the pseudo-gate films 15 located on opposite sidewalls of the fin structure 11.

[0056] The pseudo gate film 15 provides a process basis for subsequent oxidation treatment, and the pseudo gate film 15 is also used to form the first pseudo gate layer 17.

[0057] In this embodiment, there is a gap between the pseudo-gate films 15 located on opposite sidewalls of the fin structure 11, so that the gap 21 can expose the sidewall surface of the pseudo-gate film 15 of the adjacent fin structure 11 along the extension direction perpendicular to the fin structure 11, and the sidewall surface of the pseudo-gate film 15 on opposite sidewalls of the fin structure 11 can be oxidized during the subsequent oxidation process of the pseudo-gate film 15.

[0058] In this embodiment, the fin structure 11 is typically a trapezoidal structure along the extension direction perpendicular to the fin structure 11, and the opening formed between adjacent fin structures 11 is typically an inverted trapezoidal structure. Therefore, the gap 21 formed between the pseudo-gate films 15 located on opposite sidewalls of the fin structure 11 is typically a V-shaped gap. That is, along the direction perpendicular to the substrate 10, the closer to the substrate 10, the smaller the opening size of the gap 21.

[0059] In this embodiment, the dummy gate film 15 is made of amorphous silicon. In other embodiments, the dummy gate film may also be made of polycrystalline silicon.

[0060] It should be noted that the thickness of the dummy gate film 15 should not be too small or too large. If the thickness of the dummy gate film 15 is too small, it is easy to over-oxidize during the subsequent oxidation process, resulting in a thinner remaining dummy gate film 15 after oxidation. Consequently, the number of cycles required for subsequent aspect ratio adjustment increases, which can increase the process flow and cost. If the thickness of the dummy gate film 15 is too large, it can increase the probability of voids forming within the dummy gate film 15, reducing the film quality. It can also cause dummy gate films 15 located on the sidewalls of adjacent fin structures 11 to come into contact, making it difficult to form the gap 21. Furthermore, it can be difficult to oxidize the exposed sidewall surface of the dummy gate film 15 through the gap 21. Therefore, in this embodiment, the thickness of the dummy gate film 15 is 1 nm to 10 nm, for example: 1 nm, 2 nm, 3 nm, 4 nm, etc.

[0061] In this embodiment, the dummy gate film 15 is formed using chemical vapor deposition (CVD). CVD offers good step coverage, high process maturity, and ease of mass production, which helps improve the film quality of the dummy gate film 15 and saves on process costs.

[0062] In other embodiments, other suitable processes can be used to form the pseudo-gate film, such as atomic layer deposition (ALD).

[0063] like Figure 7 As shown, the pseudo-gate film 15 is oxidized to convert a portion of the pseudo-gate film 15 into an oxide layer 18. Oxidizing the pseudo-gate film 15 fixes the dangling bonds within it, thereby suppressing atomic migration on the surface of the pseudo-gate film 15 and reducing the probability of atomic aggregation caused by dangling bonds.

[0064] During the oxidation process of the pseudo-gate film 15, due to the smaller size of the gap 21, it is more difficult to oxidize the sidewall surface of the pseudo-gate film 15 exposed by the gap 21 compared to the pseudo-gate film 15 located at the top of the fin structure 11 and at the top corner of the fin structure 11. Therefore, the pseudo-gate film 15 located at the top of the fin structure 11 and at the top corner of the fin structure 11 is oxidized at a faster rate, and the resulting oxide layer 18 is thicker.

[0065] Accordingly, after the oxidation treatment, compared with before the oxidation treatment, the difference between the top opening size of the gap 21 formed between the pseudo-gate films 15 on the opposite sidewalls of the fin structure 11 and the bottom opening size of the gap 21 is greater, thereby playing the role of adjusting the aspect ratio.

[0066] Specifically, in the step of forming the pseudo-gate film 15, the thickness of the pseudo-gate film 15 is a first thickness; in the step of oxidizing the pseudo-gate film 15, the oxidized thickness of the pseudo-gate film 15 located on the top of the fin structure 11 is a second thickness.

[0067] It should be noted that the proportion of the second thickness to the first thickness should not be too small or too large. If the proportion of the second thickness to the first thickness is too small, the oxidized thickness of the dummy gate film 15 will be too small, and the effect on aspect ratio adjustment will be insignificant. If the proportion of the second thickness to the first thickness is too large, the dummy gate film 15 will be completely oxidized, causing the formed oxide layer 18 and the dummy gate oxide layer 13 to come into contact. This increases the risk of damage to the dummy gate oxide layer 13 during subsequent removal of the oxide layer 18. Therefore, in this embodiment, the proportion of the second thickness to the first thickness is 50% to 80%.

[0068] In this embodiment, the step of forming the oxide layer 18 includes: oxidizing the pseudo-gate film 15 in an oxygen-containing atmosphere.

[0069] In the oxidation process, the difference in diffusion ability of oxygen-containing gas in the slit (i.e., the gap 21) and in the open area (i.e., the area on the pseudo-gate film 15 located at the top and top corner of the fin structure 11) is utilized, that is, the diffusion ability of oxygen-containing gas in the slit is weaker, so that the oxide layer 18 is thicker at the top and top corner of the fin structure 11 and thinner on the sidewall of the gap 21.

[0070] As one embodiment, the oxygen-containing atmosphere gas is oxygen. Oxygen is a common oxidizing gas, which is beneficial for improving process compatibility and reducing costs. Moreover, using oxygen for oxidation treatment also helps to reduce the generation of by-products, thereby reducing side effects.

[0071] In other embodiments, the oxygen-containing atmosphere can also be other types of oxygen-containing gas, such as nitric oxide. Nitric oxide is a weakly oxidizing oxygen-containing gas. By selecting this weakly oxidizing oxygen-containing gas, it is beneficial to control the oxidation rate, prevent excessive oxidation of the pseudo-gate film and avoid forming an excessively thick oxide layer. Consequently, it helps prevent the problem of an excessively thin remaining pseudo-gate film after subsequent oxide layer removal, reducing the number of aspect ratio adjustment processes, thereby simplifying the process and saving costs.

[0072] It should be noted that during the formation of the oxide layer 18, the oxygen gas flow rate should not be too high; otherwise, the dummy gate film 15 may be oxidized at an excessive rate, which is detrimental to process control and may also lead to excessive oxidation of the dummy gate film 15. Therefore, in this embodiment, the oxygen gas flow rate is less than or equal to 50 ml / min.

[0073] The oxygen flow rate should not be too low, otherwise the oxidation process will be inefficient. Therefore, in this embodiment, the oxygen flow rate is 10 ml / min to 50 ml / min, for example: 35 ml / min, 40 ml / min, 45 ml / min, 50 ml / min, etc.

[0074] In other embodiments, the step of forming the oxide layer may further include: oxidizing the dummy gate film using oxygen free radicals. Specifically, oxygen free radicals are generated by ion bombardment, and then introduced into the reaction chamber to oxidize the dummy gate film.

[0075] During the oxidation process of the pseudo-gate film using oxygen free radicals, the difference in diffusion ability of oxygen free radicals in the slits (i.e., the gaps) and in the open areas (i.e., the areas on the pseudo-gate film located at the top and top corners of the fin structure) can be utilized to make the oxide layer thicker at the top and top corners of the fin structure and thinner on the sidewalls of the gaps, thereby also achieving the effect of adjusting the aspect ratio.

[0076] It should be noted that during the oxidation treatment of the dummy gate film using oxygen free radicals, the chamber temperature within the reaction chamber should not be too low or too high. If the chamber temperature is too low, the oxidation rate will be too low; if the chamber temperature is too high, the dummy gate film will transform into an oxide layer too quickly, which is detrimental to process control and may also lead to excessive oxidation of the dummy gate film. Therefore, in this embodiment, the chamber temperature is between 240°C and 750°C, for example: 300°C, 400°C, 500°C, 600°C, 700°C, etc.

[0077] like Figure 8 As shown, the oxide layer 18 is removed.

[0078] Specifically, the oxide layer 18 is removed to provide space for the subsequent deposition of the second pseudo-gate film 17.

[0079] In this embodiment, the process for removing the oxide layer 18 includes a gas etching process.

[0080] Specifically, the etching gas in the gas etching process is hydrofluoric acid gas. The etching gas has a high selectivity for etching the oxide layer 18 and the dummy gate film 15, which can effectively reduce the impact of the gas etching process on the remaining dummy gate film 15, thereby improving the quality of the remaining dummy gate film 15.

[0081] It should be noted that, in this embodiment, the aspect ratio adjustment process further includes: after oxidizing the pseudo-gate film 15 and before removing the oxide layer 18, the pseudo-gate film 15 is subjected to a heat preservation treatment.

[0082] Specifically, the pseudo-gate film 15 is subjected to heat preservation treatment in a protective atmosphere.

[0083] The heat preservation treatment is used to provide energy to the pseudo-gate film 15 in a high-temperature environment, causing the internal atoms of the pseudo-gate film 15 to migrate. When the migration reaches a certain level, the energy is released, and the internal atoms reach a steady state.

[0084] Oxidizing the pseudo-gate film 15 can fix the dangling bonds on the surface of the pseudo-gate film 15 and inhibit the migration of atoms on the surface of the pseudo-gate film 15. This can avoid the problem of atomic agglomeration caused by the migration of the dangling bonds during the heat preservation process. Correspondingly, it helps to prevent the agglomerated atoms from blocking the openings between adjacent fin structures 11, and can reduce the probability of generating holes in the first pseudo-gate layer 14.

[0085] In this embodiment, the protective atmosphere includes an inert gas or hydrogen, and the inert gas can be nitrogen or argon.

[0086] It should be noted that the process temperature of the heat preservation treatment should not be too low or too high. If the process temperature of the heat preservation treatment is too low, the internal atoms of the pseudo-gate 15 may not be able to accumulate enough energy to migrate, which is not conducive to the internal atoms of the pseudo-gate 15 reaching a steady state; if the process temperature of the heat preservation treatment is too high, it may cause the material of the pseudo-gate 15 to crystallize, affecting the morphology of the pseudo-gate structure. Therefore, in this embodiment, the process temperature of the heat preservation treatment is 250°C to 550°C.

[0087] Accordingly, in this embodiment, the process time for heat preservation of the pseudo-gate film 15 is 1 minute to 180 minutes.

[0088] In this embodiment, during the aspect ratio adjustment process, the dangling bonds in the pseudo-gate film 15 can be fixed by oxidizing the pseudo-gate film 15, which helps to reduce the probability of atomic aggregation caused by dangling bonds. As a result, the process temperature of the heat preservation process can be increased accordingly during the heat preservation process, allowing the internal atoms of the pseudo-gate film 15 to enter a steady state more quickly. This, in turn, helps to improve the process efficiency of the heat preservation process, save process time, and reduce costs.

[0089] refer to Figure 9 A second pseudo-gate layer 17 is formed on the first pseudo-gate layer 14 to fill the V-shaped groove 16. The second pseudo-gate layer 17 and the first pseudo-gate layer 14 constitute a pseudo-gate structure 19, which spans the fin structure 11.

[0090] The pseudo-gate structure 19 is used to occupy space for the subsequent formation of the device gate structure.

[0091] In this embodiment, the first pseudo-gate layer 14 is formed by adjusting the aspect ratio once or multiple times, which helps to reduce the probability of atomic agglomeration caused by dangling bonds. This reduces the likelihood of agglomerated atomic clusters blocking the openings between adjacent fin structures 11, thus reducing the probability of holes and other defects in the pseudo-gate structure 19.

[0092] Furthermore, through the aspect ratio adjustment process, the first dummy gate layer 14 located on the opposite sidewalls of the fin structure 11 forms a V-shaped trench 16. The top opening size of the V-shaped trench 16 is larger than the bottom opening size, thereby reducing the aspect ratio of the V-shaped trench 16. This reduces the filling difficulty between the first dummy gate layer 14 on the adjacent fin sidewalls of the second dummy gate layer 17, correspondingly reducing the probability of defects such as holes in the second dummy gate layer 17, improving the filling performance of the second dummy gate layer 17 between adjacent fin structures 11, and the film formation quality of the dummy gate structure 19, thus providing a process basis for the subsequent formation of the device gate structure.

[0093] Specifically, the dummy gate structure 19 will be removed to form a gate opening, and the device gate structure will be filled in the gate opening. This embodiment improves the probability of generating defects such as holes in the dummy gate structure 19 and improves the filling quality of the dummy gate structure 19. Correspondingly, it reduces the probability of impurities accumulating in the holes and being difficult to remove during the subsequent removal of the dummy gate structure 19, reduces the generation of defects such as impurities in the subsequent device gate structure, and improves the formation quality of the device gate structure, thereby optimizing the performance of the semiconductor structure.

[0094] In this embodiment, the material of the second dummy gate layer 17 is amorphous silicon. The material of the second dummy gate layer 17 is the same as that of the first dummy gate layer 14, which is beneficial for improving process compatibility. In other embodiments, the material of the second dummy gate layer can also be polycrystalline silicon.

[0095] Specifically, in this embodiment, the second pseudo-gate layer 17 is formed using atomic layer deposition (ALD). Atomic layer deposition has good gap-filling performance and step coverage, which is beneficial to improving the filling quality of the second pseudo-gate layer 17 in the V-shaped trench 16.

[0096] It should be noted that the method for forming the semiconductor structure further includes: after forming the dummy gate structure 19, forming source and drain doped regions (not shown) in the fin structures 11 on both sides of the dummy gate structure 19.

[0097] The source and drain doped layers are used as the source or drain of a field-effect transistor. When the field-effect transistor is working, the source and drain doped layers are used to provide the source of charge carriers.

[0098] In this embodiment, the source / drain doped layer includes an ion-doped stress layer, which provides stress to the channel region, thereby improving carrier mobility. Specifically, when forming an NMOS transistor, the source / drain doped layer includes an N-type ion-doped stress layer, and the material of the stress layer is Si or SiC; when forming a PMOS transistor, the source / drain doped layer includes a P-type ion-doped stress layer, and the material of the stress layer is Si or SiGe.

[0099] refer to Figure 10 The method for forming the semiconductor structure further includes: the fin structure 11 being a fin; removing the dummy gate structure 19 to form a gate opening (not shown); and forming a device gate structure 20 in the gate opening.

[0100] The gate opening provides spatial location for forming the device gate structure 20. The method for forming the semiconductor structure further includes removing the dummy gate structure 13 after removing the dummy gate structure 19 and before forming the device gate structure 20 in the gate opening.

[0101] The device gate structure 20 is used to control the opening and closing of the conductive channel.

[0102] In this embodiment, the device gate structure 20 spans the fin and covers part of the top and part of the sidewalls of the fin.

[0103] In this embodiment, the device gate structure 20 is a metal gate structure, and the device gate structure 20 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0104] The gate dielectric layer is used to achieve insulation between the device gate structure 20 and the fin structure.

[0105] The material of the gate dielectric layer includes one or more of silicon oxide, nitrogen-doped silicon oxide, HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, La2O3, and Al2O3.

[0106] Specifically, the gate dielectric layer may include a high-k gate dielectric layer or a gate oxide layer, or the gate dielectric layer may include a gate oxide layer and a high-k gate dielectric layer located on the gate oxide layer.

[0107] The gate electrode layer is made of Al, Cu, Ag, Au, Pt, Ni, Ti, or W. In this embodiment, the gate electrode layer is made of W.

[0108] In other embodiments, the device gate structure may also be a polysilicon gate structure. Accordingly, the device gate structure includes a gate oxide layer and a polysilicon gate layer located on the gate oxide layer.

[0109] In other embodiments, when the fin structure includes a protrusion on the substrate and one or more channel stacks located on the protrusion, after forming the source / drain doped regions, the method of forming the semiconductor structure further includes: removing the dummy gate structure to form a gate opening; removing the sacrificial layer through the gate opening to form a through-slot between the protrusion and an adjacent channel layer or between adjacent channel layers; and forming a device gate structure within the gate opening and the through-slot, the device gate structure surrounding the channel layer.

[0110] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a plurality of discrete fin structures located on the substrate, the fin structures being used to provide channels; One or more aspect ratio adjustments are performed to form a first pseudo-gate layer on the top and sidewalls of the exposed fin structure. The first pseudo-gate layer on the opposite sidewalls of the fin structure forms a V-shaped groove. The aspect ratio adjustment process includes: forming a pseudo-gate film on the exposed top and sidewalls of the fin structure, with gaps between the pseudo-gate films located on opposite sidewalls of the fin structure; oxidizing the pseudo-gate film to convert a portion of the pseudo-gate film into an oxide layer; and removing the oxide layer. A second pseudo-gate layer is formed on the first pseudo-gate layer to fill the V-shaped trench. The second pseudo-gate layer and the first pseudo-gate layer constitute a pseudo-gate structure, which spans the fin structure.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the first pseudo-gate layer includes amorphous silicon or polycrystalline silicon.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, Forming the oxide layer includes oxidizing the pseudo-gate film in an oxygen-containing atmosphere.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The oxygen-containing atmosphere includes oxygen or nitric oxide.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The oxygen-containing atmosphere is oxygen, and the process parameters for the oxidation treatment include: the oxygen flow rate is less than or equal to 50 ml / min.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The formation of the oxide layer includes: oxidizing the pseudo-gate film using oxygen free radicals.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process parameters for oxidation treatment include: chamber temperature of 240℃ to 550℃.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for removing the oxide layer includes a gas etching process; the etching gas includes hydrofluoric acid gas.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the pseudo-gate film, the thickness of the pseudo-gate film is 1 nm to 10 nm.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the aspect ratio adjustment process, during the formation of the dummy gate film, the thickness of the dummy gate film is a first thickness; during the oxidation process of the dummy gate film, the oxidized thickness of the dummy gate film located on top of the fin structure is a second thickness, which is 50% to 80% of the first thickness.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the step of forming the first pseudo-gate layer, the first pseudo-gate layer located on the opposite sidewall of the fin structure forms a V-shaped trench, wherein the depth-to-width ratio of the V-shaped trench is 2:1 to 10:

1.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The aspect ratio adjustment process further includes: after oxidizing the pseudo-gate film and before removing the oxide layer, performing a heat preservation treatment on the pseudo-gate film.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The process parameters for heat preservation treatment of the pseudo-gate film include: process temperature of 240℃ to 550℃ and process time of 1 minute to 180 minutes.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the semiconductor structure further includes: after providing the substrate and before performing one or more aspect ratio adjustment processes, forming an isolation layer surrounding the fin structure on the substrate, wherein the top surface of the isolation layer is lower than the top surface of the fin structure; and forming a pseudo-gate oxide layer on the top and sidewalls of the fin structure exposed by the isolation layer. In the step of forming the first pseudo-gate layer, the first pseudo-gate layer is formed on the pseudo-gate oxide layer on the top and sidewalls of the fin structure.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The fin-like structure is a fin section; Alternatively, the fin structure may include a protrusion on a substrate and one or more channel stacks on the protrusion, each channel stack including a sacrificial layer and a channel layer on the sacrificial layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The method for forming the semiconductor structure further includes: after forming the dummy gate structure, forming source / drain doped regions in the fin structures on both sides of the dummy gate structure; The method for forming the semiconductor structure further includes: the fin structure being a fin; removing the dummy gate structure to form a gate opening; and forming a device gate structure in the gate opening; or... The fin structure includes a protrusion on a substrate and one or more channel stacks on the protrusion; the dummy gate structure is removed to form a gate opening; the sacrificial layer is removed through the gate opening to form a through-slot between the protrusion and an adjacent channel layer or between adjacent channel layers; a device gate structure is formed in the gate opening and the through-slot, the device gate structure surrounding the channel layer.

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