Three-dimensional heterogeneous integrated radio frequency microsystem

Abstract

The application discloses a three-dimensional heterogeneous integrated radio frequency micro system, which comprises a silicon-based packaging layer and a high / low temperature co-fired ceramic packaging layer; a low-power radio frequency chip is placed on a silicon-based adapter layer, and the connection of radio frequency signals, power signals and control signals is completed through a top redistribution layer of the silicon-based adapter layer and a silicon-based packaging bonding wire; a high-power radio frequency chip is placed on a high / low temperature co-fired ceramic base, and the connection of radio frequency signals, power signals and control signals is completed through a high / low temperature co-fired ceramic packaging bonding wire and the high / low temperature co-fired ceramic base. The application adopts a combination mode of a silicon-based packaging technology and a high / low temperature co-fired ceramic technology, realizes three-dimensional packaging of a system through multi-chip stacking, and optimizes the layout of chips in the package according to the characteristics of packaging materials and chip materials, the radio frequency performance and the physical performance of the two, so that the volume of the radio frequency micro system is reduced, and the reliability of the system is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency microsystem packaging technology, and particularly to a three-dimensional heterogeneous integrated radio frequency microsystem. BACKGROUND

[0002] Traditional integrated circuit packaging mainly adopts two-dimensional structure single chip packaging or simple IC stacking technology, which has extremely low internal space utilization and long interconnection, easily causing complex interconnection parasitic effects, and further leading to signal distortion, seriously affecting the performance of the chip. In order to realize the miniaturization, lightness, thinness, integration, multifunction, low power consumption, high reliability and low cost of the system device, engineers have proposed chip stacking technology and vertical interconnection technology and other system packaging technologies and methods.

[0003] High / low temperature co-fired ceramic packaging technology and silicon-based packaging technology can both perform three-dimensional stacking of chips to realize three-dimensional packaging of the system. The two packaging technologies have their own advantages and disadvantages. The high / low temperature co-fired ceramic packaging process is low in price, but has low process precision. The silicon-based packaging process is high in cost, but has high process precision and can better compatible with silicon-based chips.

[0004] With the development of radio frequency microsystem technology, the volume of the system is becoming smaller and smaller, the power density in the unit volume of the system is becoming higher and higher, and the requirement for process processing precision is also becoming higher and higher. The comprehensive application of high / low temperature co-fired ceramic packaging technology and silicon-based packaging technology can fully play the advantages of the two packaging processes and improve the performance of the radio frequency microsystem.

[0005] Patent 1 (application number: 201810340528.1, application date: April 17, 2018) provides a ceramic double-sided three-dimensional integrated architecture of an ultra-wideband radio frequency microsystem. Cavities are formed on both sides of the ceramic substrate. A metal microframe is welded on the front surface of the ceramic substrate. A front cover plate is welded on the metal microframe. A back cover plate is welded on the back cavity of the ceramic substrate. BGA pads are arranged on the area of the back surface of the ceramic substrate except the back cover plate. BGA solder balls are welded on the back surface of the ceramic substrate through the BGA pads. The internal integration density of the radio frequency microsystem is improved by nearly one time. The volume occupancy rate of the external interconnection interface and the hermetic packaging is greatly reduced. However, the thermal expansion coefficient and the thermal conductivity of the system are poor, and the thermal reliability is not good enough. Patent 2 (application number: 201610626411.0, application date: August 2, 2016) provides a radio frequency microsystem packaging module and a manufacturing method. Through wafer vertical stacking and electrical interconnection, the packaging size of the radio frequency microsystem packaging module is reduced, and its electrical performance is improved. However, the problem of the thermal expansion coefficient and the thermal conductivity of the system is not solved. SUMMARY

[0006] The three-dimensional heterogeneous integrated radio frequency microsystem has high integration, small volume, low power, high stability and low production cost.

[0007] The technical solution for achieving the object of the present application is as follows: a three-dimensional heterogeneous integrated radio frequency microsystem, comprising a silicon-based packaging layer and a high / low-temperature co-fired ceramic packaging layer.

[0008] The silicon-based packaging layer comprises solder balls, a top redistribution layer of a silicon-based cover layer, an insulating layer of the silicon-based cover layer, the silicon-based cover layer, a through silicon via of the silicon-based cover layer, a silicon-based cavity, a low-power radio frequency chip, a silicon-based packaging bonding wire, a top redistribution layer of a silicon-based adapter layer, the silicon-based adapter layer, a through silicon via of the silicon-based adapter layer and a bottom redistribution layer of the silicon-based adapter layer arranged in sequence.

[0009] The high / low-temperature co-fired ceramic packaging layer comprises heterogeneous interlayer solder balls, a high / low-temperature co-fired ceramic cover plate, a high / low-temperature co-fired ceramic cavity, a high / low-temperature co-fired ceramic vertical via, a high-power radio frequency chip, a high / low-temperature co-fired ceramic packaging bonding wire and a high / low-temperature co-fired ceramic base arranged in sequence.

[0010] The low-power radio frequency chip is placed on the silicon-based adapter layer, and the connection of radio frequency signals, power supply signals and control signals is completed through the top redistribution layer of the silicon-based adapter layer and the silicon-based packaging bonding wire; the high-power radio frequency chip is placed on the high / low-temperature co-fired ceramic base, and the connection of radio frequency signals, power supply signals and control signals is completed through the high / low-temperature co-fired ceramic packaging bonding wire and the high / low-temperature co-fired ceramic base.

[0011] Further, the high-power radio frequency chip is placed on the high / low-temperature co-fired ceramic base, signals are introduced into the top of the high / low-temperature co-fired ceramic packaging layer through the high / low-temperature co-fired ceramic packaging bonding wire, the high / low-temperature co-fired ceramic base and the high / low-temperature co-fired ceramic vertical via, and then signal interconnection is formed with the silicon-based packaging layer.

[0012] Further, the high / low-temperature co-fired ceramic base is free of solder balls on the bottom.

[0013] Further, the top redistribution layer of the silicon-based cover layer in the silicon-based packaging layer is provided with solder balls, and the solder balls are interconnected with an external motherboard.

[0014] Further, the bottom redistribution layer of the silicon-based adapter layer in the silicon-based packaging layer is provided with a solder pad, and signal interconnection is formed with the high / low-temperature co-fired ceramic packaging layer through the heterogeneous interlayer solder balls.

[0015] Further, the silicon-based packaging layer is composed of N layers of solder balls, a top redistribution layer of a silicon-based cover layer, an insulating layer of the silicon-based cover layer, the silicon-based cover layer, a through silicon via of the silicon-based cover layer, a silicon-based cavity, a low-power radio frequency chip, a silicon-based packaging bonding wire, a top redistribution layer of a silicon-based adapter layer, the silicon-based adapter layer, a through silicon via of the silicon-based adapter layer, and a bottom redistribution layer of the silicon-based adapter layer to form an N-layer silicon-based package, and signal interconnection is realized between layers through solder, and N is greater than or equal to 1.

[0016] Further, the high / low-temperature co-fired ceramic packaging layer is composed of N layers of heterogeneous interlayer solder balls, a high / low-temperature co-fired ceramic cover plate, a high / low-temperature co-fired ceramic cavity, a high / low-temperature co-fired ceramic vertical via, a high-power radio frequency chip, a high / low-temperature co-fired ceramic packaging bonding wire, and a high / low-temperature co-fired ceramic base to form an N-layer high / low-temperature co-fired ceramic package, and signal interconnection is realized between layers through solder, and N is greater than or equal to 1.

[0017] Compared with the prior art, the present application has the following advantages: (1) the high / low-temperature co-fired ceramic packaging process and the silicon-based packaging process are combined, thick chips can be integrated by using the high / low-temperature co-fired ceramic packaging process, and the integration degree of the system is improved; (2) the high / low-temperature co-fired ceramic has a higher thermal expansion coefficient and thermal conductivity than the silicon-based material, the use of the two packaging processes solves the problem of reduced thermal reliability caused by the high-power radio frequency chip, and the reliability of the system is improved. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a structural schematic diagram of a three-dimensional heterogeneous integrated radio frequency microsystem according to the present application.

[0019] Figure 2 is a structural schematic diagram of a two-layer silicon-based package + one-layer high / low-temperature co-fired ceramic package in an embodiment of the present application.

[0020] Figure 3 is a structural schematic diagram of a one-layer silicon-based package + two-layer high / low-temperature co-fired ceramic package in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The present application will be further described in detail below with reference to the drawings and specific embodiments.

[0022] In combination Figure 1 , the three-dimensional heterogeneous integrated radio frequency microsystem according to the present application comprises a silicon-based packaging layer 120 and a high / low-temperature co-fired ceramic packaging layer 121.

[0023] The silicon-based packaging layer 120 includes solder balls 101, a silicon-based cover layer top redistribution layer 102, a silicon-based cover layer insulating layer 103, a silicon-based cover layer 104, a silicon-based cover layer through silicon via 105, a silicon-based cavity 106, a low-power radio frequency chip 107, a silicon-based packaging bonding wire 108, a silicon-based adapter layer top redistribution layer 109, a silicon-based adapter layer 110, a silicon-based adapter layer through silicon via 111, and a silicon-based adapter layer bottom redistribution layer 112 arranged in sequence.

[0024] The high / low-temperature co-fired ceramic packaging layer includes heterogeneous interlayer solder balls 113, a high / low-temperature co-fired ceramic cover plate 114, a high / low-temperature co-fired ceramic cavity 115, a high / low-temperature co-fired ceramic vertical via 116, a high-power radio frequency chip 117, a high / low-temperature co-fired ceramic packaging bonding wire 118, and a high / low-temperature co-fired ceramic base 119 arranged in sequence.

[0025] The low-power radio frequency chip 107 is placed on the silicon-based adapter layer 110, and the connection of radio frequency signals, power signals, and control signals is completed through the silicon-based adapter layer top redistribution layer 109 and the silicon-based packaging bonding wire 108. The high-power radio frequency chip 117 is placed on the high / low-temperature co-fired ceramic base 119, and the connection of radio frequency signals, power signals, and control signals is completed through the high / low-temperature co-fired ceramic packaging bonding wire 118 and the high / low-temperature co-fired ceramic base 119.

[0026] Further, the high-power radio frequency chip 117 is placed on the high / low-temperature co-fired ceramic base 119, and the signal is introduced to the top of the high / low-temperature co-fired ceramic packaging layer 121 through the high / low-temperature co-fired ceramic packaging bonding wire 118, the high / low-temperature co-fired ceramic base 119, and the high / low-temperature co-fired ceramic vertical via 116, and then forms signal interconnection with the silicon-based packaging layer 120.

[0027] Further, the bottom of the high / low-temperature co-fired ceramic base 119 is not planted with solder balls, and can be in full contact with the cold plate unit, thereby ensuring the best heat conduction effect of the high-power radio frequency chip 117 and the cold plate unit.

[0028] Further, the solder balls 101 are planted on the silicon-based cover layer top redistribution layer 102 in the silicon-based packaging layer 120, and the solder balls 101 are interconnected with an external motherboard.

[0029] Further, the solder pads are arranged on the silicon-based adapter layer bottom redistribution layer 112 in the silicon-based packaging layer 120, and can form signal interconnection with the high / low-temperature co-fired ceramic packaging layer 121 through the heterogeneous interlayer solder balls 113.

[0030] Further, the silicon-based packaging layer 120 can be composed of 1 layer of solder balls 101, a silicon-based cover layer top redistribution layer 102, a silicon-based cover layer insulating layer 103, a silicon-based cover layer 104, a silicon-based cover layer through silicon via 105, a silicon-based cavity 106, a low-power radio frequency chip 107, a silicon-based packaging bonding wire 108, a silicon-based adapter layer top redistribution layer 109, a silicon-based adapter layer 110, a silicon-based adapter layer through silicon via 111, and a silicon-based adapter layer bottom redistribution layer 112. Alternatively, the silicon-based packaging layer 120 can be composed of N layers of silicon-based packaging, where N > 1, and the layers are connected by solder.

[0031] Further, the high / low temperature co-fired ceramic packaging layer 121 can be composed of 1 layer of heterogeneous interlayer solder balls 113, a high / low temperature co-fired ceramic cover plate 114, a high / low temperature co-fired ceramic cavity 115, a high / low temperature co-fired ceramic vertical via 116, a high-power radio frequency chip 117, a high / low temperature co-fired ceramic packaging bonding wire 118, and a high / low temperature co-fired ceramic base 119. Alternatively, the high / low temperature co-fired ceramic packaging layer 121 can be composed of N layers of high / low temperature co-fired ceramic packaging, where N > 1, and the layers are connected by solder.

[0032] Further, the silicon-based packaging layer 120 uses a silicon-based packaging process, which improves the integration of the system.

[0033] Further, the high / low temperature co-fired ceramic packaging layer 121 uses a high / low temperature co-fired ceramic packaging process, which improves the thermal expansion coefficient and thermal conductivity of the system.

[0034] Further, the silicon-based packaging process and the high / low temperature co-fired ceramic packaging process are used together, which solves the problem of reduced thermal reliability caused by high-power radio frequency chips while maintaining a small system size.

[0035] Embodiment 1

[0036] The three-dimensional heterogeneous integrated radio frequency microsystem of this embodiment uses a 2-layer silicon-based packaging + 1-layer high / low temperature co-fired ceramic packaging structure, as shown in FIG. 1. Figure 2As shown, the three-dimensional heterogeneous integrated radio frequency microsystem is composed of a silicon-based packaging layer 220 and a high / low temperature co-fired ceramic packaging layer 221. From top to bottom, the silicon-based packaging layer 220 comprises, in sequence, 1 layer of solder balls 201, 1 layer of a silicon-based cover layer top redistribution layer 202, 1 layer of a silicon-based cover layer insulating layer 203, 1 layer of a silicon-based cover layer 204, 1 layer of a silicon-based cover layer through silicon via 205, 1 layer of a silicon-based cavity 206, 1 layer of a low-power radio frequency chip 207, 1 layer of a silicon-based packaging bonding wire 208, 1 layer of a silicon-based adapter layer top redistribution layer 209, 1 layer of a silicon-based adapter layer 210, 1 layer of a silicon-based adapter layer through silicon via 211, 1 layer of a silicon-based adapter layer bottom redistribution layer 212, 2 layers of solder balls 222, 2 layers of a silicon-based cover layer top redistribution layer 223, 2 layers of a silicon-based cover layer insulating layer 224, 2 layers of a silicon-based cover layer 225, 2 layers of a silicon-based cover layer through silicon via 226, 2 layers of a silicon-based cavity 227, 2 layers of a low-power radio frequency chip 228, 2 layers of a silicon-based packaging bonding wire 229, 2 layers of a silicon-based adapter layer top redistribution layer 230, 2 layers of a silicon-based adapter layer 231, 2 layers of a silicon-based adapter layer through silicon via 232, and 2 layers of a silicon-based adapter layer bottom redistribution layer 233. The high / low temperature co-fired ceramic packaging layer 221 comprises, in sequence, a heterogeneous interlayer solder ball 213, a high / low temperature co-fired ceramic cover plate 214, a high / low temperature co-fired ceramic cavity 215, a high / low temperature co-fired ceramic vertical via 216, a high-power radio frequency chip 217, a high / low temperature co-fired ceramic packaging bonding wire 218, and a high / low temperature co-fired ceramic base 219. This packaging structure can integrate more low-power radio frequency chips and improve the integration of the system.

[0037] Example 2

[0038] The three-dimensional heterogeneous integrated radio frequency microsystem of this embodiment adopts a 1-layer silicon-based packaging + 2-layer high / low temperature co-fired ceramic packaging structure, as shown in FIG. 2. Figure 3As shown, the three-dimensional heterogeneous integrated radio frequency microsystem is composed of a silicon-based packaging layer 320 and a high / low temperature co-fired ceramic packaging layer 321. From top to bottom, the silicon-based packaging layer 320 comprises, in sequence, solder balls 301, a top redistribution layer of a silicon-based cover layer 302, an insulating layer of the silicon-based cover layer 303, the silicon-based cover layer 304, a through silicon via of the silicon-based cover layer 305, a silicon-based cavity 306, a low-power radio frequency chip 307, a silicon-based packaging bonding wire 308, a top redistribution layer of a silicon-based adapter layer 309, the silicon-based adapter layer 310, a through silicon via of the silicon-based adapter layer 311, a bottom redistribution layer of the silicon-based adapter layer 312; the high / low temperature co-fired ceramic packaging layer 321 comprises, in sequence, two layers of solder balls 313, two layers of high / low temperature co-fired ceramic cover plates 314, two layers of high / low temperature co-fired ceramic cavities 315, two layers of high / low temperature co-fired ceramic vertical vias 316, two layers of high-power radio frequency chips 317, two layers of high / low temperature co-fired ceramic packaging bonding wires 318, two layers of high / low temperature co-fired ceramic pedestals 319, one layer of solder balls 322, one layer of high / low temperature co-fired ceramic cover plates 323, one layer of high / low temperature co-fired ceramic cavities 324, one layer of high / low temperature co-fired ceramic vertical vias 325, one layer of low-power radio frequency chips 326, one layer of high / low temperature co-fired ceramic packaging bonding wires 327, and one layer of high / low temperature co-fired ceramic pedestals 328. The one layer of low-power radio frequency chips 326 can be a chip with a very thick thickness that cannot be integrated by using a silicon-based process, thereby expanding the types of integrated chips.

[0039] The high / low temperature co-fired ceramic packaging process and the silicon-based packaging process are combined, the chip with a relatively thick thickness is integrated by using the high / low temperature co-fired ceramic packaging process, and the integration degree of the system is improved; the high / low temperature co-fired ceramic has a higher thermal expansion coefficient and a higher thermal conductivity than the silicon-based material, the two packaging processes are used in combination, the problem of reduced thermal reliability caused by the high-power radio frequency chip is solved, and the reliability of the system is improved.

[0040] The above merely describes the preferred embodiments of the present application, and any equivalent changes and modifications made within the scope of the claims of the present application shall fall within the scope of the claims of the present application.

Claims

1. A three-dimensional heterogeneous integrated radio frequency microsystem, characterized in that, The silicon-based packaging layer (120) and the high / low temperature co-fired ceramic packaging layer (121) are included. The silicon-based packaging layer (120) includes sequentially arranged solder balls (101), a silicon-based cover layer top redistribution layer (102), a silicon-based cover layer insulating layer (103), a silicon-based cover layer (104), a silicon-based cover layer through silicon via (105), a silicon-based cavity (106), a low-power radio frequency chip (107), a silicon-based packaging bonding wire (108), a silicon-based adapter layer top redistribution layer (109), a silicon-based adapter layer (110), a silicon-based adapter layer through silicon via (111), and a silicon-based adapter layer bottom redistribution layer (112). The high / low temperature co-fired ceramic packaging layer (121) includes sequentially arranged heterogeneous interlayer solder balls (113), a high / low temperature co-fired ceramic cover plate (114), a high / low temperature co-fired ceramic cavity (115), a high / low temperature co-fired ceramic vertical via (116), a high-power radio frequency chip (117), a high / low temperature co-fired ceramic packaging bonding wire (118), and a high / low temperature co-fired ceramic base (119). The low-power radio frequency chip (107) is placed on the silicon-based adapter layer (110), and the connection of radio frequency signals, power signals, and control signals is completed through the silicon-based adapter layer top redistribution layer (109) and the silicon-based packaging bonding wire (108); the high-power radio frequency chip (117) is placed on the high / low temperature co-fired ceramic base (119), and the connection of radio frequency signals, power signals, and control signals is completed through the high / low temperature co-fired ceramic packaging bonding wire (118) and the high / low temperature co-fired ceramic base (119).

2. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, The high-power radio frequency chip (117) is placed on the high / low temperature co-fired ceramic base (119), signals are introduced to the top of the high / low temperature co-fired ceramic packaging layer (121) through the high / low temperature co-fired ceramic packaging bonding wire (118), the high / low temperature co-fired ceramic base (119), and the high / low temperature co-fired ceramic vertical via (116), and then signal interconnection is formed with the silicon-based packaging layer (120).

3. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, The high / low temperature co-fired ceramic base (119) is free of ball planting at the bottom.

4. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, Solder balls (101) are planted on the silicon-based cover layer top redistribution layer (102) in the silicon-based packaging layer (120), and the solder balls (101) are interconnected with an external motherboard.

5. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, A solder pad is arranged on the silicon-based adapter layer bottom redistribution layer (112) in the silicon-based packaging layer (120), and signal interconnection is formed with the high / low temperature co-fired ceramic packaging layer (121) through the heterogeneous interlayer solder balls (113).

6. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, The silicon-based packaging layer (120) is composed of N layers of solder balls (101), a silicon-based cover layer top redistribution layer (102), a silicon-based cover layer insulating layer (103), a silicon-based cover layer (104), a silicon-based cover layer through silicon via (105), a silicon-based cavity (106), a low-power radio frequency chip (107), a silicon-based packaging bonding wire (108), a silicon-based adapter layer top redistribution layer (109), a silicon-based adapter layer (110), a silicon-based adapter layer through silicon via (111), and a silicon-based adapter layer bottom redistribution layer (112), and signal interconnection is achieved between layers through solder, N≥1.

7. The 3-D heterogeneous integrated radio-frequency microsystem of claim 1, wherein, The high / low temperature co-fired ceramic packaging layer (121) is composed of N layers of heterogeneous interlayer solder balls (113), a high / low temperature co-fired ceramic cover plate (114), a high / low temperature co-fired ceramic cavity (115), a high / low temperature co-fired ceramic vertical via (116), a high-power radio frequency chip (117), a high / low temperature co-fired ceramic packaging bonding wire (118), and a high / low temperature co-fired ceramic base (119) to form an N-layer high / low temperature co-fired ceramic package, and signal interconnection is realized through solder between layers, and N≥1.

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