A super-fast avalanche transistor suitable for voltage pulse triggering
By introducing a ring-shaped deep well structure and an oxygen-doped semi-insulating polysilicon layer into the avalanche transistor, the problems of premature turn-on and uneven overvoltage under voltage pulse triggering are solved, achieving higher withstand voltage and faster turn-on speed.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-11-28
- Publication Date
- 2026-03-24
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Figure CN115911116B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of power semiconductor technology, and more specifically, relates to an ultrafast avalanche transistor suitable for voltage pulse triggering. Background Technology
[0002] Power semiconductor devices are the core switching devices in the field of pulse technology, and their performance determines the output performance of the entire pulse system. The switching speed, voltage withstand capability, and current carrying capacity of power semiconductors are the core parameters of pulse switches.
[0003] Avalanche transistors (ATTs), as ultra-high-speed, fast-leading-edge semiconductor pulse power devices used in nanosecond (ns) and picosecond (ps) level pulse power systems, possess a series of excellent characteristics such as high speed and high reliability. Currently, the conventional application of ADTs involves base-triggered turn-on, with turn-on times exceeding tens of nanoseconds. However, ADTs used in fast-leading-edge pulse generator circuits often have their base and emitter shorted and are triggered by a voltage pulse, resulting in a very fast turn-on speed, often within sub-nanoseconds.
[0004] Current avalanche transistor designs are still designed for conventional base-triggered turn-on, without considering the more widely applicable voltage pulse-triggered ultra-fast turn-on. However, with the base and emitter shorted, avalanche transistors under voltage pulse triggering often exhibit problems such as premature turn-on and uneven overvoltage turn-on. Summary of the Invention
[0005] To address the shortcomings of existing technologies, the present invention aims to provide an ultrafast avalanche transistor suitable for voltage pulse triggering, which can effectively improve the voltage pulse withstand capability of avalanche transistors and solve the problems of premature turn-on and uneven turn-on under overvoltage triggering in traditional avalanche transistors.
[0006] To achieve the above objectives, the present invention provides an ultrafast avalanche transistor suitable for voltage pulse triggering, comprising, from bottom to top, a collector electrode, a collector n+ substrate layer, a collector n0 epitaxial layer, a p+ base layer, and an n+ emitter layer, wherein a ring-shaped deep well structure is provided next to the p+ base layer, the inner ring of the deep well structure is located close to the curved boundary of the p+ base layer, and the bottom of the deep well structure is the junction of the collector n0 epitaxial layer and the collector n+ substrate layer, and the deep well structure uses a passivation material SiO2-Si3N4 as the filler; an oxygen-doped semi-insulating polysilicon layer is covered on the n+ emitter layer, and the oxygen doping content of the oxygen-doped semi-insulating polysilicon layer is 25% to 30%;
[0007] The ultrafast avalanche transistor further includes a circular base electrode and an emitter electrode. The surface of the collector region n0 epitaxial layer is covered with an oxide layer, and a metal field plate is covered on the oxide layer. The metal field plate is in contact with the base electrode and the oxygen-doped semi-insulating polysilicon layer, respectively. The bottom of the metal field plate penetrates the oxide layer and contacts the p+ base layer, and the bottom of the emitter electrode penetrates the oxygen-doped semi-insulating polysilicon layer and contacts the n+ emitter layer.
[0008] In one embodiment, the material of the n+ substrate layer in the collector region is n-type SI-P, and its n+ doping concentration is 1*10⁻⁶. 19 cm -3 ~1*10 22 cm -3 The thickness of the n+ substrate layer in the collector region is 100 μm to 1 μm.
[0009] In one embodiment, the material of the collector region n0 epitaxial layer is n-type SI-P, and its n0 doping concentration is 1*10⁻⁶. 14 cm -3 ~1*10 16 cm -3 Furthermore, the thickness of both the collector region n0 epitaxial layer and the deep well structure is 100μm to 200μm.
[0010] In one embodiment, the material of the p+ base layer is p-type SI-B, and its p+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 The p+ base region layer has a thickness of 5 μm to 20 μm and a surface area of 1 μm². 2 ~100cm 2 The width of the deep well structure is 10μm to 20μm.
[0011] In one embodiment, the material of the n+ emitter layer is n-type SI-P, and its n+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 The thickness of the n+ emission region layer is 1μm to 10μm.
[0012] In one embodiment, the oxide layer is a SiO2 oxide layer, and the thickness of the oxide layer is 5 μm to 10 μm.
[0013] In one embodiment, the oxygen-doped semi-insulating polycrystalline silicon layer is SiO2. x A silicon and silicon oxide composite, wherein the thickness of the oxygen-doped semi-insulating polycrystalline silicon is 5 μm to 10 μm.
[0014] In one embodiment, the materials of the collector electrode, the base electrode, and the emitter electrode are all at least one metal selected from Al and Au, and the thickness of the collector electrode, the base electrode, and the emitter electrode is 0.5 μm to 50 μm.
[0015] In one embodiment, the material of the metal field plate is Al.
[0016] The ultrafast avalanche transistor suitable for voltage pulse triggering provided by this invention has the following effects:
[0017] (1) An annular deep well structure is provided at the junction of the p+ base region layer 30 and the collector region n0 epitaxial layer 20 in the avalanche transistor. Since the annular deep well structure is located next to the p+ base region layer 30, it can make the curved edge diffusion boundary ( Figure 3 The area indicated by reference numeral B is replaced by a deep well structure, which can solve the problem of lateral diffusion of p-type impurities in the p+ base layer 30 due to thermal processes and avoid the appearance of curved diffusion boundaries. At the same time, the deep well structure is filled with passivation layer material SiO2-Si3N4. Since SiO2-Si3N4 has weak conductivity, it can avoid the electric field from concentrating at the edge of the p+n0 junction, making the electric field distribution more uniform. It can effectively solve the problem of electric field spike accumulation at the curved edge of the outer boundary of the p+ base layer 30 inside the avalanche transistor under voltage pulse triggering conditions, thereby solving the problem of uneven breakdown of the device caused by uneven electric field at high peak values. As a result, the internal electric field distribution of the avalanche transistor is more uniform and the dv / dt withstand capacity is higher when the voltage pulse is triggered.
[0018] (2) An oxygen-doped semi-insulating polysilicon layer 80 is covered on the n+ emitter layer 40 in the avalanche transistor. Since the oxygen-doped semi-insulating polysilicon layer 80 is located on the p+ base layer 30 and is in contact with the metal field plate 70, and also in contact with the emitter 94, the oxygen doping content of the oxygen-doped semi-insulating polysilicon layer is 25% to 30%, which makes the oxygen-doped semi-insulating polysilicon layer 80 have weak conductivity. When the avalanche transistor is triggered by a voltage pulse, part of the leakage current in the p+ base region flows through the oxygen-doped semi-insulating polysilicon layer 80 to the emitter electrode 94, thereby reducing the amount of carrier injection on the n+ emitter layer 40 and slowing down the degree of collisional ionization of the carriers injected from the n+ emitter layer 40. This increases the dv / dt withstand capacity of the avalanche transistor when triggered by a voltage pulse, avoids premature turn-on of the avalanche transistor, and increases the withstand voltage value of the avalanche transistor when turned on by overvoltage. The higher the voltage that the avalanche transistor withstands when triggered by a voltage pulse, the more intense the collisional ionization, thereby increasing the overvoltage turn-on speed of the avalanche transistor. Attached Figure Description
[0019] Figure 1This is a schematic diagram of the structure of an ultrafast avalanche transistor suitable for voltage pulse triggering provided in an embodiment of the present invention;
[0020] Figure 2 This is a diagram showing the electric field distribution at the outer boundary of the p+ base region when the base-emitter junction is shorted and a voltage pulse is triggered in a conventional avalanche transistor.
[0021] Figure 3 This is the electric field distribution diagram of the outer boundary of the p+ base region when the base-emitter junction is shorted and the voltage pulse triggering is provided by the present invention.
[0022] Figure 4 This is a schematic diagram of the application circuit of the ultrafast avalanche transistor suitable for voltage pulse triggering provided by the present invention;
[0023] Figure 5 The voltage-current characteristic curves of the ultrafast avalanche transistor suitable for voltage pulse triggering provided by this invention and the conventional avalanche transistor are shown; where the horizontal axis is 10V / div and the vertical axis is 2e-8A / div.
[0024] Figure 6 This is a voltage pulse triggering turn-on characteristic curve of the ultrafast avalanche transistor and the conventional avalanche transistor provided by the present invention; wherein, the horizontal axis is 2e-9s / div and the vertical axis is 100V / div. Detailed Implementation
[0025] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.
[0026] It should be noted that in traditional power semiconductor devices, the pn junction plays a crucial role, and the voltage blocking capability of the pn junction directly affects the device's operating characteristics. For example... Figure 2 As shown, in the actual manufacturing process of power devices, when p-type impurity diffusion is performed on the surface of the n0 epitaxial layer in the collector region through a mask to form a pn0 junction, lateral diffusion occurs due to the thermal process, introducing curved diffusion boundaries at the edge of the pn0 junction. Figure 2 Within the range indicated by label A), the breakdown voltage at the curved diffusion boundary is much lower than that at the other flat edges of the pn junction. When voltage is applied across a conventional avalanche transistor, the voltage is mainly borne by the reverse collector junction pn0 inside the device. However, the curved diffusion boundary at the reverse collector junction pn0 has a larger electric field than the other flat edges, causing carriers to undergo collisional ionization first, leading to electrical breakdown and premature breakdown of the entire device, resulting in low withstand voltage.
[0027] To address this, the present invention provides an ultrafast avalanche transistor suitable for voltage pulse triggering, such as... Figure 1 As shown, it includes, from bottom to top, a collector region electrode 90, a collector region n+ substrate layer 10, a collector region n0 epitaxial layer 20, a p+ base region layer 30, and an n+ emitter region layer 40.
[0028] A ring-shaped deep well structure 50 is provided next to the p+ base region layer 30. The inner ring of the deep well structure 50 is located near the curved boundary of the p+ base region layer 30. The bottom of the deep well structure 50 is at the junction of the collector region n0 epitaxial layer 20 and the collector region n+ substrate layer 10. The deep well structure 50 is filled with a passivation material SiO2-Si3N4. An oxygen-doped semi-insulating polycrystalline silicon layer 80 is covered on the n+ emitter region layer 40. The oxygen doping content of the oxygen-doped semi-insulating polycrystalline silicon layer 80 is 25% to 30%.
[0029] In addition, the ultrafast avalanche transistor also includes a circular base electrode 92 and an emitter electrode 94. The surface of the collector region n0 epitaxial layer 20 is covered with an oxide layer 60, and a metal field plate 70 is covered on the oxide layer 60. The metal field plate 70 is in contact with the base electrode 92 and the oxygen-doped semi-insulating polysilicon layer 80, respectively. The bottom of the metal field plate 70 passes through the oxide layer 60 and contacts the p+ base layer 30. The bottom of the emitter electrode 94 passes through the oxygen-doped semi-insulating polysilicon layer 80 and contacts the n+ emitter layer 40.
[0030] The ultrafast avalanche transistor suitable for voltage pulse triggering provided in this embodiment has an annular deep well structure at the junction of the p+ base region layer 30 and the collector region n0 epitaxial layer 20 in the avalanche transistor. Since this annular deep well structure is located next to the p+ base region layer 30, it can make the curved edge diffusion boundary ( Figure 3 The area indicated by reference numeral B is replaced by a deep well structure, which can solve the problem of lateral diffusion of p-type impurities in the p+ base layer 30 due to thermal processes and avoid the appearance of curved diffusion boundaries. At the same time, the deep well structure is filled with passivation layer material SiO2-Si3N4. Since SiO2-Si3N4 has weak conductivity, it can avoid the electric field from concentrating at the edge of the p+n0 junction, making the electric field distribution more uniform. It can effectively solve the problem of electric field spike accumulation at the curved edge of the outer boundary of the p+ base layer 30 inside the avalanche transistor under voltage pulse triggering conditions, thereby solving the problem of uneven breakdown of the device caused by uneven electric field at high peak values. As a result, the internal electric field distribution of the avalanche transistor is more uniform and the dv / dt withstand capacity is higher when the voltage pulse is triggered.
[0031] Furthermore, the ultrafast avalanche transistor suitable for voltage pulse triggering provided in this embodiment has an oxygen-doped semi-insulating polysilicon layer 80 covering the n+ emitter layer 40 in the avalanche transistor. Since this oxygen-doped semi-insulating polysilicon layer 80 is disposed on the p+ base layer 30 and is in contact with the metal field plate 70, and also in contact with the emitter 94, the oxygen doping content of the oxygen-doped semi-insulating polysilicon layer is 25% to 30%, which makes the oxygen-doped semi-insulating polysilicon layer 80 have weak conductivity. This allows part of the leakage current in the p+ base region of the avalanche transistor to flow to the emitter electrode 94 through the oxygen-doped semi-insulating polysilicon layer 80 when the avalanche transistor is triggered by a voltage pulse. This reduces the amount of carrier injection on the n+ emitter layer 40 and slows down the degree of collisional ionization of the carriers injected from the n+ emitter layer 40. As a result, the dv / dt withstand capacity of the avalanche transistor is increased when triggered by a voltage pulse, avoiding premature turn-on of the avalanche transistor and increasing the withstand voltage value of the avalanche transistor when it is turned on by overvoltage. The higher the voltage that the avalanche transistor withstands when triggered by a voltage pulse, the more intense the collisional ionization, thereby increasing the overvoltage turn-on speed of the avalanche transistor.
[0032] To clearly illustrate the effects of the present invention, the following description is provided in conjunction with specific embodiments:
[0033] An ultrafast avalanche transistor suitable for voltage pulse triggering, such as Figure 1 As shown, the structure includes, from bottom to top, a collector region electrode 90, a collector region n+ substrate layer 10, a collector region n0 epitaxial layer 20, a p+ base region layer 30, and an n+ emitter region layer 40; an annular deep well structure 50 is disposed next to the p+ base region layer 30; and a circular base region electrode 92 and an emitter region electrode 94. The base region electrode 92 is connected to the surface field plate structure 70, and its bottom passes through the SiO2 oxide layer 60 and contacts the p+ base region layer 30. The surface of the n+ emitter region layer 40 is covered with an oxygen-doped semi-insulating polysilicon layer 80, and the bottom of the emitter region electrode 94 passes through the oxygen-doped semi-insulating polysilicon layer 80 and contacts the n+ emitter region layer 40.
[0034] Specifically, the fabrication method of the high-voltage deep-well avalanche transistor provided in this embodiment is as follows:
[0035] Step 1: Fabricate the collector region n+ substrate layer 10, wherein the material of the collector region n+ substrate layer 10 is n-type SI-P, and its n+ doping concentration is 1*10⁻⁶. 19 cm -3 ~1*10 22 cm -3 Furthermore, the thickness of the collector region n+ substrate layer 10 is 100μm to 1μm.
[0036] Step 2: Fabricate a collector region n0 epitaxial layer 20 on the collector region n+ substrate layer 10. The material of the collector region n0 epitaxial layer 20 is n-type SI-P, and its n0 doping concentration is 1*10⁻⁶. 14 cm -3 ~1*10 16 cm -3 Furthermore, the thickness of the epitaxial layer 20 in the collector region n0 is 100μm-200μm.
[0037] Step 3: Perform p-type impurity diffusion on the surface of the collector region n0 epitaxial layer 20 to form a p+ base layer 30. The material of the p+ base layer 30 is p-type SI-B, and its p+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 Furthermore, the thickness of the p+ base layer 30 is 5 μm to 20 μm, and the surface area is 1 μm². 2 ~100cm 2 .
[0038] Step 4: Perform n+ type impurity diffusion in the p+ base layer 30 to form the n+ emitter layer 40. The material of the n+ emitter layer 40 is n-type SI-P, and its n+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 Furthermore, the thickness of the n+ emitter layer 40 is 1 μm to 10 μm, and its surface area is 1 μm². 2 ~100cm 2 .
[0039] Step 5: Fabricate an annular deep well structure 50 around the p+ base layer 30. The inner ring of the deep well structure 50 is close to the curved boundary of the p+ base layer 30. The width of the deep well structure 50 is 10μm to 20μm and the thickness is 100μm to 200μm. The filling material of the deep well structure 50 is SiO2-Si3N4. The bottom of the deep well structure 50 is the junction between the collector region n0 epitaxial layer and the collector region n+ substrate layer.
[0040] Step 6: Cover the surface of the epitaxial layer 20 in the collector region n0 with a SiO2 oxide layer 60, the thickness of which is 5μm to 10μm.
[0041] Step 7: Cover the surface of the n+ emitter layer 40 with an oxygen-doped semi-insulating polycrystalline silicon layer 80. The oxygen content of the oxygen-doped semi-insulating polycrystalline silicon layer is 25% to 30%, and the thickness of the oxygen-doped semi-insulating polycrystalline silicon layer 80 is 5 μm to 10 μm.
[0042] Step 8: Fabricate a metal field plate structure 70 on top of the SiO2 oxide layer and the oxygen-doped semi-insulating polycrystalline silicon layer. The material of the metal field plate structure 70 is Al.
[0043] Step 9: Fabricate a base electrode 92 and an emitter electrode 94 on the metal field plate structure 70. The base electrode 92 is deposited sequentially with metals Al and Au. The metal field plate structure 70 is connected to the base electrode 92 and covers the SiO2 oxide layer 60 and the oxygen-doped semi-insulating polycrystalline silicon layer 80. The bottom of the metal field plate structure 70 passes through the SiO2 oxide layer 60 and the oxygen-doped semi-insulating polycrystalline silicon layer 80 and contacts the p+ base layer 30. The thickness is 0.5 μm to 50 μm. The emitter electrode 94 is deposited sequentially with metals Al and Au. The bottom of the emitter electrode 94 passes through the oxygen-doped semi-insulating polycrystalline silicon layer 80 and contacts the n+ emitter layer 40. The thickness is 0.5 μm to 50 μm.
[0044] Step 10: The collector region electrode 90 is formed by sequentially depositing metals Al and Au on the bottom of the collector region n+ substrate layer 10, with a thickness of 0.5 μm to 50 μm.
[0045] To verify the withstand voltage effect and turn-on effect of the ultrafast avalanche transistor suitable for voltage pulse triggering provided by this invention, the following settings were configured: Figure 4 The application circuit shown includes a collector-limiting current resistor R2, a base-limiting current resistor R3, an ultrafast avalanche transistor Q1 suitable for voltage pulse triggering (provided in this embodiment), and a load R1, all connected in sequence by wires. An energy storage capacitor C is also connected between the load R1 and the avalanche transistor Q1. Utilizing capacitor energy storage, a high voltage is applied to the avalanche transistor Q1 at the collector-limiting current resistor R2. The energy storage capacitor C, the deep-well avalanche transistor Q1, and the load R1 form a discharge circuit, turning on the avalanche transistor Q1 and outputting a high-voltage pulse to the load R1.
[0046] Figure 5 The voltage-current-voltage curves of the ultrafast avalanche transistor suitable for voltage pulse triggering and the conventional avalanche transistor provided by this invention are shown below. Figure 5 The curve Q1 in the middle represents the voltage and current waveform of the ultrafast avalanche transistor Q1 suitable for voltage pulse triggering provided by this invention. Figure 5 The curve Q2 serves as a control group, representing the voltage and current waveforms of a conventional avalanche transistor. Figure 5 As can be seen from curves Q1 and Q2, the withstand voltage of the ultrafast avalanche transistor suitable for voltage pulse triggering provided by this invention is significantly improved.
[0047] Figure 6 The present invention provides voltage pulse triggering turn-on characteristic curves for an ultrafast avalanche transistor suitable for voltage pulse triggering and a conventional avalanche transistor, wherein... Figure 6The curve Q1 represents the turn-on voltage waveform of the ultrafast avalanche transistor Q1, which is suitable for voltage pulse triggering, provided by this invention. Figure 5 The curve Q2 represents the turn-on voltage waveform of a traditional avalanche transistor as a control group. Figure 6 As can be seen from curves Q1 and Q2, the ultrafast avalanche transistor provided by this invention, which is suitable for voltage pulse triggering, can achieve a higher voltage value when triggered by voltage pulse, significantly improves dv / dt withstand capacity, and significantly improves turn-on speed when triggered by voltage pulse.
[0048] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. An ultrafast avalanche transistor suitable for voltage pulse triggering, characterized in that, The device comprises, from bottom to top, a collector region electrode, a collector region n+ substrate layer, a collector region n0 epitaxial layer, a p+ base region layer, and an n+ emitter region layer. A ring-shaped deep well structure is provided next to the p+ base region layer, with the inner ring of the deep well structure positioned close to the curved boundary of the p+ base region layer. The bottom of the deep well structure is the junction of the collector region n0 epitaxial layer and the collector region n+ substrate layer. The deep well structure uses SiO2-Si3N4 as the passivation material. An oxygen-doped semi-insulating polycrystalline silicon layer is covered on the n+ emitter region layer, and the oxygen doping content of the oxygen-doped semi-insulating polycrystalline silicon layer is 25% to 30%. The ultrafast avalanche transistor further includes a circular base electrode and an emitter electrode. The surface of the collector region n0 epitaxial layer is covered with an oxide layer, and a metal field plate is covered on the oxide layer. The metal field plate is in contact with the base electrode and the oxygen-doped semi-insulating polysilicon layer, respectively. The bottom of the metal field plate penetrates the oxide layer and contacts the p+ base layer, and the bottom of the emitter electrode penetrates the oxygen-doped semi-insulating polysilicon layer and contacts the n+ emitter layer.
2. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The material of the n+ substrate layer in the collector region is n-type SI-P, and its n+ doping concentration is 1*10⁻⁶. 19 cm -3 ~1*10 22 cm -3 The thickness of the n+ substrate layer in the collector region is 100 μm to 1 μm.
3. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The material of the n0 epitaxial layer in the collector region is n-type SI-P, and its n0 doping concentration is 1*10⁻⁶. 14 cm -3 ~1*10 16 cm -3 Furthermore, the thickness of both the collector region n0 epitaxial layer and the deep well structure is 100μm to 200μm.
4. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The material of the p+ base layer is p-type SI-B, and its p+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 The p+ base region layer has a thickness of 5 μm to 20 μm and a surface area of 1 μm². 2 ~100cm 2 The width of the deep well structure is 10μm to 20μm.
5. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The material of the n+ emitter layer is n-type SI-P, and its n+ doping concentration is 1*10^6. 19 cm -3 ~1*10 22 cm -3 The thickness of the n+ emission region layer is 1μm to 10μm.
6. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The oxide layer is a SiO2 oxide layer, and the thickness of the oxide layer is 5μm to 10μm.
7. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The oxygen-doped semi-insulating polycrystalline silicon layer is a silicon oxide composite, and the thickness of the oxygen-doped semi-insulating polycrystalline silicon is 5μm to 10μm.
8. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The materials of the collector electrode, base electrode, and emitter electrode are all at least one metal selected from Al and Au, and the thickness of the collector electrode, base electrode, and emitter electrode is 0.5 μm to 50 μm.
9. The ultrafast avalanche transistor suitable for voltage pulse triggering according to claim 1, characterized in that, The material of the metal field plate is Al.
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