A high linearity gate voltage bootstrap switch based on three paths

Abstract

The present invention claims a high linearity gate voltage bootstrap switch based on three paths, belonging to the technical field of analog integrated circuit design. In order to prevent the source-substrate of the PMOS tube from being forward biased, the substrate end and the source are connected, but the N-well parasitic capacitance C is increased. nwell The first capacitor C1 and the PMOS tube M10 and the second capacitor C2 and the PMOS tube M11 are respectively combined into two main paths, and the third capacitor C3 and the PMOS tube M12 are combined into an auxiliary path. The substrate of the PMOS tube M10 and the substrate of the PMOS tube M7, the substrate of the PMOS tube M11 and the substrate of the PMOS tube M6 are all connected to the substrate of the PMOS tube M12. When the input signal is transmitted to the gate end of the switch tube through the two main paths, it can not only speed up the establishment of the gate end voltage, but also save the C nwell Load this link, and use the remaining auxiliary paths to drive C nwell , thereby improving the linearity of the overall circuit signal.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuit design, and in particular relates to a high-linearity gate voltage bootstrap switch based on three paths. Background Art

[0002] With the development of analog integrated circuits and the rapid growth of the communication and multimedia markets, digital signal processing technology has also developed rapidly and is in high demand. Because digital signals have the comprehensive advantages of strong anti-interference ability, easy integration, low power consumption and low cost, more and more analog signal processing is gradually replaced by digital signal technology. However, signals in the natural world usually exist in analog form, such as temperature, sound, etc., which are continuous analog signals. In order for these analog signals to be processed by digital systems, it is necessary to convert the analog signals that are continuous in time into discrete digital signals. The analog-to-digital converter (ADC), as an important bridge between analog signals and digital signals, is an indispensable part of integrated circuits.

[0003] The process of converting continuous input signals into DC signals in ADC is called sampling and holding, which is achieved by controlling the closing and closing of the sampling switch. The switches used for sampling are generally single-tube MOS switches, CMOS switches, and gate voltage bootstrap switches. Since the gate-source voltage of single-tube MOS switches and CMOS switches changes with the input signal, their on-resistance cannot be constant, resulting in nonlinearity in the sampling process. The traditional gate voltage bootstrap switch structure can effectively solve this problem, using capacitor charging and discharging to achieve the gate-source voltage of the switch tube being independent of the input signal, thereby improving the sampling linearity and speed.

[0004] Figure 1 This is the circuit structure diagram of the traditional gate voltage bootstrap switch, which includes a sampling switch tube M10, a bootstrap capacitor Cb and a MOS tube. Its working principle is:

[0005] Sampling stage: When the clock CLK is at a high level, the inverted signal CLKB of the clock signal is at a low level, the bootstrap switch is in the on state, and M8 is in the off state. At this time, M5, M6 and M9 are also in the on state, so that the voltage of node 2 follows the input signal Vin, and the voltage of node 1 will be pulled to VDD+Vin.

[0006] Holding stage: When the clock CLK is at a low level, the bootstrap switch is in the holding state, M7 and M8 are in the on state, so that the voltages of nodes 1 and 2 are pulled to GND. Therefore, at this time, M1 and M2 are also in the on state, and other MOS transistors remain in the off state, so that the capacitor C stores a charge of VDD·Cb. The gate of the bootstrap switch is pulled down to a low level, and the output Vout keeps the sampled voltage unchanged.

[0007] The on-resistance of the sampling switch can be expressed as:

[0008]

[0009] where is the carrier mobility, C ox is the gate oxide capacitance per unit area of ​​the sampling switch tube MSW, W / L is the width-to-length ratio of the sampling switch tube M10, V GS is the gate-source voltage of the sampling switch M10, V TH is the conduction threshold voltage of the sampling switch tube M10.

[0010] The gate voltage bootstrap switch makes the gate-source voltage Vgs of the sampling switch tube M10 fixed to VDD during the sampling phase, so that its on-resistance remains almost unchanged, reducing the nonlinear distortion caused by the change of Vgs of the sampling switch tube. However, the tube is not ideal, and there are various parasitic parameters, such as parasitic capacitance, which introduces nonlinear distortion and affects linearity. In order to prevent the source-body junction of PMOS transistors M2 and M5 from being forward biased, their body terminals are connected to the source instead of VDD. However, the N-well containing M2 and M5 adds a large nonlinear capacitance C to the V1 node. nwell Therefore, during the sampling period, C nwell The voltage V1 is modulated, and the voltage V1 modulates the conductance G5 of M5. Nonlinear C nwell And G5 modulates the gate voltage VG of the bootstrap switch tube, reducing the sampling linearity. Summary of the invention

[0011] The present invention aims to solve the above problems of the prior art. A high linearity gate voltage bootstrap switch based on three paths is proposed. The technical solution of the present invention is as follows:

[0012] A high linearity gate voltage bootstrap switch based on three paths, comprising:

[0013] A first capacitor C1, a second capacitor C2, a third capacitor C3, a load capacitor CL and a plurality of MOS transistors, wherein the MOS transistors include NMOS transistors M1, NMOS transistors M2, NMOS transistors M3, NMOS transistors M4, PMOS transistors M5, PMOS transistors M6, PMOS transistors M7, NMOS transistors M8, NMOS transistors M9, PMOS transistors M10, PMOS transistors M11, PMOS transistors M12 and a bootstrap switch transistor MSW, wherein the drain of the NMOS transistor M1 is connected to the source of the bootstrap switch transistor MSW and serves as the input end of the gate voltage bootstrap switch circuit; the NMOS transistors The gate of M1 is connected to the gate of NMOS tube M3, the source of NMOS tube M8, the drains of PMOS tube M6 and PMOS tube M7, the gate of NMOS tube M10, the gate of NMOS tube M11 and the gate of NMOS tube M12; the source of NMOS tube M1 is respectively connected to the negative ends of capacitors C1, C2 and C3, the drain of NMOS tube M2, the source of NMOS tube M3 and the source of NMOS tube M4; the source of NMOS tube M2 is connected to the ground, and the gate of NMOS tube M2 is connected to the gate of NMOS tube M9 and serves as the clock reverse signal of the gate voltage bootstrap switch;

[0014] The drain of the NMOS tube M3 is connected to the drain of the NMOS tube M4, the drain of the PMOS tube M5, the gate of the NMOS tube M6, and the gate of the NMOS tube M7; the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M5 and serves as the clock positive signal of the gate voltage bootstrap switch; the source of the NMOS tube M5 is connected to VDD; the source of the PMOS tube M6 is connected to the positive end of the second capacitor C2, and the substrate of the PMOS tube M6 is connected to the positive end of the third capacitor C3; the source of the PMOS tube M7 is connected to the positive end of the first capacitor C1, and the substrate of the PMOS tube M7 is connected to the positive end of the third capacitor C3; the drain of the NMOS tube M8 is connected to the source of the NMOS tube M9, and the substrate of the NMOS tube M8 is connected to VDD; the drain of the NMOS tube M9 is connected to the ground;

[0015] The drain of the PMOS tube M10 and the drains of the PMOS tubes M11 and M12 are all connected to VDD. The source of the PMOS tube M10 is connected to the source of the PMOS tube M7 and the positive end of the first capacitor C1, the gate of the PMOS tube M10 is connected to the drain of the PMOS tube M7, and the substrate of the PMOS tube M10 is connected to the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12; the source of the PMOS tube M11 is connected to the source of the PMOS tube M6 and the positive end of the second capacitor C2, and the substrate of the PMOS tube M11 is connected to the substrate of the PMOS tube M6 and the substrate of the PMOS tube M12; the source of the PMOS tube M12 is connected to the positive end of the third capacitor C3, the substrate of the PMOS tube M6, the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12;

[0016] The drain of the bootstrap switch tube MSW serves as a gate voltage bootstrap output signal terminal and is connected to the load capacitor CL, and its gate is connected to the gate of the NMOS tube M1; the substrates of the NMOS tubes M1, M2, M3, M4, M8, M9, and the bootstrap switch tube MSW are connected to the ground; the substrates of the PMOS tubes M5, M6, and M7 are connected to VDD.

[0017] The substrates of the PMOS transistor M6 , the PMOS transistor M7 , the PMOS transistor M10 , the PMOS transistor M11 , and the PMOS transistor M12 are connected together, and are all connected to the positive end of the third capacitor C3 .

[0018] Further, when CLK is at a high level and CLKB is at a low level, NMOS tube M4 is turned on, PMOS tube M6 and PMOS tube M7 are turned on, NMOS tube M1 is turned on, the voltage on the lower plate of the capacitor follows VIN, and the voltage on the upper plate of the capacitor is equal to Vin plus the voltage stored on the original capacitor; the bootstrap switch tube MSW is turned on, and the output voltage Vout is equal to the input voltage Vin; when CLK is at a low level and CLKB is at a high level, NMOS tube M2, NMOS tube M8, and NMOS tube M9 are turned on, the drain voltage of the NMOS tube drops to GND, the negative ends of the capacitors C1, C2, and C3 are grounded, and the positive ends of the capacitors C1, C2, and C3 are charged to VDD due to the conduction of PMOS tube M10, PMOS tube M11, and PMOS tube M12; the bootstrap switch tube MSW is disconnected because the gate voltage is grounded, and the output signal is in a holding state.

[0019] Furthermore, when CLK is at a high potential, the gate voltage bootstrap switch output Vout is equal to the input Vin; when CLK is at a low potential, the gate voltage bootstrap switch output Vout maintains the previous voltage unchanged.

[0020] The advantages and beneficial effects of the present invention are as follows:

[0021] The present invention provides a high linearity gate voltage bootstrap switch based on three paths. Figure 1 In order to prevent the source-body junction of the PMOS transistor from being forward biased, the substrates of the PMOS tubes M2 and M5 are connected to the source terminals of their own tubes instead of VDD, but this will increase the N-well parasitic capacitance C nwell Compared with the traditional gate voltage bootstrap switch circuit, in order to eliminate the N-well parasitic capacitance C nwellDue to the impact brought by the power supply, the bootstrap capacitor Cb is divided into C1, C2 and C3. In this way, two main signal paths consisting of the first capacitor C1 and the PMOS tube M10 and the second capacitor C2 and the PMOS tube M11 and an auxiliary signal path consisting of the third capacitor C3 and the PMOS tube M12 are formed. The substrate of the PMOS tube M10 and the substrate of the PMOS tube M7, as well as the substrate of the PMOS tube M11 and the substrate of the PMOS tube M6 are all connected to the substrate of the PMOS tube M12, which is the point V1. When the input signal is transmitted to the gate end of the switch tube through the two main paths, it can not only speed up the establishment of the gate end voltage, but also save the C nwell Load this link, and use the remaining auxiliary paths to drive C nwell Through these three paths, the linearity and driving strength of the signal can be optimized respectively. nwell This affects the on-resistance of the switch tube, leading to sampling nonlinearity problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is the schematic diagram of the traditional gate voltage bootstrap switch circuit;

[0023] Figure 2 It is a schematic diagram of a gate voltage bootstrap switch circuit based on three paths according to a preferred embodiment of the present invention;

[0024] Figure 3 It is a spectrum simulation diagram of a gate voltage bootstrap switch based on three paths according to a preferred embodiment of the present invention. DETAILED DESCRIPTION

[0025] The following will describe the technical solutions in the embodiments of the present invention in detail in conjunction with the accompanying drawings in the embodiments of the present invention. The described embodiments are only part of the embodiments of the present invention.

[0026] The technical solution of the present invention to solve the above technical problems is:

[0027] In a conventional gate voltage bootstrap switch, to prevent the source-body junction of PMOS transistors M2 and M5 from being forward biased, their body terminals are connected to the source instead of VDD. However, the N-well containing M2 and M5 adds a large nonlinear capacitance C to the V1 node. nwell Therefore, during the sampling period, C nwell The voltage V1 is modulated, and the voltage V1 modulates the conductance G5 of M5. Nonlinear C nwell And G5 modulates the gate voltage VG of the bootstrap switch tube, reducing the sampling linearity.

[0028] Based on this, in the embodiment of the present application, the bootstrap capacitor Cb is divided into C1, C2 and C3. In this way, two main signal paths consisting of the first capacitor C1 and the PMOS tube M10 and the second capacitor C2 and the PMOS tube M11 and an auxiliary signal path consisting of the third capacitor C3 and the PMOS tube M12 are formed. The substrate of the PMOS tube M10 and the substrate of the PMOS tube M7, as well as the substrate of the PMOS tube M11 and the substrate of the PMOS tube M6 are all connected to the substrate of the PMOS tube M12, which is the point V1. When the input signal is transmitted to the gate end of the switch tube through the two main paths, it can not only speed up the establishment of the gate end voltage, but also save the C nwell Load this link, and use the remaining auxiliary paths to drive C nwell Through these three paths, the linearity and driving strength of the signal can be optimized respectively. nwell This affects the on-resistance of the switch tube, leading to sampling nonlinearity problems.

[0029] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0030] like Figure 2 As shown, a gate voltage bootstrap switch based on three paths includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a load capacitor CL and a plurality of MOS tubes, characterized in that: the MOS tubes include NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, PMOS tube M5, PMOS tube M6, PMOS tube M7, NMOS tube M8, NMOS tube M9, PMOS tube M10, PMOS tube M11, PMOS tube M1 and a bootstrap switch tube MSW, the NMOS tube The drain of the S tube M1 is connected to the source of the bootstrap switch tube MSW and serves as the input end of the gate voltage bootstrap switch circuit; the gate of the NMOS tube M1 is connected to the gate of the NMOS tube M3, the source of the NMOS tube M8, the drains of the PMOS tubes M6 and M7, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M12; the source of the NMOS tube M1 is connected to the negative ends of C1, C2, C3, the drain of the NMOS tube M2, the source of the NMOS tube M3 and the source of the NMOS tube M4.

[0031] The source of the NMOS tube M2 is connected to the ground, and the gate of the NMOS tube M2 is connected to the gate of the NMOS tube M9 and serves as a clock reverse signal of the gate voltage bootstrap switch.

[0032] The drain of the NMOS tube M3 is connected to the drain of the NMOS tube M4, the drain of the PMOS tube M5, the gate of the NMOS tube M6, and the gate of the NMOS tube M7.

[0033] The gate of the NMOS transistor M4 is connected to the gate of the NMOS transistor M5 and serves as a clock positive signal of the gate voltage bootstrap switch.

[0034] The source of the NMOS tube M5 is connected to VDD.

[0035] The source of the PMOS transistor M6 is connected to the positive end of the third capacitor C2, and the substrate of the PMOS transistor M6 is connected to the positive end of the third capacitor C2.

[0036] The source of the PMOS transistor M7 is connected to the positive end of the first capacitor C1 , and the substrate of the PMOS transistor M7 is connected to the positive end of the third capacitor C2 .

[0037] The drain of the NMOS tube M8 is connected to the source of the NMOS tube M9, the substrate of the NMOS tube M8 is connected to VDD; the drain of the NMOS tube M9 is connected to the ground.

[0038] The drain of the PMOS tube M10 and the drains of the PMOS tubes M11 and M12 are all connected to VDD. The source of the PMOS tube M10 is connected to the source of the PMOS tube M7 and the positive end of the first capacitor C1, the gate of the PMOS tube M10 is connected to the drain of the PMOS tube M7, and the substrate of the PMOS tube M10 is connected to the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12.

[0039] The source of the PMOS tube M11 is connected to the source of the PMOS tube M6 and the positive end of the second capacitor C2, and the substrate of the PMOS tube M11 is connected to the substrate of the PMOS tube M6 and the substrate of the PMOS tube M12.

[0040] The source of the PMOS tube M12 is connected to the positive end of the third capacitor C3, the substrate of the PMOS tube M6, the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12.

[0041] The drain of the bootstrap switch tube MSW serves as a gate voltage bootstrap output signal terminal and is connected to the load capacitor CL, and the gate thereof is connected to the gate of the NMOS tube M1.

[0042] The substrates of the NMOS tube M1, NMOS tube M2, NMOS tube M3, NMOS tube M4, NMOS tube M8, NMOS tube M9 and the bootstrap switch tube MSW are connected to the ground.

[0043] The substrates of the PMOS tube M5 , the PMOS tube M6 , and the PMOS tube M7 are connected to VDD.

[0044] Further, when CLK is at a high level and CLKB is at a low level, NMOS tube M4 is turned on, PMOS tube M6 and PMOS tube M7 are turned on, NMOS tube M1 is turned on, the voltage on the lower plate of the capacitor follows Vin, and the voltage on the upper plate of the capacitor is equal to Vin plus the voltage stored on the original capacitor. The bootstrap switch tube (MSW) is turned on, and the output voltage Vout is equal to the input voltage Vin. When CLK is at a low level and CLKB is at a high level, NMOS tube M2, NMOS tube M8, and NMOS tube M9 are turned on, and the drain voltage of the NMOS tube drops to GND, the negative ends of C1, C2, and C3 are grounded, and the positive ends of C1, C2, and C3 are grounded due to the conduction of PMOS tube M10, PMOS tube M11, and PMOS tube M12, and the three capacitors are charged to VDD. The bootstrap switch tube MSW is disconnected because the gate voltage is grounded, and the output signal is in a hold state.

[0045] Furthermore, when CLK is at a high potential, the gate voltage bootstrap switch output Vout is equal to the input Vin; when CLK is at a low potential, the gate voltage bootstrap switch output Vout maintains the previous voltage unchanged.

[0046] Figure 3 It is the spectrum simulation curve of the gate voltage bootstrap switch circuit of the present invention, wherein the horizontal axis is the frequency in MHz and the vertical axis is the amplitude in dB. The simulation results show that when the input Vin is about 250MHz and the switching frequency is 500MHz, the signal-to-noise ratio reaches 92.85dB and the spurious-free dynamic range reaches 110.98dB.

[0047] In the above embodiment of the present application, a high linearity gate voltage bootstrap switch based on three paths includes: a bootstrap switch tube (MSW), a MOS tube (M1-M12), capacitors (C1, C2 and C3) and a load capacitor (CL). In the embodiment of the present application, two main paths consisting of a first capacitor C1 and a PMOS tube M10 and a second capacitor C2 and a PMOS tube M11 are used to accelerate the establishment of the gate voltage of the bootstrap switch tube MSW, while an auxiliary path consisting of a third capacitor C3 and a PMOS tube M12 is used to drive the nonlinear capacitor C nwell , reducing the impact on sampling. This allows high linearity of the bootstrap switch within the input range.

[0048] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0049] The above embodiments should be understood to be only used to illustrate the present invention and not to limit the protection scope of the present invention. After reading the contents of the present invention, technicians can make various changes or modifications to the present invention, and these equivalent changes and modifications also fall within the scope defined by the claims of the present invention.

Claims

1. A high linearity gate voltage bootstrap switch based on three paths, characterized in that: include: A first capacitor C1, a second capacitor C2, a third capacitor C3, a load capacitor CL and a plurality of MOS transistors, wherein the MOS transistors include NMOS transistors M1, NMOS transistors M2, NMOS transistors M3, NMOS transistors M4, PMOS transistors M5, PMOS transistors M6, PMOS transistors M7, NMOS transistors M8, NMOS transistors M9, PMOS transistors M10, PMOS transistors M11, PMOS transistors M12 and a bootstrap switch transistor MSW, wherein the PMOS transistors M10, PMOS transistors M11 and PMOS transistors M12 have the same size, and the first capacitor C1 and the second capacitor C2 and the third capacitor C3 have the same capacitance; the drain of the NMOS transistor M1 is connected to The source of the bootstrap switch tube MSW is used as the input end of the gate voltage bootstrap switch circuit; the gate of the NMOS tube M1 is connected to the gate of the NMOS tube M3, the source of the NMOS tube M8, the drains of the PMOS tubes M6 and M7, the gate of the NMOS tube M10, the gate of the NMOS tube M11 and the gate of the NMOS tube M12; the source of the NMOS tube M1 is respectively connected to the negative ends of the capacitors C1, C2, and C3, the drain of the NMOS tube M2, the source of the NMOS tube M3 and the source of the NMOS tube M4; the source of the NMOS tube M2 is connected to the ground, and the gate of the NMOS tube M2 is connected to the gate of the NMOS tube M9 and serves as a clock reverse signal of the gate voltage bootstrap switch; The drain of the NMOS tube M3 is connected to the drain of the NMOS tube M4, the drain of the PMOS tube M5, the gate of the NMOS tube M6, and the gate of the NMOS tube M7; the gate of the NMOS tube M4 is connected to the gate of the NMOS tube M5 and serves as the clock positive signal of the gate voltage bootstrap switch; the source of the NMOS tube M5 is connected to VDD; the source of the PMOS tube M6 is connected to the positive end of the second capacitor C2, and the substrate of the PMOS tube M6 is connected to the positive end of the third capacitor C3; the source of the PMOS tube M7 is connected to the positive end of the first capacitor C1, and the substrate of the PMOS tube M7 is connected to the positive end of the third capacitor C3; the drain of the NMOS tube M8 is connected to the source of the NMOS tube M9, and the substrate of the NMOS tube M8 is connected to VDD; the drain of the NMOS tube M9 is connected to the ground; The drain of the PMOS tube M10 and the drains of the PMOS tubes M11 and M12 are all connected to VDD; the source of the PMOS tube M10 is connected to the source of the PMOS tube M7 and the positive end of the first capacitor C1, the gate of the PMOS tube M10 is connected to the drain of the PMOS tube M7, and the substrate of the PMOS tube M10 is connected to the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12; the source of the PMOS tube M11 is connected to the source of the PMOS tube M6 and the positive end of the second capacitor C2, and the substrate of the PMOS tube M11 is connected to the substrate of the PMOS tube M6 and the substrate of the PMOS tube M12; the source of the PMOS tube M12 is connected to the positive end of the third capacitor C3, the substrate of the PMOS tube M6, the substrate of the PMOS tube M7 and the substrate of the PMOS tube M12; The drain of the bootstrap switch tube MSW serves as a gate voltage bootstrap output signal terminal and is connected to the load capacitor CL, and its gate is connected to the gate of the NMOS tube M1; the substrates of the NMOS tubes M1, M2, M3, M4, M8, M9, and the bootstrap switch tube MSW are connected to the ground; the substrates of the PMOS tubes M5, M6, and M7 are connected to VDD.

2. The three-path based high linearity gate voltage bootstrap switch according to claim 1, characterized in that: When CLK is at a high level and CLKB is at a low level, NMOS tube M4 is turned on, PMOS tube M6 and PMOS tube M7 are turned on, NMOS tube M1 is turned on, the voltage on the lower plate of the capacitor follows VIN, and the voltage on the upper plate of the capacitor is equal to Vin plus the voltage stored on the original capacitor; the bootstrap switch tube MSW is turned on, and the output voltage Vout is equal to the input voltage Vin; when CLK is at a low level and CLKB is at a high level, NMOS tubes M2, M8, and M9 are turned on, the drain voltage of the NMOS tube drops to GND, the negative ends of the capacitors C1, C2, and C3 are grounded, and the positive ends of the capacitors C1, C2, and C3 are charged to VDD due to the conduction of PMOS tubes M10, M11, and M12; the bootstrap switch tube MSW is disconnected because the gate voltage is grounded, and the output signal is in a holding state.

3. A three-path high linearity gate voltage bootstrap switch according to claim 2, characterized in that: When CLK is at a high potential, the gate voltage bootstrap switch output Vout is equal to the input Vin; when CLK is at a low potential, the gate voltage bootstrap switch output Vout maintains the previous voltage unchanged.

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