A high-speed SAR-ADC circuit with redundancy algorithm

Abstract

The application relates to a high-speed SAR-ADC circuit with a redundancy algorithm, comprising: a DAC array unit, which samples an input signal and completes a binary search algorithm by utilizing inter-capacitor charge redistribution; a dynamic comparator, which is used for comparing the size of a differential analog input signal, outputting a binary digital signal and completing quantization; a clock logic unit, which is used for providing a sample-and-hold clock, a reset clock and a synchronization clock, and the clock output end of the clock logic unit is connected with the DAC array unit, the comparator, the bit latch and the combination logic unit; and a combination logic unit, which controls signal switching of a capacitor array according to the output result of the comparator, completes conversion of redundant bits and buffers and outputs a quantization code. The application uses an asynchronous SAR-ADC architecture with redundancy, and since the asynchronous SAR-ADC is adopted, the time of each cycle can be fully utilized, the speed is improved, the redundancy method is used, the fault tolerance of conversion is improved, and the precision is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, in particular to a high-speed SAR-ADC circuit with redundancy algorithm. BACKGROUND

[0002] The speed and accuracy of ADC are a pair of contradictions, and the existing SAR-ADC mainly has two schemes of synchronous ADC and asynchronous ADC.

[0003] Synchronous ADC: each comparison period needs to involve a synchronous clock;

[0004] Among them, the problem of synchronous ADC:

[0005] The frequency of each comparison period is completely the same, but since the charging time required by each step is different, each period needs to meet the requirement of the maximum charging time, which leads to the waste of sampling time and limits the speed of ADC.

[0006] Asynchronous ADC: each comparison period automatically enters the next step after the result is output

[0007] Among them, the problem of asynchronous ADC:

[0008] Since the result of the comparator determines the arrival of the next period, it may enter the next comparison period before being fully charged, which affects the sampling accuracy. SUMMARY

[0009] To solve the above technical problems, the purpose of the present application is to provide a high-speed SAR-ADC circuit with redundancy algorithm.

[0010] To achieve the above purpose, the present application adopts the following technical scheme:

[0011] A high-speed SAR-ADC circuit with redundancy algorithm comprises:

[0012] A DAC array unit samples an input signal and completes a binary search algorithm by using charge redistribution between capacitors;

[0013] A dynamic comparator is used to compare the size of a differential analog input signal and output a binary digital signal to complete quantization, wherein the dynamic comparator comprises a comparator and a bit latch, an output end of the DAC array unit is connected with an input end of the comparator, an output end of the comparator is connected with an input end of the bit latch, and a latch end of the bit latch is connected with an input end of the DAC array unit;

[0014] A clock logic unit is used to provide a sample and hold clock, a reset clock and a synchronous clock, and a clock output end of the clock logic unit is connected with the DAC array unit, the comparator, the bit latch and a combination logic unit.

[0015] A combination logic unit controls the signal switching capacitor array according to the output result of the comparator, completes the conversion of the redundant bits and buffers the output quantization code, and the input end of the combination logic is connected with the output end of the bit latch.

[0016] Preferably, the high-speed SAR-ADC circuit with a redundancy algorithm, the sampling and holding clock of the clock logic unit is connected with the DAC array unit, the reset clock of the clock logic unit is connected with the comparator and the bit latch, and the synchronization clock of the clock logic unit is connected with the combination logic.

[0017] Preferably, the high-speed SAR-ADC circuit with a redundancy algorithm, the DAC array unit is composed of a binary arranged capacitor array with multiple redundant bits and switches.

[0018] Preferably, the high-speed SAR-ADC circuit with a redundancy algorithm, the unit capacitance C in the DAC array unit is provided with a parasitic capacitance between the metal and the metal, and the parasitic capacitance value is 1.5fF.

[0019] Preferably, the high-speed SAR-ADC circuit with a redundancy algorithm, the combination logic unit adopts a binary full adder algorithm.

[0020] Preferably, the high-speed SAR-ADC circuit with a redundancy algorithm, 10-bit parallel output is formed through the combination logic unit after the result of the comparator.

[0021] By the above scheme, the present application has at least the following advantages:

[0022] The present application uses an asynchronous SAR-ADC architecture with redundancy, and since the asynchronous SAR-ADC is used, the time of each cycle can be fully utilized, the speed is improved, and the redundancy method is used, the fault tolerance of conversion is improved, and the precision is improved.

[0023] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, and can be implemented according to the content of the specification, the following will be described in detail with the preferred embodiments of the present application and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical scheme of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments, it should be understood that the following drawings only show some embodiments of the present application, therefore should not be regarded as a limitation, for those skilled in the art, without creative labor, other related drawings can also be obtained according to these drawings.

[0025] Figure 1 is a structural schematic diagram of the application;

[0026] Figure 2 is a structural schematic diagram of the DAC array unit of the application. DETAILED DESCRIPTION

[0027] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application but not all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0028] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0029] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0030] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "vertical", "horizontal", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the product of the application is used, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0031] In addition, the terms "horizontal", "vertical" and the like do not mean that the components must be absolutely horizontal or vertical, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0032] In the description of the present application, it also needs to be explained that, unless otherwise explicitly specified and limited, the terms "arrange", "install", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected, it can be mechanically connected, or it can be electrically connected, it can be directly connected, or indirectly connected through an intermediate medium, it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0033] Embodiment

[0034] As shown in Figure 1 and Figure 2 , a high-speed SAR-ADC circuit with redundancy algorithm comprises:

[0035] The DAC array unit adopts and utilizes the charge redistribution between capacitors to complete the binary search algorithm for the input signal;

[0036] The dynamic comparator is used for comparing the size of the differential analog input signal, outputting a binary digital signal, completing quantization, and the dynamic comparator comprises a comparator and a bit latch, the output end of the DAC array unit is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the bit latch, and the latch end of the bit latch is connected with the input end of the DAC array unit;

[0037] The clock logic unit is used for providing a sample and hold clock, a reset clock and a synchronization clock, and the clock output end of the clock logic unit is connected with the DAC array unit, the comparator, the bit latch and the combination logic unit;

[0038] The combination logic unit controls the signal switching capacitor array according to the output result of the comparator, completes the conversion of the redundant bits and buffers the output quantization code, and the input end of the combination logic is connected with the output end of the bit latch.

[0039] In the present application, the sample and hold clock of the clock logic unit is connected with the DAC array unit, the reset clock of the clock logic unit is connected with the comparator and the bit latch, and the synchronization clock of the clock logic unit is connected with the combination logic.

[0040] The DAC array unit in the present application is composed of a binary arranged capacitor array with multiple redundant bits and switches.

[0041] In the present application, the parasitic capacitor is arranged between the unit capacitors C and the metal in the DAC array unit, and the parasitic capacitor value is 1.5fF.

[0042] The combination logic unit in the present application adopts a binary full adder algorithm.

[0043] The 10-bit parallel output is formed by the combination logic unit according to the result of the comparator.

[0044] The working principle of the present application is as follows:

[0045] In the specific working process of the present application, the DAC array unit works,

[0046] In the sampling stage, SH and SH' are closed, and VinP and VinN are charged to the positive and negative electrodes of the comparator respectively.

[0047] In the comparison stage, SH and SH' are opened, and the first comparison is performed. If VshP is greater than VshN, S12 is closed, otherwise S12' is closed. Then the next comparison is performed. If VshP is greater than VshN, S11 is closed, otherwise S11' is closed. Then, the 14 comparison results B1, B2…B14 are obtained in turn.

[0048] Finally, the 14 comparison results are output in parallel by the combination logic unit.

[0049] The combination logic unit satisfies the logical relationship, and D0-D9 are the final 10-bit output results, as shown in Table 1.

[0050] Table 1

[0051]

[0052] From the above Table 1, it can be inferred that:

[0053] D0=B14

[0054] D1=B9+B12+B13+the previous bit carry

[0055] D2=B8+B9+B10+B11+the previous bit carry

[0056] D3=B5+B7+B8+the previous bit carry

[0057] D4=B1+B4+B7+the previous bit carry

[0058] D5=B6+the previous bit carry

[0059] D6=B4+B5+the previous bit carry

[0060] D7=B1+B3+the previous bit carry

[0061] D8=B1+B2+the previous bit carry

[0062] D9=the previous bit carry

[0063] The above merely describes the preferred embodiments of the present application and is not intended to limit the present application. It should be pointed out that, for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present application, and these improvements and modifications should also be considered as falling within the protection scope of the present application.

Claims

1. A high speed SAR-ADC circuit with redundancy algorithm, characterized by, The application relates to a 10-bit parallel outputting quantization circuit, which comprises the following parts: a DAC array unit which samples an input signal and uses inter-capacitor charge redistribution to complete a binary search algorithm; a dynamic comparator which is used for comparing the size of a differential analog input signal, outputs a binary digital signal and completes quantization, wherein the dynamic comparator comprises a comparator and a bit latch, the output end of the DAC array unit is connected with the input end of the comparator, the output end of the comparator is connected with the input end of the bit latch, and the latch end of the bit latch is connected with the input end of the DAC array unit; a clock logic unit which is used for providing a sample-and-hold clock, a reset clock and a synchronous clock, wherein the clock output end of the clock logic unit is connected with the DAC array unit, the comparator, the bit latch and a combination logic unit; a combination logic unit which is used for controlling signal switching of a capacitor array according to the output result of the comparator, completing conversion of redundant bits and buffering and outputting a quantization code, wherein the input end of the combination logic is connected with the output end of the bit latch; the sample-and-hold clock of the clock logic unit is connected with the DAC array unit, the reset clock of the clock logic unit is connected with the comparator and the bit latch, and the synchronous clock of the clock logic unit is connected with the combination logic; the DAC array unit is composed of a binary-arranged capacitor array with multiple redundant bits and switches.

2. The high-speed SAR-ADC circuit with redundancy algorithm according to claim 1, characterized in that: The unit capacitor C of the DAC array unit is provided with a parasitic capacitor between metal and metal, and the parasitic capacitor value is 1.5 fF.

3. The high-speed SAR-ADC circuit with redundancy algorithm according to claim 1, characterized in that: The combination logic unit adopts a binary full-addition algorithm.

4. The high-speed SAR-ADC circuit with redundancy algorithm according to claim 3, characterized in that: The combination logic unit is used for forming 10-bit parallel outputting after the result of the comparator.

Images