Source synchronization system, calibration method, system on chip, component, device and medium

Abstract

The application provides a source synchronization system, a calibration method, a system on chip, a component, an equipment and a medium. The source synchronization system comprises a sending chip and a receiving chip; a transmitter of the sending chip and a receiver of the receiving chip are connected through a channel to form each Lane; a plurality of delay units are connected with each transmitter or each receiver respectively to adjust the delay of the Lane where the connected transmitter or receiver is located; a code type identifier is connected between the output ends of any data Lane and a standard Lane to detect the data phase relationship between the data Lane and the standard Lane; wherein the data Lane is a Lane used for data transmission in each Lane; and the standard Lane is a preselected data Lane. The application does not require the identified code type to be a fixed type, thereby reducing the dependence on the code type. Moreover, the scheme of the application requires a smaller layout area, thereby being beneficial to the miniaturization of the system.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a source synchronous system, calibration method, system on chip, components, equipment and medium. Background Art

[0002] like Figure 1 As shown, a source synchronous system consists of a transmitting chip, a cable (channel), and a receiving chip. The clock transmitter in the transmitting chip is connected to the clock receiver in the receiving chip via a channel, and the data transmitter in the transmitting chip is connected to the data receiver in the receiving chip via a channel (TX in the figure represents the transmitter, RX represents the receiver, CK represents the clock signal, and CKRX represents the clock receiver). During operation, the transmitter transmits a clock signal simultaneously with the data signal, and the two maintain a certain phase relationship. The receiving end uses this clock signal to sample the data signal. Because the routing, packaging, and layout of the transmitters, channels, and receivers in each lane (channel) vary, the delays between lanes vary, resulting in skew between data lanes and between data lanes and clock lanes. In long-distance and high-speed applications, this skew affects and limits the maximum transmission rate achievable by the system. Therefore, calibration is necessary to limit the skew to a small range to ensure that each lane receives and correctly processes the transmitted data simultaneously.

[0003] Currently, in order to achieve offset calibration, the Figure 2 This is achieved using the method shown in the figure. Specifically, based on the source synchronous system, a pattern generator or pattern memory (i.e., Pattern Gen / Memory in the figure) is added to each transmitter, and a pattern generator or pattern memory is added to the receiver, along with a pattern detection circuit (i.e., Pattern Checker in the figure; the MUX in the figure is a signal selector). Delay elements are inserted into the data signal path or clock signal path of each transmitter and / or receiver. Before calibration, a test pattern is agreed upon. During calibration, the transmitter transmits a test signal with this pattern, and the receiver receives data and compares the received data with the test pattern generated (or stored) by the pattern generator (or pattern memory) to determine whether the data transmitted in the system is correct. During this process, the optimal adoption point for each lane (i.e., the delay at which the lane can correctly receive data) is found by adjusting the delay element.

[0004] However, the method has a high dependence on the code type, and must be based on a determined or stored code type for correction. When the code type of the data actually transmitted by the source synchronous system is quite different from the code type used for calibration, the calibration result can have a large deviation. In addition, a code type generator or code type memory is needed in both the transmitter and the receiver, which occupies a large layout area, and is not conducive to system miniaturization. SUMMARY

[0005] Embodiments of the present application provide a source synchronous system, a skew calibration method, a system on chip, an electronic component, an electronic device and a computer readable storage medium, to solve the above problems.

[0006] Embodiments of the present application provide a source synchronous system, comprising: a transmitting chip and a receiving chip; the transmitter of the transmitting chip and the receiver of the receiving chip are connected through a channel to form each Lane; a plurality of delay units are connected to each of the transmitters or each of the receivers to adjust the delay of the Lane where the connected transmitter or receiver is located; a code type discriminator is connected between the output end of any data Lane and a standard Lane to detect the data phase relationship between the data Lane and the standard Lane; wherein the data Lane is a Lane in each of the Lanes used for data transmission; and the standard Lane is a pre-selected data Lane.

[0007] In the above implementation structure, the data phase between two Lanes (data Lane and standard Lane) is discriminated instead of the discrimination between the data received by the data Lane and the test code type generated (or stored) by the code type generator (or code type memory) in the prior art, so that the same code type is only needed to be transmitted by the two discriminated Lanes to realize the judgment of the skew in the two Lanes, without the need for the discriminated code type to be a fixed type, reducing the dependence on the code type, without the need for a preset test code type, and the calibration of the data code type actually transmitted by the source synchronous system can be performed, and the calibration result is more accurate. The scheme of the present application does not need to configure a code type generator (or code type memory) on both sides of each data Lane, nor does it need to configure a code type detection circuit for each data Lane, but only needs to set a code type discriminator between each data Lane and the standard Lane, so that the layout area required is smaller, which is conducive to system miniaturization.

[0008] Further, the code pattern identifier comprises: a data phase identification module, input ends of which are connected with output ends of the data Lane and the standard Lane respectively, and first and second output ends of which output first and second signals reflecting a data phase relationship between the data Lane and the standard Lane; a first D flip-flop and a second D flip-flop with reset function, a data input port of each of the first and second D flip-flops being used to access a reference voltage; a clock port of the first D flip-flop being connected with the first output end of the data phase identification module, and a reset port of the first D flip-flop being connected with the second output end of the data phase identification module; a clock port of the second D flip-flop being connected with the second output end of the data phase identification module, and a reset port of the second D flip-flop being connected with the first output end of the data phase identification module; a third D flip-flop and a fourth D flip-flop, data input ports of each of the third and fourth D flip-flops being used to access the reference voltage; a clock port of the third D flip-flop being connected with a data output port of the first D flip-flop; and a clock port of the fourth D flip-flop being connected with a data output port of the second D flip-flop.

[0009] In the above implementation, the two D flip-flops (i.e., the first and second D flip-flops) with reset function can eliminate glitches in the signals output by the data phase identification module, so that the signals output by the third and fourth D flip-flops can more accurately reflect the phase relationship between the data in the two Lanes.

[0010] Further, the data phase identification module is a frequency discriminator or a phase discriminator.

[0011] In the above implementation, the data phase identification module is implemented by a frequency discriminator or a phase discriminator. Then, since the frequency discriminator or the phase discriminator only needs two flip-flops at least, the code pattern identifier only needs six flip-flops at least, which can effectively reduce the cost and the layout area.

[0012] Further, the standard Lane is a preset data Lane specially used for offset calibration between the Lanes.

[0013] In the above implementation, by setting the standard Lane specially used for offset calibration between the Lanes, even in the normal use process of the source synchronous system (i.e., in the process of normal data transmission of the data Lane), the calibration of a certain data Lane in the normal use process can be realized by configuring the same data for the standard Lane as a certain data Lane.

[0014] The embodiment of the present application further provides a skew calibration method applied to the source synchronous system, the method comprising: obtaining a clock signal delay when data in the standard Lane can be stably sampled; determining an optimal sampling point of the standard Lane according to the clock signal delay; and determining an optimal sampling point of each data Lane according to the clock signal delay and the optimal sampling point of the standard Lane.

[0015] Through the above implementation, the clock signal delay and the optimal sampling point of each data Lane can be determined based on the source synchronous system, so that each data Lane can correctly receive data.

[0016] Further, the source synchronous system further comprises a clock Lane for transmitting a clock signal; the obtaining of the clock signal delay when data in the standard Lane can be stably sampled comprises: setting a delay of the standard Lane as a maximum skew of the source synchronous system; and adjusting the delay of each data Lane and the delay of the clock Lane alternately in a delay range of the data Lane until the delay of the clock Lane when a phase conversion relationship between a target data Lane and the standard Lane meets a preset relationship is obtained; the target data Lane is any data Lane; and the delay of the clock Lane is the clock signal delay.

[0017] The preset relationship is that the phase of the target data Lane and the standard Lane is the same, and after the delay of the target data Lane is increased by one unit time interval UI, the output of the pattern discriminator meets a first combination, and after the delay of the target data Lane is reduced by one UI, the output of the pattern discriminator meets a second combination.

[0018] In the above implementation process, by setting the delay of the standard Lane as the maximum skew of the source synchronous system, it can be ensured that there is a data Lane having the same phase as the standard Lane after adjusting the delay. Through the judgment of whether the preset relationship is met, it can be judged whether the data receiver samples according to the clock signal in a stable region of data or in an edge region, so that the clock signal delay which can make the data in the stable region can be accurately determined.

[0019] Further, the optimal sampling point of the standard Lane is determined according to the clock signal delay; the delay of the target data Lane and the clock Lane is kept, the delay of the standard Lane is adjusted in turn within a range of plus or minus one UI of the maximum offset of the source synchronous system, so as to obtain a standard Lane delay range in which the phase conversion relationship between the target data Lane and the standard Lane meets the preset relationship; and the optimal sampling point of the standard Lane is determined according to the standard Lane delay range.

[0020] In the implementation manners described above, the data stable region (i.e., the standard Lane delay range) in which data sampling is performed in the standard Lane can be accurately found through the judgment of whether the preset relationship is met, so that the optimal sampling point of the standard Lane can be quickly obtained.

[0021] Further, the optimal sampling point of the standard Lane is determined according to the standard Lane delay range, including: determining the median value of the standard Lane delay range as the optimal sampling point of the standard Lane.

[0022] In the implementation manners described above, by taking the median value of the standard Lane delay range as the optimal sampling point of the standard Lane, sufficient margin can be left when alignment is performed, and the risk of collecting data in a critical region in the transmission process can be reduced.

[0023] Further, the optimal sampling point of each data Lane is determined according to the clock signal delay and the optimal sampling point of the standard Lane, including: for each data Lane, keeping the clock signal delay and the optimal sampling point of the standard Lane unchanged, adjusting the delay of the data Lane in turn within a maximum delay range of the data Lane, until a delay K is obtained in which the phase of the data Lane is the same as that of the standard Lane; adjusting the delay of the data Lane in turn within a range of plus or minus one UI of the delay K, so as to obtain a data Lane delay range in which the phase conversion relationship between the data Lane and the standard Lane meets a preset relationship; and determining the optimal sampling point of the data Lane according to the data Lane delay range.

[0024] The preset relationship is that the phase of the data Lane is the same as that of the standard Lane, and after the delay of the data Lane is increased by one UI, the output of the pattern discriminator meets a first combination, and after the delay of the data Lane is reduced by one UI, the output of the pattern discriminator meets a second combination.

[0025] In the implementation process, the delay K is first found, which makes the phases of the data Lane and the standard Lane same, then the delay of the data Lane is adjusted in the range of plus or minus one UI of the delay K, and the data Lane delay range, which makes the phase conversion relationship between the data Lane and the standard Lane meet the preset relationship (i.e., the data stable region in the data Lane when data sampling is performed) is obtained, so that the optimal sampling point of the data Lane can be quickly obtained.

[0026] Further, the optimal sampling point of the data Lane is determined according to the data Lane delay range, including: determining the median value of the data Lane delay range as the optimal sampling point of the data Lane.

[0027] In the implementation manner, by taking the median value of the data Lane delay range as the optimal sampling point of the data Lane, when alignment is performed, sufficient margin can be left, and the risk of collecting data in the critical region in the transmission process is reduced.

[0028] Further, the standard Lane is a preset data Lane specially used for offset calibration between the Lanes; the method further includes: in the data transmission process, synchronizing the data in the data Lane to be calibrated in the standard Lane for transmission; re-determining the optimal sampling point of the standard Lane according to the clock signal delay; and determining the optimal sampling point of each data Lane to be calibrated according to the clock signal delay and the re-determined optimal sampling point of the standard Lane.

[0029] Through the implementation manner, the calibration of a data Lane in the normal use process (i.e., in the data transmission process) of the source synchronous system can be realized, so that the application embodiment has a wider application scenario.

[0030] The application embodiment further provides a system on chip, including the source synchronous system of any one of the above.

[0031] The application embodiment further provides a system on chip, including a controller and the source synchronous system of any one of the above; the controller is used for executing a preset program or programs to execute the method of any one of the above.

[0032] The application embodiment further provides an electronic component, including the system on chip of any one of the above.

[0033] The application embodiment further provides an electronic device, including the system on chip of any one of the above, or including the electronic component.

[0034] The embodiment of the present application further provides a computer readable storage medium, which stores one or more programs, and the one or more programs can be executed by one or more controllers to implement any of the above methods. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments of the present application, and it should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation to the scope, and for those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0036] Figure 1 It is a structural schematic diagram of a source synchronization system of the most basic source synchronization system;

[0037] Figure 2 It is a structural schematic diagram of a source synchronization system provided by the prior art;

[0038] Figure 3 It is a structural schematic diagram of a source synchronization system provided by the embodiment of the present application;

[0039] Figure 4 It is a clock sampling schematic diagram provided by the embodiment of the present application;

[0040] Figure 5 It is a structural schematic diagram of a code type identifier provided by the embodiment of the present application;

[0041] Figure 6 It is a waveform schematic diagram of a code type identifier provided by the embodiment of the present application;

[0042] Figure 7 It is a transition schematic diagram of three output states provided by the embodiment of the present application;

[0043] Figure 8 It is a flow schematic diagram of an offset calibration method provided by the embodiment of the present application;

[0044] Figure 9 It is a specific implementation flow schematic diagram of step S801 provided by the embodiment of the present application;

[0045] Figure 10 It is a specific implementation flow schematic diagram of step S802 provided by the embodiment of the present application;

[0046] Figure 11 It is a specific implementation flow schematic diagram of step S803 provided by the embodiment of the present application;

[0047] Figure 12A schematic diagram of a specific implementation process of offset calibration during use provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application.

[0049] In order to solve the problem that the existing technology has a very high code type dependence and requires a large layout area, a new source synchronization system is provided in the embodiment of the present application. Figure 3 As shown, Figure 3 The schematic diagram of the basic structure of the source synchronous system provided in the embodiment of the present application includes a transmitting chip and a receiving chip. The transmitter of the transmitting chip and the receiver of the receiving chip are connected by channels to form lanes.

[0050] It should be noted that in actual applications, the transmitting chip will have multiple data transmitters TX, which are connected to the data receiver RX in the receiving chip to form a data lane for data transmission. In addition, the transmitting chip will also have a clock transmitter CLKTX, which is connected to the clock receiver CLKRX in the receiving chip to form a clock lane for clock signal transmission. Figures 1 to 3 As shown, the clock signal transmitted by the clock Lane will be used in each data Lane for data sampling.

[0051] The so-called data sampling means that the data receiver RX will collect data according to the cycle of the clock signal. Figure 4 As shown, Figure 4 The data before and after sampling is shown. The part marked as "XXX" represents the critical area of ​​the two data. The data in this area is in a random state. When sampled, the sampled data may be the earlier data or the later data, such as Lane 0.

[0052] In the embodiment of the present application, the source synchronous system further includes a plurality of delay units Delay, each of which is connected to each transmitter or each receiver to adjust the delay of the Lane where the connected transmitter or receiver is located.

[0053] It should be understood that Figure 3 The figure shows a method for setting a delay unit for each transmitter in the transmitting chip. In practical applications, a delay unit can also be set for each receiver in the receiving chip, or a delay unit can be set for each transmitter in the transmitting chip and for each receiver in the receiving chip. All of these methods can achieve delay control for lanes.

[0054] It should also be understood that the delay units described in the embodiments of the present application can be implemented in any structure that can realize delay control, and the embodiments of the present application do not make any limitation.

[0055] As shown in Figure 3 In the embodiments of the present application, a code discriminator is further included in the source synchronous system and connected between the output end of any data Lane and the output end of a standard Lane (i.e. the Training Lane in the drawings) to detect the data phase relationship between the data Lane and the standard Lane. The standard Lane is a data Lane selected in advance.

[0056] It should be noted that in the embodiments of the present application, the standard Lane can be a data Lane specially set in advance for performing offset calibration between the Lanes. That is, the standard Lane can be a data Lane used only for performing offset calibration, and the standard Lane does not participate in actual data transmission during use of the source synchronous system. In this way, since the standard Lane does not participate in actual data transmission, the same data as a certain data Lane can be transmitted by the standard Lane during actual use of the source synchronous system, so that offset calibration of the data Lane during actual use can be realized.

[0057] Of course, in the embodiments of the present application, the standard Lane can also be a Lane selected from the data Lanes participating in actual data transmission, instead of being specially set. At this time, the standard Lane can be selected in advance, for example Figure 3 In the embodiments of the present application, the second Lane from top to bottom in

[0058] In the embodiments of the present application, as shown in Figure 5 The code discriminator can include a data phase discrimination module, a first D flip-flop and a second D flip-flop with reset function, and a third D flip-flop and a fourth D flip-flop which can have or can not have reset function. Wherein:

[0059] The input end of the data phase discrimination module is connected with the output end of one data Lane and the output end of the standard Lane respectively, and outputs a first signal PU and a second signal PD reflecting the data phase relationship between the data Lane and the standard Lane through a first output end and a second output end.

[0060] For example, the data phase identification module can be implemented by a frequency discriminator or a phase discriminator, but not as a limitation.

[0061] The data input ports of the first D flip-flop, the second D flip-flop, the third D flip-flop and the fourth D flip-flop are connected to a reference voltage.

[0062] The clock port of the first D flip-flop is connected to the first output of the data phase identification module, and the reset port of the first D flip-flop is connected to the second output of the data phase identification module.

[0063] The clock port of the second D flip-flop is connected to the second output of the data phase identification module, and the reset port of the second D flip-flop is connected to the first output of the data phase identification module.

[0064] The clock port of the third D flip-flop is connected to the data output port of the first D flip-flop.

[0065] The clock port of the fourth D flip-flop is connected to the data output port of the second D flip-flop.

[0066] In this way, the glitches in the signal output by the data phase identification module can be eliminated by the two D flip-flops with reset function (i.e. the first D flip-flop and the second D flip-flop), so that the signal output by the third D flip-flop and the fourth D flip-flop can more accurately reflect the phase relationship of the data in the two Lanes.

[0067] For the convenience of understanding the working principle of the code type identifier in the embodiments of the present application, the output result of the code type identifier is described below in the case that a data phase identification module is a frequency discriminator, and the phase relationship detection is performed in the rising edge detection mode.

[0068] Please refer to Figure 6 (Note that, considering that there is a certain delay in the transmission of the signal between the code type identifier and the flip-flops, the rising edge of the TCK (the signal output by the receiver of the standard Lane or the data Lane) is delayed by a certain time, and the rising edge of the RCK (the signal output by the receiver of the data Lane or the standard Lane) is also delayed by a certain time) Figure 6 As shown in FIG. 6, when the rising edge of the TCK (the signal output by the receiver of the standard Lane or the data Lane) comes first, the PD outputs a jump to 1 and keeps until the rising edge of the RCK (the signal output by the receiver of the data Lane or the standard Lane) comes, and the PU only appears a high pulse when the rising edge of the RCK comes, and the pulse width is related to the design of the frequency discriminator.

[0069] When the rising edge of RCK comes first, PU outputs a jump to 1 and keeps until the rising edge of TCK comes, PD only appears a high pulse at the rising edge of TCK, the pulse width is related to the design of frequency discriminator.

[0070] The first D flip-flop and the second D flip-flop with reset function, after reset, the output is 0, so that the pulse (for example Figure 6 in the dashed box) generated by the rising edge of one of PU and PD arriving later than the rising edge of the other of PU and PD is eliminated, that is, only the pulse related to the rising edge delay of TCK and RCK is retained in the output PUO and PDO of the frequency discriminator.

[0071] Finally, PUO and PDO are respectively used as the clock signals of the third D flip-flop and the fourth D flip-flop, to detect whether the rising edge has occurred in the entire identification range. If it has occurred, the corresponding DN and UP outputs 1 and keeps until the identification time ends.

[0072] At the end of the identification period: if DN is 1, it indicates that the phase of TCK is earlier than that of RCK in the entire identification time range; UP is 1, it indicates that the phase of TCK is later than that of RCK in the identification period; DN and UP are both 0, it indicates that the rising edges of the two data are completely the same.

[0073] The truth table of the entire code pattern discriminator is shown in Table 1 below:

[0074] Table 1

[0075] Same phase TCK is 1 UI earlier than RCK TCK is 1 UI later than RCK UP 0 0 1 DN 0 1 0

[0076] Therefore, based on the identification of the above code pattern discriminator, for the two Lanes connected to the code pattern discriminator, if the data received by the two Lanes are the same and the phase difference is 1 UI or 0, then the identification result can be switched between DN = UP = 0 and DN = 1, UP = 0 or DN = 0, UP = 1 by increasing or decreasing the delay relationship of the two Lanes by 1 UI, as shown in Figure 7 Similarly, by increasing or decreasing the delay relationship of the two Lanes by 1 UI, it can be judged whether the data receiver samples according to the clock signal in the stable region of the data (for example Figure 4 Training Lane, Lane1, Lane2 and LaneN in Figure 4 ) or in the edge region (for example Lane0 in

[0077] It should be understood that, in the embodiments of the present application, in addition to the detection based on the rising edge described above, the detection based on the falling edge or the detection based on both the rising edge and the falling edge can also be performed, and the difference brought by this is only that the truth table can be adaptively changed, but the principle is consistent.

[0078] Based on the source synchronization system provided in the embodiments of the present application, a method for implementing offset calibration for the source synchronization system is further provided in the embodiments of the present application.

[0079] Please refer to Figure 8 As shown in the figure, the method comprises:

[0080] S801: Obtain the clock signal delay when data in a standard Lane can be stably sampled.

[0081] It should be noted that, when performing offset calibration between the Lanes, the same data signal is transmitted in each data Lane (including the standard Lane), for example Figure 4 As shown in the figure, D0-D1-D2-D3 are all transmitted.

[0082] In the embodiments of the present application, the delay of the standard Lane can be set as the maximum offset of the source synchronization system, and then the delay of each data Lane and the delay of the clock Lane are adjusted in turn within the delay range of the data Lane, until the delay of the clock Lane (the delay of the clock Lane is the clock signal delay) when the phase conversion relationship between the target data Lane and the standard Lane meets the preset relationship is obtained. The target data Lane is any data Lane.

[0083] The maximum offset of the source synchronization system can be obtained by obtaining the design index of the source synchronization system.

[0084] The preset relationship is that the phase of the target data Lane and the standard Lane is the same, and after the delay of the target data Lane is increased by one UI, the output of the pattern discriminator conforms to the first combination, and after the delay of the target data Lane is reduced by one UI, the output of the pattern discriminator conforms to the second combination.

[0085] Taking the examples shown in Table 1 and Figure 7 As shown in the examples, assuming that the output of the target data Lane is TCK, the preset relationship is that the initial state is DN=UP=0 (i.e., the phase of the target data Lane and the standard Lane is the same), after the delay of the target data Lane is increased by one UI, DN=1, UP=0, and after the delay of the target data Lane is reduced by one UI, DN=0, UP=1.

[0086] It should be understood that in the embodiments of the present application, the adjustment of the delay of each data Lane and the delay of the clock Lane can be achieved by dichotomous scanning or sequential scanning, but is not limited thereto.

[0087] S802: The optimal sampling point of the standard Lane is determined according to the clock signal delay.

[0088] In this step, the delays of the target data Lane and the clock Lane are kept unchanged, the delay of the standard Lane is adjusted in turn within the range of plus or minus one UI of the maximum offset of the source synchronous system, and the range of the delay of the standard Lane that makes the phase conversion relationship between the target data Lane and the standard Lane meet the preset relationship is obtained, and then the optimal sampling point of the standard Lane is determined according to the range of the delay of the standard Lane.

[0089] For example, the median of the range of the delay of the standard Lane can be determined as the optimal sampling point of the standard Lane.

[0090] S803: The optimal sampling point of each data Lane is determined according to the clock signal delay and the optimal sampling point of the standard Lane.

[0091] In this step, for each data Lane:

[0092] The clock signal delay and the optimal sampling point of the standard Lane are kept unchanged, the delay of the data Lane is adjusted in turn within the range of the maximum offset of the source synchronous system, and the delay K that makes the phase of the data Lane and the standard Lane the same is obtained.

[0093] Then, the delay of the data Lane is adjusted in turn within the range of plus or minus one UI of the delay K, and the range of the delay of the data Lane that makes the phase conversion relationship between the data Lane and the standard Lane meet the preset relationship is obtained.

[0094] Finally, the optimal sampling point of the data Lane is determined according to the range of the delay of the data Lane. For example, the median of the range of the delay of the data Lane can be determined as the optimal sampling point of the data Lane.

[0095] To facilitate the understanding of the above method of the embodiments of the present application, the following takes the case shown in Table 1 as an example to illustrate the scheme of the embodiments of the present application: Figure 7

[0096] ​Assuming the maximum offset between each data Lane is N*UI, the delay of the clock Lane (i.e. CLK Lane) and each data Lane (i.e. Data Lane) can be adjusted in a minimum step of UI / M between 0 and (N+1)UI. Wherein, UI / M can be any value that can be executed by the delay unit set by the engineer, i.e. M can be a constant value set by the engineer.

[0097] For step S801: first, the delay of the standard Lane (i.e. Training Lane) can be set to N*UI, and then fixed. Then, in the range of 0~(N+1)UI and 0~1*UI, the delay of each data Lane and the delay of the clock Lane are scanned alternately by bisection method to find at least one data Lane whose received data is the same as that of the standard Lane, whose phase is the same, and whose detection result can correctly switch between UP=DN=0 and UP=0, DN=1 or UP=1, DN=0 after increasing or decreasing the delay of the data Lane by 1*UI, then the sampling point of the clock is located in the stable region of the standard Lane and the data Lane; in this process, as long as any data Lane satisfying the above relationship is found, this stage ends. The specific implementation process can be referred to Figure 9 As shown, comprising:

[0098] First, set the delay of the Training Lane from 0→N*UI, then set the delay of the Data Lane to 0, update the delay of the Data Lane, and set the delay of the Clock Lane (i.e. CLK Lane) to 0, update the delay of the Clock Lane. Then enter the delay update phase of the Data Lane:

[0099] Detect the phase relationship between each Data Lane and the Training Lane:

[0100] First, determine whether the relationship between the Data Lane and the Training Lane satisfies UP=DN=0? If yes, decrease the delay of the Data Lane by 1UI, then determine whether the phase relationship between the Data Lane and the Training Lane is UP=1 and DN=0? If yes, save and record the delay relationship between the Training Lane and the corresponding Data Lane after increasing the delay of the Data Lane by 1UI, indicating that a data Lane satisfying the above relationship is found. If not, increase the delay of the Data Lane by 4UI and go to the (N+1)UI judgment logic.

[0101] If the phase relationship between the Data Lane and the Training Lane does not satisfy UP = DN = 0, then it is determined whether the phase relationship between the Data Lane and the Training Lane satisfies UP = 1 and DN = 0. If yes, the Data Lane is delayed by +1 UI, and then it is determined whether the phase relationship between the Data Lane and the Training Lane is UP = DN = 0. If yes, the delay relationship between the Training Lane and the corresponding Data Lane is saved and recorded, indicating that a data Lane satisfying the above relationship is found. If no, the Data Lane is delayed by +2 UI, and then the (N+1) UI judgment logic is entered.

[0102] If the phase relationship between the Data Lane and the Training Lane does not satisfy UP = 1 and DN = 0, then it is determined whether the phase relationship between the Data Lane and the Training Lane satisfies UP = 0 and DN = 1. If yes, the Data Lane is delayed by -1 UI, and then it is determined whether the phase relationship between the Data Lane and the Training Lane is UP = DN = 0. If yes, the delay relationship between the Training Lane and the corresponding Data Lane is saved and recorded, indicating that a data Lane satisfying the above relationship is found. If no, the Data Lane is delayed by +4 UI, and then the (N+1) UI judgment logic is entered.

[0103] If the phase relationship between the Data Lane and the Training Lane does not satisfy UP = 0 and DN = 1, then the Data Lane is delayed by +3 UI, and then the (N+1) UI judgment logic is entered.

[0104] The (N+1) UI judgment logic is: it is determined whether the data delay is greater than or equal to (N+1) UI. If no, the delay updating phase of the Data Lane is re-entered. If yes, the delay of the Data Lane is reduced by the delay accumulated in this round, and then it is determined whether the delay of the clock Lane is equal to (M-1) UI / M. If not equal, the delay updating of the clock Lane is performed according to the bisection method, and then the delay updating phase of the Data Lane is re-entered. If equal, it is determined whether the delay of the Data Lane is equal to (M-1) UI / M. If equal, the error is returned, and the flow is ended; if not equal, the delay of the Data Lane is updated according to the bisection method, and then the delay of the clock Lane is set to 0, and the delay updating phase of the Data Lane is re-entered.

[0105] It should be understood that, Figure 9The "Training Lane delay from 0→N*UI" means adjusting the delay of the standard Lane from 0 to N*UI.

[0106] For step S802: the delay of the data Lane and the clock Lane found in S801 can be kept unchanged, the delay of the standard Lane is adjusted from N*UI by bisection between (N-1)UI to N*UI and N*UI to (N+1)UI, the maximum delay and the minimum delay corresponding to DN=UP=0 are found, which can make the identification result correctly switch between UP=DN=0, UP=0, DN=1, UP=1, DN=0; the median of the maximum and minimum delay corresponding to DN=UP=0 is taken as the final delay of the standard Lane, that is, the best sampling point of the standard Lane. The specific implementation process can be referred to in Figure 10 As shown in the figure, comprising:

[0107] The delay of the data Lane and the clock Lane found in S801 can be fixed first, then the delay of the Training Lane is adjusted to -UI / 2, and then the phase relationship between the Training Lane and the data Lane found in step S801 is detected.

[0108] If the phase relationship satisfies UP=DN=0, it is judged whether the delay of the Training Lane has been adjusted to the maximum, if not, the delay of the Training Lane is reduced by bisection, and then the process of detecting the phase relationship between the Training Lane and the data Lane found in step S801 is re-entered. If yes, the delay of the Training Lane is recorded as the delay corresponding to the right edge of the Training Lane eye diagram, and then the process of finding the delay corresponding to the left edge of the Training Lane eye diagram is entered.

[0109] If the phase relationship does not satisfy UP=DN=0, it is also judged whether the delay of the Training Lane has been adjusted to the maximum, if not, the delay of the Training Lane is increased by bisection, and then the process of detecting the phase relationship between the Training Lane and the data Lane found in step S801 is re-entered. If yes, the delay of the Training Lane is added to the minimum adjustable delay, and then the adjusted delay of the Training Lane is recorded as the delay corresponding to the right edge of the Training Lane eye diagram, and then the process of finding the delay corresponding to the left edge of the Training Lane eye diagram is entered.

[0110] The process of finding the delay corresponding to the left edge of the Training Lane eye diagram comprises:

[0111] After delaying the Training Lane by (N+0.5)UI, the phase relationship between the Training Lane and the data Lane found in step S801 is detected.

[0112] If the phase relationship satisfies UP=DN=0, it is first determined whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is increased using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data Lane found in step S801 is re-entered. If yes, the delay of the Training Lane is recorded as the delay corresponding to the left edge of the Training Lane eye diagram.

[0113] If the phase relationship does not satisfy UP=DN=0, it is still first determined whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is decreased using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data Lane found in step S801 is re-entered. If yes, the delay of the Training Lane is subtracted by the minimum adjustable delay, and then the adjusted delay of the Training Lane is recorded as the delay corresponding to the left edge of the Training Lane eye diagram.

[0114] The median of the delays corresponding to the left and right edges of the Training Lane eye diagram is taken as the delay of the Training Lane, and the optimal sampling point of the Training Lane is obtained and recorded.

[0115] For step S803: for any data Lane:

[0116] The delay of the clock Lane determined in S801 and the optimal sampling point of the standard Lane determined in S802 can be kept unchanged, and first the sampling point at which the data Lane and the standard Lane have the same phase is found in the range of 0-(N+1)UI (i.e. the delay K). Specifically, the data Lane delay starts from 0, and in the range of 0-UI, the initial delay is set using the dichotomy, and after each initial delay, the delay value that can receive the same data and have the same phase with the standard Lane is searched in the range of 0-(N+1)UI with a step of 3UI. After the first matched delay value is found, the searching is stopped, and the delay value at this time is recorded as "delay K".

[0117] In (delay K-UI) to delay K, the delay of data Lane is adjusted by using dichotomy in the range of (delay K) to (delay K+UI), to find the maximum delay and minimum delay corresponding to DN=UP=0, which can make the identification result correctly switch between UP=DN=0, UP=0, DN=1, UP=1, DN=0.

[0118] Take the median of the maximum and minimum delay corresponding to DN=UP=0 as the final delay of data Lane, that is, the best sampling point of data Lane. For specific implementation process, please refer to Figure 11 As shown in the figure, it includes:

[0119] Determine that the Training Lane has reached the best sampling point, and fix the delay of the clock Lane. After setting the delay of the Data Lane to 0, enter the delay update phase of the Data Lane:

[0120] Detect the phase relationship between each Data Lane and the Training Lane. If the phase relationship satisfies UP=DN=0, then the Data Lane delay-1UI, and then detect whether the phase relationship between the Data Lane and the Training Lane is UP=1 and DN=0? If yes, the Data Lane delay+1UI, and then enter the best sampling point finding phase of the Data Lane. If not, the Data Lane delay+4UI, and then go to the (N+1)UI judgment logic.

[0121] If the phase relationship satisfies UP=1 and DN=0, then the Data Lane delay+1UI, and then detect whether the phase relationship between the Data Lane and the Training Lane is UP=DN=0? If yes, enter the best sampling point finding phase of the Data Lane. If not, the Data Lane delay+2UI, and then go to the (N+1)UI judgment logic.

[0122] If the phase relationship satisfies UP=0 and DN=1, then the Data Lane delay-1UI, and then detect whether the phase relationship between the Data Lane and the Training Lane is UP=DN=0? If yes, enter the best sampling point finding phase of the Data Lane. If not, the Data Lane delay+4UI, and then go to the (N+1)UI judgment logic.

[0123] If none of the above phase relationships is satisfied, then the Data Lane delay+3UI, and then go to the (N+1)UI judgment logic.

[0124] The (N+1)UI judgment logic includes: judging whether the data delay is greater than or equal to (N+1)UI? If not, re-enter the delay updating stage of the Data Lane. If yes, subtract the accumulated delay of this round from the delay of the Data Lane, and then judge whether the delay of the Data Lane is equal to (M-1)UI / M. If yes, return error and end the flow; if not, update the delay of the Data Lane according to the bisection method, and then re-enter the delay updating stage of the Data Lane.

[0125] The Data Lane optimal sampling point searching stage includes:

[0126] Record the delay of the Data Lane, subtract the delay of the Data Lane by UI / 2, and detect the phase relationship between the Training Lane and the Data Lane.

[0127] If the phase relationship satisfies UP=DN=0, judge whether the delay of the Data Lane has been adjusted to the maximum. If not, increase the delay of the Data Lane by the bisection method, and then re-enter the step of detecting the phase relationship between the Training Lane and the Data Lane. If yes, record the delay of the Data Lane as the delay corresponding to the right edge of the Data Lane eye diagram, and then enter the process of searching for the delay corresponding to the left edge of the Data Lane eye diagram.

[0128] If the phase relationship does not satisfy UP=DN=0, judge whether the delay of the Data Lane has been adjusted to the maximum. If not, decrease the delay of the Data Lane by the bisection method, and then re-enter the step of detecting the phase relationship between the Training Lane and the Data Lane. If yes, add the minimum adjustable delay to the delay of the Data Lane, and then record the adjusted delay of the Data Lane as the delay corresponding to the right edge of the Data Lane eye diagram, and then enter the process of searching for the delay corresponding to the left edge of the Data Lane eye diagram.

[0129] The process of searching for the delay corresponding to the left edge of the Data Lane eye diagram includes:

[0130] Restore the delay of the Data Lane to the record when entering the Data Lane optimal sampling point searching stage, and then add the delay of the Data Lane by UI / 2, and detect the phase relationship between the Training Lane and the Data Lane.

[0131] If the phase relationship satisfies UP=DN=0, it is determined whether the delay of the Data Lane has been unadjustable. If not, the delay of the Data Lane is increased by dichotomy, and then the step of detecting the phase relationship between the Training Lane and the Data Lane is re-entered. If yes, the delay of the Data Lane is recorded as the delay corresponding to the left edge of the eye diagram of the Data Lane.

[0132] If the phase relationship does not satisfy UP=DN=0, it is determined whether the delay of the Data Lane has been unadjustable. If not, the delay of the Data Lane is decreased by dichotomy, and then the step of detecting the phase relationship between the Training Lane and the Data Lane is re-entered. If yes, the delay of the Data Lane is subtracted by the minimum adjustable delay, and then the adjusted delay of the Data Lane is recorded as the delay corresponding to the left edge of the eye diagram of the Data Lane.

[0133] The middle value of the delays corresponding to the left and right edges of the eye diagram of the Data Lane is taken as the delay of the Data Lane, and the optimal sampling point of the Data Lane is obtained and recorded.

[0134] After the optimal sampling points of all the data Lanes are obtained, the calibration ends. At this time, the optimal sampling points of each data Lane and the standard Lane are aligned, and the initial calibration and data alignment of all the Lanes are realized.

[0135] In the embodiments of the present application, if the standard Lane is a preset data Lane specially used for offset calibration between Lanes, the calibration of the data Lane can also be performed in the normal use process of the source synchronous system, that is, in the process of normal data transmission of the data Lane.

[0136] For example, in the process of data transmission, the data in the data Lane to be calibrated can be synchronized and transmitted in the standard Lane, and the optimal sampling point of the standard Lane is re-determined according to the clock signal delay. Then, according to the clock signal delay and the re-determined optimal sampling point of the standard Lane, the optimal sampling points of each data Lane to be calibrated are determined.

[0137] It should be understood that the data Lane to be calibrated is one of the data Lanes. If calibration is needed for multiple data Lanes, calibration needs to be performed one by one.

[0138] For example, still taking the foregoing example, the same data as the data lane to be calibrated is transmitted in the standard lane, and the standard lane calls the clock signal delay determined in S801 and the delay of the data lane, and then the operation of S802 is repeated to re-determine the optimal sampling point corresponding delay of the standard lane, record the difference between the new optimal sampling point and the optimal sampling point determined in the initial calibration, and bring the delay change value of the standard lane (i.e. the foregoing difference value) into the data lane to be calibrated (i.e. update the delay change value in the data lane to be calibrated), and end the calibration of the data lane to be calibrated. The specific implementation process can be referred to Figure 12 As shown, comprising:

[0139] The Training Lane is brought into the delay calibrated before (i.e. the standard sampling point determined in step S803), and then the Training Lane is delayed by -UI / 2, and the phase relationship between the Training Lane and the data lane to be calibrated is detected.

[0140] If the phase relationship satisfies UP=DN=0, it is first judged whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is reduced using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data lane to be calibrated is re-entered. If yes, the delay of the Training Lane is recorded as the delay corresponding to the right side edge of the Training Lane eye diagram, and then the process of finding the delay corresponding to the left side edge of the Training Lane eye diagram is entered.

[0141] If the phase relationship does not satisfy UP=DN=0, it is first judged whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is increased using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data lane to be calibrated is re-entered. If yes, the delay of the Training Lane is added with the minimum adjustable delay, and then the adjusted delay of the Training Lane is recorded as the delay corresponding to the right side edge of the Training Lane eye diagram, and then the process of finding the delay corresponding to the left side edge of the Training Lane eye diagram is entered.

[0142] The process of finding the delay corresponding to the left side edge of the Training Lane eye diagram comprises:

[0143] After the Training Lane is delayed by (N+0.5)UI, the phase relationship between the Training Lane and the data lane to be calibrated is detected.

[0144] If the phase relationship satisfies UP=DN=0, it is firstly judged whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is increased by using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data Lane to be calibrated is re-entered. If yes, the delay of the Training Lane is recorded as the delay corresponding to the left edge of the eye diagram of the Training Lane.

[0145] If the phase relationship does not satisfy UP=DN=0, it is still firstly judged whether the delay of the Training Lane has been unadjustable. If not, the delay of the Training Lane is decreased by using the dichotomy, and then the process of detecting the phase relationship between the Training Lane and the data Lane to be calibrated is re-entered. If yes, the delay of the Training Lane is subtracted by the minimum adjustable delay, and then the adjusted delay of the Training Lane is recorded as the delay corresponding to the left edge of the eye diagram of the Training Lane.

[0146] The median of the delays corresponding to the left and right edges of the eye diagram of the Training Lane is taken as the delay of the Training Lane, and the difference Δ is obtained by subtracting the median obtained by the previous calibration.

[0147] The delay of the data Lane to be calibrated is updated and recorded as the current delay+Δ.

[0148] It should be noted that, Figures 9 to 12 The search in the range of 0~(N+1)UI is performed by taking 3 UIs as the step size, in the actual application process, the search in the range of 0~(N+1)UI can also be performed by taking 1 UI or 2 UIs as the step size, and the present application embodiments do not limit this.

[0149] It should be further noted that, Figures 9 to 12 The adjustment sequence of the delays of the clock Lane and the data Lane in the above process can be freely changed, and does not affect the implementation of the present application embodiments.

[0150] The scheme of the embodiment of the present application can replace the identification between the data received by the data Lane and the test pattern generated (or stored) by the pattern generator (or pattern memory) in the prior art with the identification of the data phase between the two Lanes (data Lane and standard Lane), so that the same pattern is only required to be transmitted by the two identified Lanes, and the offset in the two Lanes can be determined, without the identified pattern being a fixed type, reducing the dependence on the pattern, without the need to preset the test pattern, and the data pattern actually transmitted by the source synchronous system can be calibrated, and the calibration result is more accurate. Moreover, the scheme of the present application does not need to configure the pattern generator (or pattern memory) on both sides for each data Lane, and does not need to configure a pattern detection circuit for each data Lane, but only needs to set a pattern identifier between each data Lane and the standard Lane, so that the layout area required is smaller, and the system is miniaturized. In addition, the scheme of the embodiment of the present application can realize the pattern identifier by only 6 flip-flops, so that the cost and the layout area can be effectively reduced. The scheme of the embodiment of the present application replaces the identification between the data received by the data Lane and the test pattern generated (or stored) by the pattern generator (or pattern memory) in the prior art with the identification of the data phase between the two Lanes (data Lane and standard Lane), so that the amount of data required to be processed in the calibration process is smaller, and the calibration effect is higher. In addition, the calibration by the dichotomy can also greatly shorten the calibration time.

[0151] Based on the same inventive concept, the embodiment of the present application further provides an on-chip system, which comprises the source synchronous system provided by the embodiment of the present application.

[0152] In addition, the on-chip system can further comprise a controller, so that one or more preset programs are executed by the controller to execute the offset calibration method as described above.

[0153] It should be understood that the controller described in the embodiment of the present application can be a device with a control function such as a processor core. The controller can be connected with the output end of the pattern identifier and each delay unit, so as to control the delay value of each delay unit according to the output result of the pattern identifier, and realize the offset calibration method as described above.

[0154] Based on the same inventive concept, the embodiment of the present application further provides an electronic component, which comprises the on-chip system as described above.

[0155] It should be understood that the electronic component described in the embodiment of the present application can be a communication module, a computing module or other component with a source synchronization requirement, but is not limited thereto.

[0156] Based on the same inventive concept, the embodiment of the present application further provides an electronic device, which comprises the foregoing system on chip or comprises the foregoing electronic component.

[0157] Optionally, the electronic device can be a device such as a computer, a mobile phone, a server, etc., but is not limited thereto.

[0158] Based on the same inventive concept, the embodiment of the present application further provides a computer readable storage medium, such as a floppy disk, an optical disk, a hard disk, a flash memory, a U disk, an SD (Secure Digital Memory Card) card, an MMC (Multimedia Card) card, etc., which stores one or more programs for implementing the foregoing steps, and the one or more programs can be executed by one or more controllers to implement the foregoing offset calibration method. Details are not described herein.

[0159] In the embodiments provided by the present application, it should be understood that the disclosed device and method can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of units is only a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some communication interfaces, and can be electrical, mechanical or other forms.

[0160] In addition, the units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, i.e. they can be located in one place, or can be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0161] Furthermore, the functional modules in each embodiment of the present application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0162] In this document, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations.

[0163] In this document, plural refers to two or more.

[0164] The above merely provides an example of the present application, and is not used to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A source synchronous system, characterized in that: include: A transmitting chip and a receiving chip; the transmitter of the transmitting chip and the receiver of the receiving chip are connected through channels to form lanes; The Lane includes a data Lane and a clock Lane; The data lane is a lane in each lane used for data transmission; The clock lane is a lane in each lane for transmitting a clock signal; a plurality of delay units, respectively connected to each of the transmitters or each of the receivers, to adjust the delay of the lane where the connected transmitter or receiver is located; The code pattern identifier is connected between the output ends of any data Lane and the standard Lane to detect the data phase relationship between the data Lane and the standard Lane; wherein the standard Lane is a pre-selected data Lane.

2. The source synchronous system according to claim 1, wherein: The code pattern identifier comprises: a data phase identification module, having an input terminal connected to the output terminals of the data lane and the standard lane, and outputting a first signal and a second signal reflecting the data phase relationship between the data lane and the standard lane through a first output terminal and a second output terminal; a first D flip-flop and a second D flip-flop having a reset function, wherein data input ports of the first D flip-flop and the second D flip-flop are used to access a reference voltage; a clock port of the first D flip-flop is connected to a first output terminal of the data phase identification module, and a reset port of the first D flip-flop is connected to a second output terminal of the data phase identification module; a clock port of the second D flip-flop is connected to a second output terminal of the data phase identification module, and a reset port of the second D flip-flop is connected to a first output terminal of the data phase identification module; A third D flip-flop and a fourth D flip-flop, wherein the data input ports of the third D flip-flop and the fourth D flip-flop are used to access a reference voltage; a clock port of the third D flip-flop is connected to the data output port of the first D flip-flop; and a clock port of the fourth D flip-flop is connected to the data output port of the second D flip-flop.

3. The source synchronous system according to claim 2, wherein: The data phase identification module is a phase frequency detector or a phase detector.

4. The source synchronous system according to any one of claims 1 to 3, wherein: The standard Lane is a preset data Lane specifically used for performing offset calibration between the Lanes.

5. An offset calibration method, characterized in that: Applied to the source synchronous system according to any one of claims 1 to 4, the method comprises: Obtaining a clock signal delay when data in the standard lane can be stably sampled; Determining the optimal sampling point of the standard Lane according to the clock signal delay; Determining the optimal sampling point of each of the data Lanes according to the clock signal delay and the optimal sampling point of the standard Lane; Determining the optimal sampling point of each data lane based on the clock signal delay and the optimal sampling point of the standard lane includes: for each data lane: maintaining the clock signal delay and the optimal sampling point of the standard lane unchanged, sequentially adjusting the delay of the data lane within the maximum delay range of the data lane until a delay K is obtained that makes the phases of the data lane and the standard lane identical; sequentially adjusting the delay of the data lane within a range of plus or minus one UI of the delay K to obtain a data lane delay range that makes the phase conversion relationship between the data lane and the standard lane satisfy a preset relationship; and determining the optimal sampling point of the data lane based on the data lane delay range; wherein the preset relationship is: the phases of the data lane and the standard lane are identical, and after increasing the delay of the data lane by one unit time interval UI, the output of the code pattern identifier satisfies a first combination, and after decreasing the delay of the data lane by one UI, the output of the code pattern identifier satisfies a second combination.

6. The method according to claim 5, wherein The source synchronous system also has a clock Lane for transmitting a clock signal; The obtaining of a clock signal delay when data can be stably sampled into the standard Lane includes: Setting the delay of the standard Lane to the maximum offset of the source synchronous system; Within the delay range of the data lane, the delay of each data lane and the delay of the clock lane are adjusted in turn until the delay of the clock lane is obtained when the phase conversion relationship between the target data lane and the standard lane satisfies a preset relationship; the target data lane is any data lane; the delay of the clock lane is the clock signal delay; The preset relationship is: The phase of the target data Lane and the standard Lane is the same, and after the delay of the target data Lane is increased by a unit time interval UI, the output of the code type identifier conforms to the first combination, and after the delay of the target data Lane is reduced by one UI, the output of the code type identifier conforms to the second combination.

7. The method according to claim 6, wherein Determining the optimal sampling point of the standard Lane according to the clock signal delay includes: Maintaining the delays of the target data Lane and the clock Lane, and sequentially adjusting the delays of the standard Lanes within a range of plus or minus one UI of the maximum offset of the source synchronous system, to obtain a standard Lane delay range such that the phase conversion relationship between the target data Lane and the standard Lane satisfies the preset relationship; An optimal sampling point of the standard Lane is determined according to the standard Lane delay range.

8. The method according to claim 7, wherein Determining an optimal sampling point of the standard Lane according to the standard Lane delay range includes: The median value of the standard Lane delay range is determined as the optimal sampling point of the standard Lane.

9. The method according to claim 5, wherein Determining an optimal sampling point of the data Lane according to the data Lane delay range includes: The median of the data Lane delay range is determined as the optimal sampling point of the data Lane.

10. The method according to any one of claims 5 to 9, characterized in that The standard lane is a preset data lane specifically used for performing offset calibration between the lanes; the method further includes: During the data transmission process, the data in the data lane to be calibrated is synchronously transmitted in the standard lane; Re-determining the optimal sampling point of the standard Lane according to the clock signal delay; The optimal sampling point of each of the data lanes to be calibrated is determined based on the clock signal delay and the re-determined optimal sampling point of the standard lane.

11. A system on chip, characterized in that: The method comprises the source synchronous system according to any one of claims 1 to 4.

12. A system on chip, characterized in that: The system comprises a controller and the source synchronization system according to any one of claims 1 to 4; the controller is configured to execute one or more preset programs to execute the method according to any one of claims 5 to 10.

13. An electronic component, characterized in that: Comprising the system on chip as claimed in claim 11 or 12.

14. An electronic device, characterized in that: comprising the system on chip according to claim 11 or 12, or comprising the electronic component according to claim 13.

15. A computer-readable storage medium, characterized in that The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more controllers to implement the method according to any one of claims 5 to 10.

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