A Method for Implementing Multi-Line-Pair SHDSL Aggregated Ethernet Service

Abstract

The present invention relates to a method for realizing multi-line pair SHDSL converged Ethernet services, belonging to the field of SHDSL transmission. It is characterized in that the service convergence function is implemented by an FPGA, including a TDM transceiver module and an Ethernet convergence control module. The Ethernet convergence control module includes a serial-parallel conversion module, an HDLC framing and deframing module, a first-level FIFO, and a second-level FIFO. It includes processing flows such as TDM channel binding, opening FIFO caches, opening a first-level FIFO, HDLC encoding of Ethernet data, data distribution of the first-level FIFO, and serial-parallel conversion. The implementation method of the present invention simplifies the CPU's monitoring process of the link, ensures the optimization of the device link establishment time, and the maximum bandwidth provided can reach 65.536 Mbit / s.

Description

Technical Field

[0001] The present invention relates to the field of SHDSL transmission, and particularly to a method for implementing multi-line pair SHDSL converged Ethernet services. Background Art

[0002] Traditional multi-line pair binding of SHDSL usually adopts an internal chip synchronization mechanism. For example, in the patent application with the application number 201410802910.1 and the title "A SHDSL transmission module and implementation method for multi-line pair self-adaptive aggregation", the maximum multi-channel aggregated bandwidth can reach 24.576 Mbit / s. However, this implementation method requires synchronization between multiple channels. When the synchronization is lost, it will lead to difficulties in establishing a link or even inability to establish a link. Moreover, after entering the multi-line pair mode, the CPU needs to continuously monitor whether the communication channels covered by the current multi-line pair are out of sync and the recovery situation. The link maintenance is complex and the link establishment time is relatively long. For example, in the patent application with the application number 200710007437.8 and the title "Multi-line pair DSL device detection and processing device and method", a multi-line pair DSL device detection and processing device and method are designed to solve the problem of long-time inability to establish a link caused by the loss of synchronization between line pairs in the DSL multi-line pair mode. However, this method is time-consuming to implement and it is difficult to ensure the availability of the device in application environments where the link establishment time index is relatively strict, such as the military field. Summary of the Invention

[0003] The present invention provides a method for implementing multi-line pair SHDSL converged Ethernet services to solve the above problems existing in the prior art, simplifies the CPU's monitoring process of the link, and ensures the optimization of the device link establishment time.

[0004] The technical solution of the present invention to solve the above technical problems is as follows: A method for implementing multi-line pair SHDSL converged Ethernet services, characterized in that the service aggregation function is implemented by an FPGA, including a TDM transceiver module and an Ethernet aggregation control module. The Ethernet aggregation control module includes a serial-parallel conversion module, an HDLC framing and deframing module, a first-level FIFO, and a second-level FIFO, and is used to implement the transmission of Ethernet services through multiple TDM interfaces.

[0005] Ethernet transmission direction:

[0006] 1) TDM channel binding, and the binding rule is: first set the pre-bound channels, that is, which channels are to be bound, judge the link status of each path corresponding to the TDM channel. If the link has been established, add it to the actual bound channels, otherwise exclude the channel.

[0007] 2) Open up FIFO caches, open up a first-level FIFO, and open up 4 second-level FIFOs for each path according to the maximum bandwidth of 4 channels. The first-level FIFO and the second-level FIFO each include a transmission FIFO and a reception FIFO with the same size.

[0008] 3) Ethernet data HDLC encoding: For Ethernet ingress data frames with a length less than the preset number of bytes, the preamble and FCS are removed. A 1-byte Ethernet data type encoding and 2-byte time series are added to the header, and a CRC16 check sequence is added to the tail. After HDLC encapsulation, the data is stored in the transmit first-level FIFO. For Ethernet ingress data frames with a length greater than the preset number of bytes, they need to be split according to the maximum length preset number of bytes and then encapsulated according to the above rules and saved to the first-level FIFO.

[0009] 4) First-level FIFO data distribution: The sending process is as follows: The first-level state machine calculates the bound number of channels and distributes the Ethernet frames in the first-level FIFO to the second-level FIFOs of each channel in sequence from the channel with the lowest number to the channel with the highest number. The distribution rule is to distribute the entire Ethernet frame, and if a channel is busy, that channel is skipped.

[0010] 5) Serial-to-parallel conversion: The second-level state machine maintains the input of data from the second-level FIFO to the TDM interface to achieve serial-to-parallel conversion. The TDM transceiver module generates corresponding TDM clock frequencies PCLK, TDM frame synchronization signals TFSC, and periodic symDSL frame synchronization signals TSFCS according to the channel rate. The second-level state machine sends the data in the second-level FIFO to the TDM interface according to the TDM clock frequency, and the voice time slots need to be skipped when sending data. The voice time slots are located in the first and second time slots of the TDM frame. Voice services are not processed for service distribution and are only transmitted through the first channel, that is, the bound channel with the smallest number.

[0011] Furthermore, in step 2), a FIFO buffer is opened, a first-level FIFO is opened, and 4 second-level FIFOs are opened according to the maximum bandwidth of 4 channels, 16384 kbit / s per channel.

[0012] Furthermore, in step 3), the preset number of bytes is 1792 bytes.

[0013] Furthermore, in step 5), the TDM transceiver module generates corresponding TDM clock frequencies PCLK, a TDM frame synchronization signal TFSC of 8 kHz, and a symDSL frame synchronization signal TSFCS with a period of 6 ms according to the channel rate.

[0014] Furthermore, the Ethernet aggregation control module includes an HDLC framing and deframing module, a first-level FIFO, second-level FIFOs with the same number as the TDM channels, and a serial-to-parallel conversion module.

[0015] Furthermore, the Ethernet receiving direction processing flow corresponds to the Ethernet sending direction, and the aggregation and merging from the second-level FIFO to the first-level FIFO need to be processed. When the HDLC framing and deframing module finds Ethernet type data in the data in the first-level FIFO, it starts to deframe and restores it to standard Ethernet data and sends it to the GMII interface.

[0016] The beneficial effects of the present invention are as follows: By implementing the method of the present invention, following the single-line pair link establishment control process, there is no need to configure the SHDSL chip in the M-pair mode, which simplifies the CPU's monitoring process of the link and the synchronization process between multiple line pairs, ensuring the optimization of the device link establishment time. The multi-line pair aggregation function is implemented through FPGA logic, and the maximum bandwidth provided can reach 65.536 Mbit / s. Moreover, the switching between the multi-line pair mode and the single-line pair mode does not require link disconnection and reconnection, and the application method is more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is the schematic diagram of the implementation method of multi-line pair SHDSL aggregation Ethernet service;

[0018] Figure 2 is the HDLC data encapsulation of the implementation method of multi-line pair SHDSL aggregation Ethernet service;

[0019] Figure 3 is the flowchart of the implementation method of multi-line pair SHDSL aggregation Ethernet service. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] The principle and features of the present invention will be described below. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0021] As shown in the accompanying drawings, the implementation method of the multi-line pair SHDSL aggregation Ethernet service in this embodiment is implemented by FPGA and includes a TDM transceiver module and an Ethernet aggregation control module. The Ethernet aggregation control module includes an HDLC framing and deframing module, a first-level FIFO, second-level FIFOs with the same number as the TDM channels, and a serial-parallel conversion module;

[0022] The system design and control process will be elaborated in detail below:

[0023] The working process of the service processing unit in the Ethernet transmission direction is as Figure 3 shown,

[0024] TDM channel binding, and the binding rule is: first set the pre-bound channels, that is, which channels are to be bound, judge the link status of each path corresponding to the TDM channel. If the link has been established, add it to the actual bound channels, otherwise remove the channel. This status judgment is cycled in the entire service process;

[0025] The Ethernet aggregation control module opens up FIFO caches, opens up a first-level FIFO, and opens up 4 second-level FIFOs at a maximum bandwidth of 16384 kbit / s per channel for 4 channels (when the maximum rate of a single channel of the chip is 16384 kbit / s, the maximum number of data bits in the TDM frame is 2048 bits). Both the first-level FIFO and the second-level FIFOs include transmission FIFOs and reception FIFOs of the same size;

[0026] Ethernet data HDLC encoding: for Ethernet ingress data frames with a length less than 1792 bytes, the preamble and FCS are removed, 1 byte of Ethernet data type encoding and 2 bytes of time series are added to the header, and a CRC16 check sequence is added to the tail, then it is encapsulated by HDLC and the data is stored in the transmit first-level FIFO; for Ethernet ingress data frames with a length greater than 1792 bytes, they need to be split according to the maximum length of 1792 bytes, and then encapsulated according to the above rules and saved to the first-level FIFO;

[0027] First-level FIFO data distribution: The sending process is that the first-level state machine calculates the bound number of channels, and the Ethernet frames in the first-level FIFO are distributed to the second-level FIFOs of each channel in sequence from the channel with the lower number to the channel with the higher number. The sending rule is to distribute the entire HDLC frame. If the channel is busy, skip that channel;

[0028] Serial-to-parallel conversion: The second-level state machine maintains the input of data from the second-level FIFO to the TDM interface to achieve serial-to-parallel conversion. According to G.991.2, 1 symDSL frame data contains 48 TDM data frames. The TDM frame synchronization signal and symDSL frame synchronization signal at different link rates are fixed. What changes is the TDM clock frequency and the number of data bits. The TDM transceiver module generates the corresponding TDM clock frequency PCLK, 8kHz TDM frame synchronization signal TFSC, and symDSL frame synchronization signal TSFCS with a period of 6ms according to the actual rate of the channel; the second-level state machine sends the data in the second-level FIFO to the TDM interface according to the PCLK frequency, shifting 1 bit of data per PCLK. When sending data, skip the voice time slots, which are located in the 1st and 2nd time slots after the TDM frame synchronization pulse; Voice services do not perform service distribution processing and are only transmitted through the first channel, that is, the bound channel with the smallest number.

[0029] The above is the processing of the Ethernet sending direction service flow. The Ethernet receiving direction flow corresponds to the sending processing flow. The second-level state machine in the TDM transceiver module samples the TDM clock frequency RCLK, frame synchronization signal, and symDSL frame synchronization signal at the SDI port of the SHDSL processor, performs serial-to-parallel conversion on the TDM data and caches it in the second-level FIFO. After the first-level state machine determines that the TDM transceiver module has completed the reception of one Ethernet frame, it processes the convergence and merging from the second-level FIFO to the first-level FIFO, and arranges the frames in sequence and converges them to the first-level FIFO through the 2-byte time series in the Ethernet frame header. When the HDLC framing and deframing module finds that there is Ethernet type data in the data in the first-level FIFO, it starts to deframe and restores it to standard Ethernet data and issues it to the GMII port.

Claims

1. A method for implementing multi - line - pair SHDSL converged Ethernet service, characterized in that, it is implemented by an FPGA. The FPGA includes a TDM transceiver module and an Ethernet convergence control module. The Ethernet convergence control module includes a serial - to - parallel conversion module, an HDLC framing and deframing module, a first - level FIFO, and a second - level FIFO, and is used to implement the transmission of Ethernet service through multiple TDM interfaces; Ethernet transmission direction: 1) TDM channel binding. The binding rule is as follows: first set the pre - bound channels, that is, which channels are to be bound, and judge the link status of each path corresponding to the TDM channel. If the link has been established, it is added to the actual bound channels; otherwise, the channel is excluded; 2) Open FIFO caches. Open a first - level FIFO, and open 4 second - level FIFOs according to the maximum bandwidth of 4 channels. Each of the first - level FIFO and the second - level FIFO contains a transmission FIFO and a reception FIFO of the same size; 3) HDLC encoding of Ethernet data. For an Ethernet ingress data frame with a length less than the preset number of bytes, remove the preamble and FCS, add 1 - byte Ethernet data type encoding and 2 - byte time series to the header, add a CRC16 check sequence to the tail, and then encapsulate it by HDLC and store the data in the transmission first - level FIFO. For an Ethernet ingress data frame with a length greater than the preset number of bytes, it needs to be split according to the maximum length preset number of bytes, and then encapsulated according to the above rules and stored in the first - level FIFO; 4) First - level FIFO data distribution. The sending process is as follows: the first - level state machine calculates the number of bound channels, and sequentially distributes the Ethernet frames in the first - level FIFO to the second - level FIFOs of each channel from the channel with a lower number to the channel with a higher number. The distribution rule is to distribute the entire Ethernet frame. If the channel is busy, skip this channel; 5) Serial - to - parallel conversion. The second - level state machine maintains the input of the second - level FIFO to the TDM interface to implement serial - to - parallel conversion. The TDM transceiver module generates corresponding TDM clock frequencies PCLK, TDM frame synchronization signals TFSC, and periodic symDSL frame synchronization signals TSFCS according to the channel rate. The second - level state machine sends the data in the second - level FIFO to the TDM interface according to the TDM clock frequency. When sending data, it needs to skip the voice time slots, and the voice time slots are located in the first and second time slots of the TDM frame. The voice service does not perform service distribution processing and is only transmitted through the first channel, that is, the bound channel with the smallest number.

2. The method for implementing multi - line - pair SHDSL converged Ethernet service according to claim 1, characterized in that, in step 2), open FIFO caches, open a first - level FIFO, and open 4 second - level FIFOs according to the maximum bandwidth of 16384 kbit / s for each of the 4 channels.

3. The method for implementing multi - line - pair SHDSL converged Ethernet service according to claim 1, characterized in that, in step 3), the preset number of bytes is 1792 bytes.

4. The method for implementing multi - line - pair SHDSL converged Ethernet service according to claim 1, characterized in that, In step 5), the TDM transceiver module generates a corresponding TDM clock frequency PCLK, a TDM frame synchronization signal TFSC of 8 kHz, and a symDSL frame synchronization signal TSFCS with a period of 6 ms according to the channel rate.

5. The method for implementing a multi-line pair SHDSL converged Ethernet service according to claim 1, wherein, the Ethernet convergence control module includes an HDLC framing and deframing module, a first-level FIFO, second-level FIFOs with the same number as the TDM channels, and a serial-to-parallel conversion module.

6. The method for implementing a multi-line pair SHDSL converged Ethernet service according to any one of claims 1-5, wherein, the Ethernet receiving direction processing flow corresponds to the Ethernet sending direction, and it is necessary to process the convergence and merging from the second-level FIFO to the first-level FIFO. When the HDLC framing and deframing module finds Ethernet type data in the first-level FIFO, it starts deframing and restores it to standard Ethernet data for distribution to the GMII port.

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