Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present disclosure provide a preparation method of a semiconductor structure and the semiconductor structure. The method comprises: providing a substrate; forming a first stack on the substrate and forming a plurality of first openings in the first stack; forming a fence on inner walls of the first openings; forming a second stack on the first stack and the fence; forming a first mask layer with a capacitance pattern on the second stack; based on the capacitance pattern, etching from the second stack to a direction close to the substrate to form a first capacitance hole by using a first etching process, a sidewall of a bottom of the first capacitance hole exposing at least part of the fence; wherein in the first etching process, etching selectivity ratios of the second stack and the fence are different; etching the first mask layer and the fence at the bottom of the first capacitance hole by using a second etching process to expose the substrate, so that the first capacitance hole is formed into a second capacitance hole. The method of the present disclosure makes the second capacitance hole have a high aspect ratio, and improves the electrical performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] Dynamic Random Access Memory (DRAM) consists of transistors and capacitors. To increase the capacitance of the capacitors, they often have a very high aspect ratio. During the capacitor fabrication process, incomplete etching of the bottom of the capacitor hole can easily cause the bottom of the capacitor hole to be smaller than the upper part. This causes the resulting capacitor to tilt, resulting in poor electrical contact and reduced yield.

[0003] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may include information that does not constitute the relevant technology that is already known to a person of ordinary skill in the art. Summary of the Invention

[0004] The embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure, which can prepare a semiconductor structure with uniform size, not prone to tilt and with a high aspect ratio, thereby improving the electrical performance and yield of the semiconductor structure.

[0005] An embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate; forming a first stack on the substrate, and forming a plurality of first openings in the first stack; forming a fence on the inner wall of the first opening; forming a second stack on the first stack and the fence; forming a first mask layer having a capacitor pattern on the second stack; based on the capacitor pattern, etching from the second stack toward the substrate using a first etching process to form a first capacitor hole, wherein the sidewall of the bottom of the first capacitor hole exposes at least a portion of the fence; wherein, in the first etching process, the etching selectivity of the second stack and the fence is different; etching the first mask layer and the fence at the bottom of the first capacitor hole using a second etching process to expose the substrate, so that the first capacitor hole is formed into a second capacitor hole.

[0006] According to some embodiments of the present disclosure, the capacitor pattern is located above the first opening, and a radial dimension of the capacitor pattern is smaller than or equal to a radial dimension of the first opening.

[0007] According to some embodiments of the present disclosure, a radial dimension of the first opening is 0-8 nm larger than a radial dimension of the second capacitor hole.

[0008] According to some embodiments of the present disclosure, the capacitor pattern is located above the first stack, and the radial dimension of the capacitor pattern is greater than or equal to the radial dimension of the first stack between two adjacent first openings; wherein, the first etching process is used to etch from the second stack toward the direction close to the substrate to form the first capacitor hole, including: using the first etching process to etch from the second stack to the surface of the substrate to form the first capacitor hole.

[0009] According to some embodiments of the present disclosure, a depth of the second capacitor hole is greater than or equal to 1000 nm; and / or an aspect ratio of the second capacitor hole is greater than or equal to 35:1.

[0010] According to some embodiments of the present disclosure, the fence accounts for a ratio of 1 / 3 to 1 of the radial dimension of the first opening.

[0011] According to some embodiments of the present disclosure, the first etching process is a dry etching process, and an etching gas used has an etching selectivity ratio of 5 to 10 to the first stack, the second stack, and the fence.

[0012] According to some embodiments of the present disclosure, the second etching process is a dry etching process, and an etching gas used has an etching selectivity ratio of 5 to 10 for the fence and the first stack.

[0013] According to some embodiments of the present disclosure, forming a first stack on the substrate includes: forming a first supporting layer on the substrate; forming a first sacrificial layer on the first supporting layer; wherein the first opening is located not only in the first supporting layer but also in the first sacrificial layer.

[0014] According to some embodiments of the present disclosure, forming a second stack on the first stack and the fence includes: forming a second sacrificial layer on the first stack and the fence; forming a second supporting layer on the second sacrificial layer; forming a third sacrificial layer on the second supporting layer; and forming a third supporting layer on the third sacrificial layer.

[0015] According to some embodiments of the present disclosure, the method also includes: forming a lower electrode layer on the inner wall of the second capacitor hole and the top surface of the second stack; forming a second mask layer having a first pattern on the lower electrode layer, the first pattern exposing a portion of the lower electrode layer on the top surface of the second stack; based on the first pattern, removing the exposed lower electrode layer to expose the third supporting layer; removing the exposed third supporting layer; removing the third sacrificial layer to expose the third supporting layer corresponding to the first pattern; removing the exposed second supporting layer; removing the second sacrificial layer and the remaining fence.

[0016] According to some embodiments of the present disclosure, a wet etching process is used to remove the second sacrificial layer and the remaining fences. The etchant used in the wet etching process includes an additive capable of removing the fences.

[0017] According to some embodiments of the present disclosure, a capacitor is also formed, including: forming a dielectric layer on the lower electrode layer; forming an upper electrode layer on the dielectric layer; wherein the capacitor includes the lower electrode layer, the dielectric layer and the upper electrode layer, and the lower electrode layer is a tubular electrode or a columnar electrode.

[0018] According to some embodiments of the present disclosure, the material of the fence includes at least one of polysilicon and carbon.

[0019] The present disclosure also provides a semiconductor structure that is prepared using the method described in any of the above embodiments.

[0020] It can be seen from the above technical solutions that the method for preparing the semiconductor structure and the semiconductor structure according to the embodiments of the present disclosure have at least one of the following advantages and positive effects:

[0021] In the disclosed embodiment, a fence is formed on the inner wall of the first opening of the first stack. When etching the second stack based on the capacitor pattern, the etching gas has different etching selectivities for the second stack and the fence, thereby enabling the second stack to be etched to form a first capacitor hole. The fence is located at the bottom of the first capacitor hole and acts as a placeholder, thereby preventing the bottom size from being reduced due to incomplete etching of the sidewalls at the bottom of the first capacitor hole due to the high aspect ratio of the first capacitor hole. The second etching process expands the size of the bottom of the first capacitor hole, thereby ensuring that the size of the subsequently formed second capacitor hole is more uniform, especially in the vertical direction. The fence also provides protection, preventing defects in the sidewalls of the first capacitor hole caused by uneven sputtering of the etching gas at the bottom of the first etching process. When the fence at the bottom is removed by the second etching process, the fence at the bottom of the first capacitor hole continues to etch downward along the contour of the top opening of the first capacitor hole, forming a second capacitor hole with smoother sidewalls. This improves the aspect ratio of the second capacitor hole and further enhances the electrical performance and yield of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other features and advantages of the present disclosure will become more apparent by describing in detail example embodiments thereof with reference to the accompanying drawings.

[0023] Figure 1 A flow chart of a method for preparing a semiconductor structure according to some embodiments of the present disclosure;

[0024] Figures 2 to 3 A schematic diagram illustrating forming a first stack having a first opening on a substrate according to some embodiments of the present disclosure;

[0025] Figures 4 and 5 A schematic diagram illustrating forming a fence on the inner wall of a first opening according to some embodiments of the present disclosure;

[0026] Figures 6 to 8 Schematic diagram of forming a first mask layer having a capacitor pattern on a second stack according to some embodiments of the present disclosure;

[0027] Figure 9 Schematic diagram showing etching the second stacked layer to form a first capacitor hole based on a capacitor pattern according to some embodiments of the present disclosure;

[0028] Figure 10 Schematic diagram showing how to remove a fence protruding from the inner wall of a first capacitor hole to form a second capacitor hole according to some embodiments of the present disclosure;

[0029] Figure 11 Schematic diagram of forming a lower electrode layer on the inner wall of the second capacitor hole and the top surface of the second stack according to some embodiments of the present disclosure;

[0030] Figure 12 A schematic diagram illustrating forming a second mask layer having a first pattern on a lower electrode layer according to some embodiments of the present disclosure;

[0031] Figure 13 Schematic diagram of removing the lower electrode layer and the third supporting layer corresponding to the first pattern according to some embodiments of the present disclosure;

[0032] Figure 14 A schematic diagram illustrating removal of the third sacrificial layer according to some embodiments of the present disclosure;

[0033] Figure 15 A schematic diagram illustrating the removal of the exposed third supporting layer according to some embodiments of the present disclosure;

[0034] Figure 16 Schematic diagram showing the removal of the second sacrificial layer and the fence to form a capacitor according to some embodiments of the present disclosure.

[0035] Description of reference numerals:

[0036] 1. Substrate; 2. First stack; 21. First support layer; 22. First sacrificial layer; 23. First opening; 23', second opening; 3. Initial mask layer; 31. Initial hard mask layer; 32. Initial silicon oxynitride layer; 4. Initial photoresist; 5. Fence; 6. Second stack; 61. Second sacrificial layer; 62. Second support layer; 63. Third sacrificial layer; 64. Third support layer; 7. First mask layer; 71. First hard mask layer; 72. First oxide layer; 73. First Second hard mask layer; 74, first silicon oxynitride layer; 75, first photoresist; 8, first capacitor hole; 8', second capacitor hole; 9, lower electrode layer; 10, second mask layer; 101, third hard mask layer; 102, second silicon oxynitride layer; 103, second photoresist; 11, dielectric layer; 12, upper electrode layer; S1, capacitor pattern; S2, first pattern; d1, radial dimension of the first opening; d2, radial dimension of the second opening; d3, radial dimension of the second capacitor hole. DETAILED DESCRIPTION

[0037] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0038] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of this disclosure and in which different exemplary structures that can implement various aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. In addition, the terms "first", "second", etc. in the claims are used only as marks and are not numerical limitations on their objects.

[0039] The flowcharts shown in the accompanying drawings are for illustrative purposes only and do not necessarily include all contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps may be decomposed, while others may be combined or partially combined. Therefore, the actual execution order may vary depending on the actual situation.

[0040] In addition, in the description of the present disclosure, “a plurality of” means at least two, for example, two, three, etc., unless otherwise clearly and specifically defined.

[0041] Dynamic Random Access Memory (DRAM) is a semiconductor memory device commonly used in computers. It consists of many repeated memory cells. Each memory cell typically includes a capacitor and a transistor. The transistor's gate is connected to a word line, its drain is connected to a bit line, and its source is connected to a capacitor. The voltage signal on the word line controls the transistor's on and off state, allowing it to read data stored in the capacitor through the bit line or write data to the capacitor for storage.

[0042] In order to increase the capacitance of the capacitor, the capacitor often has a very high aspect ratio. In the process of forming the capacitor, the semiconductor structure is etched by a dry etching process to form a capacitor hole. However, dry etching often encounters asymmetric sputtering of plasma, which causes defects such as pits to appear on the inner wall of the lower part of the capacitor hole, making the upper and lower sizes of the capacitor hole uneven. Moreover, since the capacitor hole has a very high aspect ratio, the deeper the capacitor hole is (that is, the part closer to the bottom of the capacitor hole), the lower the concentration of plasma in the dry etching, and the etching speed slows down, resulting in incomplete etching, making the size of the lower part of the capacitor hole smaller than the size of the upper part, and the capacitor formed is prone to a conical shape. Moreover, due to stress, the formed capacitor is prone to tilt. The above situation causes poor contact between the capacitor and the landing pad, affecting the electrical performance of the semiconductor structure.

[0043] Based on this, the present disclosure provides a method for preparing a semiconductor structure. Figure 1 As shown, the method includes steps: S110 to S170.

[0044] S110: providing a substrate 1.

[0045] S120 : forming a first stack 2 on the substrate 1 , and forming a plurality of first openings 23 in the first stack 2 .

[0046] S130 : forming a fence 5 on the inner wall of the first opening 23 .

[0047] S140 : forming a second laminate 6 on the first laminate 2 and the fence 5 .

[0048] S150 : forming a first mask layer 7 having a capacitor pattern S1 on the second stack 6 .

[0049] S160: Based on capacitor pattern S1, a first etching process is used to etch from the second stack 6 toward the substrate 1 until a first capacitor hole 8 is formed. The sidewalls of the bottom of the first capacitor hole 8 expose at least a portion of the fence 5. In the first etching process, the etching selectivity of the second stack 6 and the fence 5 is different. S170: A second etching process is used to etch the first mask layer 7 and the fence 5 at the bottom of the first capacitor hole 8, exposing the substrate 1, thereby transforming the first capacitor hole 8 into a second capacitor hole 8'.

[0050] In the embodiment of the present disclosure, a fence 5 is formed on the inner wall of the first opening 23 of the first stack 2. When etching the second stack 6 based on the capacitor pattern S1, the etching gas has different etching selectivities for the second stack 6 and the fence 5, so that the second stack 6 can be etched to form a first capacitor hole 8. The fence 5 is located at the bottom of the first capacitor hole 8 and plays a placeholder role, thereby avoiding the situation where the bottom size of the first capacitor hole 8 is reduced due to incomplete etching of the sidewall of the bottom of the first capacitor hole 8 due to the high aspect ratio of the first capacitor hole. The second etching process expands the size of the bottom of the first capacitor hole 8, that is, ensures that the second capacitor hole 8 is not completely etched. The size of the capacitor hole 8' is more uniform, especially in the vertical direction Y. At the same time, the fence 5 also plays a protective role, avoiding defects in the side wall of the first capacitor hole 8 due to uneven sputtering of the etching gas at the bottom of the first etching process. When the second etching process is used to remove the fence 5 at the bottom, the fence 5 at the bottom of the first capacitor hole 8 will continue to etch downward along the outline of the top opening of the first capacitor hole 8, forming a second capacitor hole 8' with smoother side walls, thereby improving the aspect ratio of the second capacitor hole 8' and further improving the electrical performance and yield of the semiconductor structure.

[0051] The following is a detailed description of the method for preparing the semiconductor structure according to the embodiment of the present disclosure.

[0052] The direction perpendicular to the substrate 1 is defined as the vertical direction Y. The radial dimension in the embodiment of the present disclosure refers to the dimension in the horizontal plane perpendicular to the vertical direction Y. For example, the capacitor pattern S1 can be a circular hole, and the radial dimension of the capacitor pattern S1 is its diameter. In order to be able to show it more clearly, the accompanying drawings of the embodiment of the present disclosure show a cross-sectional schematic diagram of the semiconductor structure during the preparation process, and the direction perpendicular to the vertical direction Y is defined as the horizontal direction X. The horizontal direction X can be any horizontal direction in the horizontal plane perpendicular to the vertical direction Y. In the figure, the radial dimension can be shown as the dimension along the horizontal direction X. As shown in the figure Figure 3 As shown, the radial dimension d1 of the first opening 23 in the embodiment of the present disclosure refers to the dimension of the first opening 23 along the horizontal direction X. It can also be understood that the radial dimension is a key dimension and will not be described in detail here. The above definition of direction is only for the convenience of description and is not limiting.

[0053] S110: providing a substrate 1.

[0054] like Figure 2 , showing a substrate 1 and a first stack 2 formed on the substrate 1 according to an embodiment of the present disclosure. The substrate 1 may include a semiconductor substrate having shallow trench isolation formed thereon, with an active region disposed between the shallow trench isolations. The semiconductor substrate also includes a wordline structure and a bitline structure, which are disposed at different heights of the semiconductor substrate and are both connected to the active region. The wordline structure may include a high-k dielectric layer, a polysilicon layer, a work function layer, and a wordline metal layer.

[0055] In some embodiments, the substrate of the semiconductor device may be made of silicon, silicon carbide, silicon-on-insulator (SiO2), silicon-on-insulator (SiO2), silicon-germanium-on-insulator (SiGe), or germanium-on-insulator (GeO2). The semiconductor substrate may also be implanted with certain dopants to modify electrical parameters based on design requirements.

[0056] In some embodiments, the base 1 further includes a plurality of pads, which may be disposed in the semiconductor substrate. The pads may be electrically connected to the drain of the transistor and used to connect a capacitor to provide a circuit for the semiconductor structure.

[0057] S120 : forming a first stack 2 on the substrate 1 , and forming a plurality of first openings 23 in the first stack 2 .

[0058] Continue to refer Figure 2 , a first stacked layer 2, an initial mask layer 3 and an initial photoresist 4 are sequentially stacked on a substrate 1 by a deposition process. Figure 3 As shown, the initial photoresist 4 is etched through an exposure process and a development process so that the initial photoresist 4 has a pattern of a first opening 23, and then the pattern of the first opening 23 is transferred to the initial mask layer 3. The first stack 2 is etched through the initial mask layer 3 so that the first stack 2 has multiple first openings 23.

[0059] In some embodiments, forming the first stack 2 on the substrate 1 includes forming a first supporting layer 21 on the substrate 1, and forming a first sacrificial layer 22 on the first supporting layer 21. The first supporting layer 21 may be made of silicon nitride, and the first sacrificial layer 22 may be made of silicon oxide or silicon oxynitride. The initial mask layer 3 may include an initial hard mask layer 31 and an initial silicon oxynitride layer 32 stacked in sequence, with an initial photoresist 4 formed on the initial silicon oxynitride layer 32. When etching the first stack 2 to form the first opening 23, the etching stops in the first supporting layer 21. The first supporting layer 21 supports the first sacrificial layer 22.

[0060] S130 : forming a fence 5 on the inner wall of the first opening 23 .

[0061] In some embodiments, as Figure 4and Figure 5 As shown, a layer of fence 5 with uniform thickness can be formed on the surface of the first sacrificial layer 22 by using a deposition process.

[0062] In some embodiments, the ratio of the radial dimension of the first opening 23 occupied by the fence 5 is 1 / 3 to 1. That is, after the fence 5 is filled in the first opening 23, the radial dimension 1 of the first opening 23 occupied by the fence 5 in the direction from the inner wall of the first opening 23 to the central axis of the first opening 23 is at least 1 / 3 of the radial dimension of the first opening 23. Figure 4 As shown, in the first opening 23, the dimension of the two opposing fences 5 along the horizontal direction X is at least 1 / 3 of the dimension of the first opening 23 along the horizontal direction X. Specifically, the ratio of the fence 5 to the radial dimension d1 of the first opening 23 can be 1 / 3, 1 / 2, 2 / 3, 3 / 4, etc., and can also be 1, that is, the fence 5 completely fills the first opening 23 in the radial direction. Those skilled in the art can set it according to actual conditions, and no special limitation is made here.

[0063] In some embodiments, the ratio of the radial dimension d1 of the fence 5 to the first opening 23 is less than 1, that is, in the radial direction (horizontal direction X in the figure), the fence 5 does not fill the first opening 23, and an opening is formed in the fence 5. For the convenience of description, the opening formed by the fence 5 is called the second opening 23', that is, after the fence 5 is formed, the first opening 23 is formed into the second opening 23'. Figure 4 As shown, the radial dimension d2 of the second opening 23 ′ is smaller than the radial dimension d1 of the first opening 23 .

[0064] Based on this, the method of the embodiment of the present disclosure further includes: removing the fence 5 and the first stacked layer 2 corresponding to the bottom wall of the second opening 23 ′ to expose the substrate 1 .

[0065] Specifically, the fence 5 located on the top surface of the first stack 2 and the fence 5 extending in the horizontal direction X corresponding to the bottom wall of the second opening 23' are etched back, and then the first support layer 21 extending in the horizontal direction X located below can be etched away to expose the surface of the substrate 1 corresponding to the second opening 23'. The exposed substrate 1 has a pad to facilitate electrical connection with the capacitor to be formed. In the embodiment of the present disclosure, etching the first support layer 21 located at the bottom of the second opening 23' separately can more thoroughly remove this portion of the first support layer 21, avoiding the situation in which the first support layer 21 is not completely etched in the subsequent dry etching process due to its location at the bottom.

[0066] In other embodiments, after etching back the fence 5 located on the top surface of the first stack 2 and the fence 5 located on the bottom wall of the second opening 23' and extending in the horizontal direction X, the etching can be stopped, that is, the first supporting layer 21 located below and extending in the horizontal direction X is no longer etched. This portion of the first supporting layer 21 can be removed together with the removal of the second stack 6 in the subsequent step S160, thereby saving process steps.

[0067] In some embodiments, the ratio of the fence 5 to the radial dimension d1 of the first opening 23 is 1. That is, in the horizontal direction X, the fence 5 completely occupies the first opening 23, and the fence 5 does not form the second opening 23'. In this case, in the above embodiment, only the fence 5 located on the top surface of the first stack 2 is etched back, leaving the remaining fence 5 and the first supporting layer 21 in the first opening 23.

[0068] In some embodiments, regardless of whether the fence 5 completely fills the first opening 23 in the radial direction, the height of the fence 5 in the vertical direction Y is at least 1 / 2 of the height of the first stack 2. Specifically, the height of the fence 5 can be 2 / 3, 3 / 4, 4 / 5, or 5 / 6 of the height of the first stack 2, or the height of the fence 5 can be the same as the height of the first stack 2, without particular limitation. The height of the first stack 2 can be the depth of the first opening 23.

[0069] S140 : forming a second laminate 6 on the first laminate 2 and the fence 5 .

[0070] In some embodiments, forming the second stack 6 on the first stack 2 and the fence 5 includes: forming the second stack 6 in the second opening 23'. Figures 6 to 8 As shown, when there is a second opening 23 ′, the second stack 6 is filled in the second opening 23 ′ and is continuously deposited and formed on the first stack 2 and the fence 5 .

[0071] like Figure 6 As shown, forming the second stack 6 on the first stack 2 and the fence 5 includes: forming a second sacrificial layer 61 on the first stack 2 and the fence 5 (when there is a second opening 23', including forming the second sacrificial layer 61 in the second opening 23'), forming a second supporting layer 62 on the second sacrificial layer 61. Forming a third sacrificial layer 63 on the second supporting layer 62, and forming a third supporting layer 64 on the third sacrificial layer 63.

[0072] The second sacrificial layer 61 and the third sacrificial layer 63 may be made of silicon oxide, and the second sacrificial layer 61, the third sacrificial layer 63, and the first sacrificial layer 21 in the first stack 2 may be made of the same material. The second supporting layer 62 and the third supporting layer 64 may be made of silicon nitride or silicon oxynitride, and the second supporting layer 62 and the third supporting layer 64 may be made of the same material, and the second supporting layer 62 and the third supporting layer 64 serve a supporting function.

[0073] In some embodiments, the second stack 6 includes multiple sacrificial layers and support layers stacked in sequence, that is, the second stack 6 may also include a fourth sacrificial layer and a fourth support layer (not shown in the figure) provided on the third support layer 64, or may also include a fifth sacrificial layer and a fifth support layer provided on the fourth support layer. Those skilled in the art can set the number of sacrificial layers and support layers in the second stack 6 according to the actual required depth of the second capacitor hole 8', and no special limitation is made here.

[0074] In some embodiments, the fences 5 fill the first openings 23 in the radial direction, that is, no second openings 23 ′ are formed between the fences 5 . The second laminate 6 is formed on the first laminate 2 and the fences 5 , which will not be described in detail here.

[0075] S150 : forming a first mask layer 7 having a capacitor pattern S1 on the second stack 6 .

[0076] like Figure 6 As shown, a first mask layer 7 is formed on the second stack 6. The first mask layer 7 includes a first hard mask layer 71, a first oxide layer 72, a second hard mask layer 73, a first oxynitride layer 74, and a first photoresist 75 having a capacitor pattern S1, which are stacked in sequence. The capacitor pattern S1 of the first photoresist 75 is transferred to the first oxynitride layer 74, and the capacitor pattern S1 is transferred to the second hard mask layer 73 through the first oxynitride layer 74, as shown in FIG. Figure 7 As shown, the capacitor pattern S1 is transferred to the first oxide layer 72 through the second hard mask layer 73, as shown in FIG. Figure 8 As shown, the capacitor pattern S1 is transferred to the first hard mask layer 71 through the first oxide layer 72 .

[0077] The first hard mask layer 71 and the second hard mask layer 73 may be made of at least one of polysilicon and carbon. The first oxide layer 72 may be made of silicon oxide, and the first oxynitride layer 74 may be made of silicon oxynitride, which are not particularly limited.

[0078] In some embodiments, the capacitor pattern S1 is located above the first opening 23, and the radial dimension of the capacitor pattern S1 is less than or equal to the radial dimension d1 of the first opening 23. The capacitor pattern S1 being located above the first opening 23 can be understood as the center of the projection of the capacitor pattern S1 on the substrate 1 coinciding with the center of the projection of the first opening 23 on the substrate 1. The capacitor pattern S1 is actually the pattern that will subsequently form the first capacitor hole 8 and the second capacitor hole 8'.

[0079] In some other embodiments, the capacitor pattern S1 is located above the first stack 2 (not shown in the figure), and a radial dimension of the capacitor pattern S1 is greater than or equal to a radial dimension d1 of the first stack 2 between two adjacent first openings 23 .

[0080] S160: Based on the capacitor pattern S1, a first etching process is used to etch from the second stack 6 toward the substrate 1 to form a first capacitor hole 8, and the side wall of the bottom of the first capacitor hole 8 exposes at least a portion of the fence 5; wherein, in the first etching process, the etching selectivity ratios of the second stack 6 and the fence 5 are different.

[0081] In some embodiments, as Figure 9 As shown, the capacitor pattern S1 is located above the first opening 23. Based on the capacitor pattern S1, a first etching process is used to etch from the second stack 6 toward the direction close to the substrate 1 to form a first capacitor hole 8, including: using the first etching process to etch the second stack 6 until the substrate 1 is exposed to form the first capacitor hole 8.

[0082] In S140, if Figure 4 and Figure 5 As shown, after the fence 5 forms the second opening 23', the fence 5 located on the top surface of the first stack 2 and the fence 5 extending along the horizontal direction X corresponding to the bottom wall of the second opening 23' are etched back. Regardless of whether the first support layer 21 located at the bottom of the second opening 23' is further removed, since the material of the first support layer 21 is the same or similar to that of the second stack 6, for example, both are silicon oxide and / or silicon nitride, even if the first support layer 21 extending along the horizontal direction X at the bottom of the second opening 23' is not removed in S140, the first support layer 21 located at the bottom of the second opening 23' can be etched away at the same time after the second stack 6 is etched using the first etching process, so that the formed first capacitor hole 8 can expose the substrate 1 (as shown in FIG. Figure 9 shown).

[0083] In other embodiments, the ratio of the radial dimension d1 of the fence 5 to the first opening 23 is 1, and based on the capacitor pattern S1, a first etching process is used to etch from the second stack 6 toward the direction close to the substrate 1 to form the first capacitor hole 8, including: using the first etching process to etch the second stack 6 to the top surface of the fence 5 to form the first capacitor hole 8.

[0084] Specifically, the second opening 23' is not formed in the fence 5, that is, the fence 5 fills the first opening 23 in the radial direction (not shown in the figure), and the second stack 6 is formed on the fence 5. In this case, the bottom of the first capacitor hole 8 formed by etching the second stack 6 is the fence 5, and the substrate 1 is not exposed.

[0085] In other embodiments, when the capacitor pattern S1 is located above the first stack 2, the first etching process is used to etch from the second stack 6 toward the substrate 1 to form the first capacitor hole 8, including: using the first etching process to etch from the second stack 6 to the surface of the substrate 1 to form the first capacitor hole 8. Therefore, the radial size of the capacitor pattern S1 is only greater than or equal to the first stack 2 between two adjacent first openings 23 (such as Figure 3 The inner wall of the bottom of the first capacitor hole 8 formed by the columnar first stack 2 shown in FIG. 1 can expose the fence 5.

[0086] In some embodiments, the first etching process is a dry etching process, and the etching gas used has an etching selectivity ratio of 5 to 10 for the first stack 2, the second stack 6, and the fence 5, respectively. That is, the etching gas in the first etching process has a greater etching selectivity for the first stack 2 and the second stack 6. Specifically, in addition to the two end values ​​mentioned above, the etching selectivity can also be 6, 7, 8, or 9, and is not specifically limited here. Of course, the first etching process can also be other processes capable of directional etching, and those skilled in the art can select according to actual conditions, and is not specifically limited here.

[0087] The etching selectivity refers to the ratio of the etching rate of the etched material to the etching rate of another material under the same etching conditions. That is, in the embodiment of the present disclosure, the first etching process can etch the first stack 2 and the second stack 6 without etching the fence 5. As the etching depth increases, even if uneven plasma sputtering occurs, the fence 5 will not be etched. In other words, the fence 5 protects the inner wall of the first capacitor hole 8, so that the inner wall of the formed first capacitor hole 8 will not have defects.

[0088] In other embodiments, the etching gas of the first etching process has a slightly smaller etching selectivity for the first stack 2, the second stack 6, and the fence 5, respectively. In this way, when etching to the bottom of the first capacitor hole 8, it will be easier to etch the fence 5, thereby avoiding incomplete etching of the bottom of the first capacitor hole 8 due to the lower concentration of the etching gas at the bottom, and making the size of the first capacitor hole 8 in the vertical direction Y more uniform.

[0089] In some embodiments, the etching gas used in the first etching process is at least one of CF4, C3F8, and CHF3, which is not specifically limited here.

[0090] S170 : using a second etching process to etch the first mask layer 7 and the fence 5 located at the bottom of the first capacitor hole 8 to expose the substrate 1 , so that the first capacitor hole 8 is transformed into a second capacitor hole 8 ′.

[0091] In some embodiments, when the capacitor pattern S1 is located above the first opening 23, since the radial dimension of the capacitor pattern S1 is less than or equal to the radial dimension d1 of the first opening 23, the capacitor pattern S1 has the same pattern as the first capacitor hole 8 and the second capacitor hole 8'. As a result, after etching the second stack 6, the fence 5 is located at the bottom of the first capacitor hole 8 and protrudes from the sidewalls of the first capacitor hole 8. To ensure the consistency of the radial dimension of the first capacitor hole 8, the fence 5 protruding from the sidewalls of the first capacitor hole 8 needs to be removed.

[0092] The fence 5 protruding from the sidewall of the bottom of the first capacitor hole 8 is removed by a second etching process to form a second capacitor hole 8' and expose the substrate 1. Figure 10 As shown, the sidewalls of the second capacitor hole 8' have a consistent radial dimension d3, making the sidewalls of the second capacitor hole 8' smoother. When the radial dimension of the capacitor pattern S1 is smaller than the radial dimension of the first opening 23, as shown in FIG. Figure 10 As shown, the bottom of the side wall of the formed second capacitor hole 8' is the fence 5. When the radial dimension of the capacitor pattern S1 is equal to the radial dimension of the first opening 23, the second etching process completely removes the fence 5, and the side wall of the formed second capacitor hole 8' does not include the fence 5 (not shown in the figure). In this way, the subsequent process of removing the fence 5 is saved.

[0093] In some embodiments, the second etching process can be a dry etching process, and the etching gas used has an etching selectivity of 5 to 10 for the fence 5 and the first stack 2. Specifically, in addition to the above two end values, the etching selectivity can also be 6, 7, 8, or 9, which are not particularly limited here. The etching gas used in the second etching process is at least one of Cl2 and HBr. Of course, the second etching process can also be other processes capable of directional etching, which can be selected by those skilled in the art according to actual conditions, and are not particularly limited here.

[0094] The etching gas used in the second etching process has a higher etching selectivity to the fence 5. Figure 10 As shown, the fence 5 protruding from the side wall of the first capacitor hole 8 can be effectively removed without damaging other parts of the side wall of the first capacitor hole 8 (for example, the side wall formed by the second stack 6), so that the side wall of the formed second capacitor hole 8' is smoother, ensuring the consistency of the radial dimension d3 of the second capacitor hole 8'.

[0095] In some embodiments, the depth of the second capacitor hole 8' is greater than or equal to 1000nm. Specifically, the depth of the second capacitor hole 8' can be 1000nm, 1100nm, 1200nm, 1300nm, 1500nm, 1600nm, 1800nm, which is not specifically limited here. In some embodiments, the aspect ratio of the second capacitor hole is greater than or equal to 35:1. Specifically, in addition to the above ratios, it can also be 38:1, 40:1, 42:1, 45:1, etc., which is not specifically limited here. Among them, the aspect ratio of the second capacitor hole is the ratio of the depth of the second capacitor hole in the vertical direction Y to its radial dimension d3. By setting the fence 5, the second capacitor hole 8' of the embodiment of the present disclosure can have the above depth and high aspect ratio, and the size of the second capacitor hole 8' is uniform and will not be tilted, so that the capacitor formed in the second capacitor hole 8' can have a higher aspect ratio and will not be tilted, ensuring good contact between the capacitor and the pad.

[0096] In some embodiments, the first mask layer 7 formed in S150 includes a first hard mask layer 71. The first hard mask layer 71 and the fence 5 can be made of the same material. The method of the embodiment of the present disclosure also includes: using a second etching process to etch the fence 5 located at the bottom of the first capacitor hole 8 while removing the first hard mask layer 71.

[0097] Among them, the materials of the first hard mask layer 71 and the fence 5 can both be polysilicon or carbon. Therefore, when the second dry etching is used to remove the fence 5 protruding from the side wall of the first capacitor hole 8, the first mask layer 7 can be removed at the same time, saving the process of removing the first hard mask layer 71 separately and saving energy consumption.

[0098] In some embodiments, after etching the fence 5 and the first hard mask layer 71 at the bottom of the first capacitor hole 8 using a second etching process, the method further includes: etching the first stack 2 protruding from the sidewall of the second capacitor hole 8', the residual oxide of the first hard mask layer 71, and the residual oxide of the fence 5.

[0099] That is, during the etching process of the fence 5 and the first hard mask layer 71, oxides of the fence 5, such as silicon oxide, are likely to remain on the surface of the etched fence 5, and oxides of the first hard mask layer 71, such as silicon oxide, are likely to remain on the top surface of the second stack 6. These oxides are etched away to prevent them from adhering to the capacitor hole 8 and affecting the subsequent formation of the capacitor. In addition, since the bottom end of the fence 5 is formed on the first stack 2, specifically, Figure 9As shown, the bottom end of the fence 5 is formed on the first supporting layer 21. After the second etching process is used to remove only the protruding fence 5, the first supporting layer 21 located at the bottom end of the protruding fence 5 protrudes from the second capacitor hole 8' along the horizontal direction X. In order to ensure the uniformity of the radial dimension d3 of the second capacitor hole 8', the protruding first supporting layer 21 needs to be removed.

[0100] Since the etching gas in the first etching process has a high etching selectivity for the second stack 6 (including materials such as silicon oxide and silicon nitride), in the embodiment of the present disclosure, the first etching process can be used to etch the first supporting layer 21 protruding from the side wall of the second capacitor hole 8' and the residual oxide without damaging the fence 5 and the substrate 1, thereby achieving further trimming of the second capacitor hole 8', avoiding the situation where the bottom size of the second capacitor hole 8' is too small due to insufficient etching due to the low etching gas concentration at the bottom of the second capacitor hole 8', further ensuring the uniformity of the second capacitor hole 8', and the contour of the second capacitor hole 8' is smoother, so that the capacitor finally formed based on the second capacitor hole 8' can have better contact with the pad in the substrate 1, thereby improving the electrical performance of the capacitor.

[0101] In some embodiments, the thickness of the fence 5 is 6 to 12 nm. Specifically, in addition to the two end values ​​mentioned above, the thickness of the fence 5 can also be 7 nm, 8 nm, 8.5 nm, 9 nm, 10 nm, 10.5 nm, or 11 nm. Those skilled in the art can set the thickness according to actual conditions, and no special limitation is made here. By setting the thickness of the fence 5 to 6 to 12 nm, the sidewalls of the first capacitor hole 8 can be protected when etching the second stack to form the first capacitor hole 8.

[0102] In some embodiments, as Figure 3 and Figure 10 As shown, the radial dimension d1 of the first opening 23 is 0 to 8 nm larger than the radial dimension d3 of the second capacitor hole 8'. Specifically, in addition to the two end values ​​mentioned above, it can also be 0.5 nm, 1 nm, 2 nm, 3 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm or 7.5 nm, which is not specifically limited here. When it is 0 nm, the radial dimension d1 of the first opening 23 is equal to the radial dimension d3 of the second capacitor hole 8'. In the second etching process, the fence 5 can be completely removed, and there is no need to remove the fence 5 later, saving process and consumables. When the radial dimension d1 of the first opening 23 is larger than the radial dimension d3 of the second capacitor hole 8', in the second etching process, the fence 5 protruding from the side wall of the first capacitor hole 8 can be removed. The remaining fence 5 serves as the side wall of the bottom of the second capacitor hole 8', playing a supporting role, further avoiding the situation where the side wall is tilted due to stress due to the excessive depth of the second capacitor hole 8'.

[0103] In some embodiments, the fence 5 may be made of at least one of polysilicon and carbon. These materials can have different etching selectivities from the second stack 6 to protect the sidewalls and provide support during the first etching process.

[0104] In some embodiments, after forming the second capacitor hole 8 ′, the method further includes the following contents A to G.

[0105] A: A lower electrode layer 9 is formed on the inner wall of the second capacitor hole 8 ′ and the top surface of the second stacked layer 6 .

[0106] like Figure 11 As shown, a deposition process can be used to conformally form the lower electrode layer 9 in the second capacitor hole 8'. The material of the lower electrode layer 9 can include at least one of metal nitride and metal silicide species, such as titanium nitride, titanium silicide, nickel silicide, etc.

[0107] B: A second mask layer 10 having a first pattern S2 is formed on the lower electrode layer 9 , and the first pattern S2 exposes a portion of the lower electrode layer 9 on the top surface of the second stack 6 .

[0108] like Figure 12 As shown, forming the second mask layer 10 having the first pattern S2 on the lower electrode layer 9 includes forming a third hard mask layer 101, a second silicon oxynitride layer 102, and a second photoresist 103 stacked in sequence on the lower electrode layer 9. The second photoresist 103 has the first pattern S2.

[0109] The first pattern S2 is transferred from the second photoresist 103 to the second silicon oxynitride layer 102, and then transferred from the second silicon oxynitride layer 102 to the third hard mask layer 101. The first pattern S2 exposes a portion of the lower electrode layer 9 on the top surface of the second stack 6, that is, exposes a portion of the lower electrode layer 9 on the top surface of the third supporting layer 64.

[0110] C: Based on the first pattern S2 , the exposed lower electrode layer 9 is removed to expose the third supporting layer 64 .

[0111] D: removing the exposed third supporting layer 64 .

[0112] like Figure 13 As shown, a wet etching process or a dry etching process may be used to remove the exposed lower electrode layer 9 , and then the exposed third supporting layer 64 may be removed.

[0113] E: The third sacrificial layer 63 is removed to expose the second supporting layer 62 corresponding to the first pattern S2.

[0114] like Figure 14As shown, a wet etching process is used to remove all third sacrificial layers 63 in the second stack 6. The wet etching process can use hydrofluoric acid (HF) and ammonium fluoride (NH4F) as etchants, and the etching degree can be controlled by adjusting the concentration of the etchant.

[0115] F: removing the exposed second supporting layer 62 .

[0116] like Figure 15 As shown, the wet etching process can be used again to remove the exposed second support layer 62. In the embodiment of the present disclosure, the first pattern S2 corresponds to a portion of the third support layer 64 of the second stack 6, in order to remove a portion of the third support layer 64 to save space.

[0117] G: The second sacrificial layer 61 and the remaining fence 5 are removed.

[0118] like Figure 16 As shown, the second sacrificial layer 61 and the fence 5 may be removed by a wet etching process.

[0119] In some embodiments, a wet etching process is used to remove the second sacrificial layer 61 and the remaining fence 5 . The etchant used in the wet etching process may further include an additive capable of removing the fence 5 .

[0120] Among them, the etchant used in the wet etching process can be a mixed liquid of hydrofluoric acid (HF) and ammonium fluoride (NH4F). When the material of the fence 5 is polysilicon, the additive can include a strong oxidant and / or a strong acid. The strong oxidant can be, for example, hydrogen peroxide, and the strong acid can be, for example, nitric acid. When the material of the fence 5 is carbon, the additive can include sulfuric acid (H2SO4).

[0121] The deposition process used in the method of the embodiment of the present disclosure can be a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process, which is not specifically limited here.

[0122] In some embodiments, as Figure 16 As shown, the method may further include forming a capacitor. Specifically, forming the capacitor includes forming a dielectric layer 11 on the lower electrode layer 9 and forming an upper electrode layer 12 on the dielectric layer 11. The capacitor includes the lower electrode layer 9, the dielectric layer 11 and the upper electrode layer 12.

[0123] The material of the upper electrode layer 12 can be the same as that of the lower electrode layer 9, and can include at least one of a metal nitride and a metal silicide, such as titanium nitride, titanium silicide, nickel silicide, etc. The dielectric layer 11 can be a high-K dielectric layer to increase the capacitance per unit area of ​​the capacitor. The material of the dielectric layer 11 can include at least one of ZrOx, HfOx, ZrTiOx, RuOx, SbOx, and AlOx. The dielectric layer 11 can also include multiple layers of different materials.

[0124] In the disclosed embodiment, the aspect ratio of the capacitor finally formed is greater than 35:1. For example, the aspect ratio of the capacitor is 38:1, 40:1, 42:1, 45:1, etc., which is not specifically limited here. Moreover, the capacitor does not tilt at such a high aspect ratio and can make good contact with the pad in the substrate 1, thereby increasing the capacity of the capacitor, ensuring the electrical performance of the semiconductor structure, and improving the yield. Among them, the aspect ratio of the capacitor can be understood as the ratio of the size of the capacitor in the vertical direction Y to the maximum size of the capacitor in the horizontal direction X.

[0125] In summary, in the process of preparing the semiconductor structure, the fence 5 is formed on the inner wall of the first opening 23 of the first stack 2 in the embodiment of the present disclosure. When the second stack 6 is etched based on the capacitor pattern S1, the etching gas has different etching selectivities for the second stack 6 and the fence 5, so that the second stack 6 can be etched to form the first capacitor hole 8. The fence 5 is located at the bottom of the first capacitor hole 8 and plays a placeholder role, thereby avoiding the situation where the bottom size of the first capacitor hole 8 is reduced due to incomplete etching of the sidewall at the bottom of the first capacitor hole 8 due to the high aspect ratio of the first capacitor hole. The second etching process expands the size of the bottom of the first capacitor hole 8, that is, ensures that the size of the second capacitor hole 8' is more uniform, especially in the vertical direction Y. At the same time, the fence 5 also plays a role in The protective effect is achieved to avoid defects in the side walls of the first capacitor hole 8 due to uneven sputtering of the etching gas at the bottom during the first etching process. When the second etching process is used to simultaneously remove the first mask layer and the fence 5 at the bottom, the fence 5 at the bottom of the first capacitor hole 8 will continue to be etched downward along the outline of the top opening of the first capacitor hole 8. When the first mask layer 7 at the top is removed, the bottom of the first capacitor hole 8 is corrected to form a second capacitor hole 8' with smoother side walls, thereby improving the aspect ratio of the second capacitor hole 8'. When the lower electrode layer 9 is subsequently formed on the second capacitor hole 8', the contact effect between the lower electrode layer 9 and the pad in the substrate 1 can be further improved, thereby improving the electrical performance and yield of the semiconductor structure.

[0126] The embodiments of the present disclosure further provide a semiconductor structure, which can be prepared by the method in any of the above embodiments. The specific steps will not be described in detail here.

[0127] In some embodiments, the semiconductor structure includes a capacitor.

[0128] In the semiconductor structure of the disclosed embodiment, during the preparation process using the above method, a fence 5 is formed on the inner wall of the first opening 23 of the first stack 2. When the second stack 6 is etched based on the capacitor pattern S1, the etching gas has different etching selectivities for the second stack 6 and the fence 5, so that the second stack 6 can be etched to form a first capacitor hole 8. The fence 5 is located at the bottom of the first capacitor hole 8 and plays a placeholder role, thereby avoiding the situation where the bottom size of the first capacitor hole 8 is reduced due to incomplete etching of the sidewall at the bottom of the first capacitor hole 8 due to the high aspect ratio of the first capacitor hole. The second etching process expands the size of the bottom of the first capacitor hole 8, that is, ensures The size of the second capacitor hole 8' is more uniform, especially in the vertical direction Y. At the same time, the fence 5 also plays a protective role, avoiding the situation where defects are generated on the side wall of the first capacitor hole 8 due to uneven sputtering of the etching gas at the bottom of the first etching process. When the second etching process is used to remove the first mask layer and the fence 5 at the bottom, the fence 5 at the bottom of the first capacitor hole 8 will continue to etch downward along the outline of the top opening of the first capacitor hole 8. When the first mask layer 7 at the top is removed, the bottom of the first capacitor hole 8 is corrected to form a second capacitor hole 8' with smoother side walls, thereby improving the aspect ratio of the second capacitor hole 8'. Therefore, the lower electrode layer 9 formed on the second capacitor hole 8' in the semiconductor structure of the embodiment of the present disclosure can have good contact with the pad in the substrate 1, and the semiconductor structure of the embodiment of the present disclosure has better electrical performance and yield.

[0129] It should be understood that the present disclosure is not limited in its application to the detailed structure and arrangement of the components set forth in this specification. The present disclosure is capable of other embodiments and can be implemented and carried out in a variety of ways. The aforementioned variations and modifications fall within the scope of the present disclosure. It should be understood that the present disclosure disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or evident in the text and / or the drawings. All of these different combinations constitute multiple alternative aspects of the present disclosure. The embodiments described in this specification illustrate the best known ways to implement the present disclosure and will enable those skilled in the art to adopt the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a first stack on the substrate, and forming a plurality of first openings in the first stack; forming a fence on an inner wall of the first opening; forming a second laminate on the first laminate and the fence; forming a first mask layer having a capacitor pattern on the second stack; Based on the capacitor pattern, a first etching process is used to etch from the second stacked layer toward the substrate to form a first capacitor hole, wherein the sidewall of the bottom of the first capacitor hole exposes at least a portion of the fence; wherein, in the first etching process, the second stacked layer and the fence have different etching selectivities; The first mask layer and the fence at the bottom of the first capacitor hole are etched using a second etching process to expose the substrate, so that the first capacitor hole is transformed into a second capacitor hole.

2. The method according to claim 1, characterized in that The capacitor pattern is located above the first opening, and a radial dimension of the capacitor pattern is smaller than or equal to a radial dimension of the first opening.

3. The method according to claim 2, characterized in that The radial dimension of the first opening is larger than the radial dimension of the second capacitor hole by 0-8 nm.

4. The method according to claim 1, wherein The capacitor pattern is located above the first stack, and a radial dimension of the capacitor pattern is greater than or equal to a radial dimension of the first stack between two adjacent first openings; The method of etching from the second stacked layer toward the substrate to form a first capacitor hole by using a first etching process includes: A first etching process is adopted to etch from the second stacked layer to the surface of the substrate to form the first capacitor hole.

5. The method according to claim 1, wherein The depth of the second capacitor hole is greater than or equal to 1000 nm; and / or, The aspect ratio of the second capacitor hole is greater than or equal to 35:

1.

6. The method according to claim 1, characterized in that The ratio of the fence to the radial dimension of the first opening is 1 / 3 to 1.

7. The method according to claim 1, characterized in that The first etching process is a dry etching process, and an etching gas used has an etching selectivity ratio of 5 to 10 to the first stacked layer, the second stacked layer, and the fence.

8. The method according to claim 1, characterized in that The second etching process is a dry etching process, and the etching selectivity ratio of the etching gas used to the fence and the first stacked layer is 5-10.

9. The method according to any one of claims 1 to 8, characterized in that forming a first stack on the substrate, comprising: forming a first supporting layer on the substrate; forming a first sacrificial layer on the first supporting layer; The first opening is located not only in the first supporting layer, but also in the first sacrificial layer.

10. The method according to claim 9, characterized in that Forming a second stack on the first stack and the fence comprises: forming a second sacrificial layer on the first stack and the fence; forming a second supporting layer on the second sacrificial layer; forming a third sacrificial layer on the second supporting layer; A third supporting layer is formed on the third sacrificial layer.

11. The method according to claim 10, characterized in that Also includes: forming a lower electrode layer on an inner wall of the second capacitor hole and a top surface of the second stack; forming a second mask layer having a first pattern on the lower electrode layer, wherein the first pattern exposes a portion of the lower electrode layer on the top surface of the second stack; Based on the first pattern, removing the exposed lower electrode layer to expose the third supporting layer; removing the exposed third supporting layer; removing the third sacrificial layer to expose the third supporting layer corresponding to the first pattern; removing the exposed second supporting layer; The second sacrificial layer and the remaining fence are removed.

12. The method according to claim 11, characterized in that The second sacrificial layer and the remaining fences are removed by a wet etching process, wherein an etchant used in the wet etching process includes an additive capable of removing the fences.

13. The method according to claim 11, characterized in that Also included is forming a capacitor, comprising: forming a dielectric layer on the lower electrode layer; forming an upper electrode layer on the dielectric layer; The capacitor includes the lower electrode layer, the dielectric layer and the upper electrode layer, and the lower electrode layer is a tubular electrode or a columnar electrode.

14. The method according to claim 1, wherein The material of the fence includes at least one of polysilicon and carbon.

15. A semiconductor structure, characterized in that The method according to any one of claims 1 to 14 is used for preparation.

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