Apparatus and methods for providing scalable ball grid array (BGA) assignment and PCB circuit trace branching patterns for RF chip interfaces.

Abstract

A pin diagram covers a surface area of ​​a layer on a printed circuit board (PCB). A pin diagram includes multiple electrical markings for each pin in the diagram and multiple blank spaces within the diagram. Each electrical marking can be assigned to a pin on the pin diagram. Each electrical marking includes a positive (P+) pin, a negative (P-) pin, or a ground (G) pin. If a space in the pin diagram has no electrical markings, it may include blank space / planar portions of the printed circuit board (PCB). A pin diagram may include multiple rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include channel cell blocks. Pin diagrams help couple two circuit elements together, connecting them to a layer of the PCB.

Description

[0001] Priority claims and related application statements

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 049,530, filed July 8, 2020, entitled “SYSTEM AND METHOD FOR PROVIDING A SCALABLE BALL GRID ARRAY (BGA) ASSIGNMENT AND A PCBCIRCUIT TRACE BREAKOUT PATTERN FOR RF CHIP INTERFACES”, filed pursuant to 35 USC §119(e), the entire contents of which are incorporated herein by reference, and is a non-provisional application of that U.S. Provisional Patent Application. Background Technology

[0003] With the expansion of fifth-generation (5G) portable computing devices (PCDs, i.e., mobile phones, laptop data cards, mobile hotspots, and various 5G modules) and the increasing bandwidth demands, the communication speed requirements between baseband integrated circuits (ICs) and radio frequency (RF 4G / 5G Sub 6) / 5G mmWave IF (intermediate frequency) ICs are also increasing. Exemplary on-chip / inter-chip communication speeds used to support communications such as 5G signals can include, but are not limited to, approximately 18.0 Gbps. Such communication speeds may become even higher in the near future.

[0004] To support these high-speed communications, PCDs contain IC packages with one or more semiconductor dies stacked vertically. Sometimes, the packages are in the same molding compound as the IC packages. Such multi-chip IC packages are often referred to as "system-in-package" (SIP) and chip-stacked "multi-chip module" (MCM).

[0005] The IC dies in these multi-chip IC packages can be electrically coupled to a printed circuit board (PCB) substrate using a ball grid array (BGA) flip-chip configuration. As understood by those skilled in the art, a BGA is a type of surface-mount package for ICs. Pin diagrams are used to plan how specific signals or communication interfaces exist on the PCB using a routing strategy. That is, the "pins" at the ends of the PCB traces are electrically connected to the "solder balls" of the BGA. Typically, more than one layer of printed circuit board may be needed to connect two ICs.

[0006] As data signals propagate along these communication lines at increasing speeds, designing predictable IC package pinouts that meet various metrics becomes increasingly challenging, including signal integrity targets such as, but not limited to, crosstalk or offset. System isolation targets between high-frequency signal channels are often unattainable unless a reliable ground return path for via transitions exists in the BGA breakout area.

[0007] If the pinout pattern is not systematic and intuitive, routing circuit traces on a PCB that supports high-speed communication signals can be challenging. Such a pinout pattern can lead to additional noise coupling and additional cost for original equipment manufacturers (OEMs) to add extra PCB layers. The signal integrity performance of high-speed communication channels within the PCB layer is critical to information transmission between the modem and the RFIC / IFIC.

[0008] Therefore, what is needed in the art is a system and method that provides a systematic and intuitive pin diagram pattern that can effectively support high-speed communication between IC packages having one or more vertically stacked semiconductor dies. Such a pin diagram pattern can help reduce signal crosstalk and / or offset between communication channels. Summary of the Invention

[0009] A method and apparatus for coupling two semiconductor dies to a layer of a printed circuit board (PCB) includes semiconductor dies stacked vertically relative to the PCB. The dies are coupled to the PCB using a ball grid array (BGA). Each die may include a microchip and can be coupled to the PCB using the BGA. A pinout corresponding to the BGA covers a surface area of ​​the PCB.

[0010] A pin diagram includes multiple electrical markers for each pin in the pin diagram and multiple blank spaces within the pin diagram. Each electrical marker can be assigned to a pin on the pin diagram. Each electrical marker can include one of a positive (P+) pin, a negative (P-) pin, and a ground (G) pin. If a space in the pin diagram has no electrical marker, it can include blank space / planar portion of a printed circuit board (PCB). In an alternative example, a space in the pin diagram without an electrical marker can include a pin, but that pin may not be connected to anything / not connected to any circuit element and can be characterized as floating relative to the electrical markers mentioned above.

[0011] The pin diagram may include multiple rows and a first repeating pin polarity pattern. The first repeating pin polarity pattern may include a channel cell block. The channel cell block may have a central area defined by four pin diagram cells, wherein two of the four pin diagram cells include two pins corresponding to a differential signal channel pair within the PCB.

[0012] The pin diagram may include multiple square cells, each representing an electrical mark for a pin or empty space. Each channel cell block may have one positive pin (P+) and one negative pin (P-), while the remaining two sub-regions of the central area comprise two empty spaces in the pin diagram.

[0013] Channel cell blocks (which can be 4×4 squares) can overlap each other along the length of the pin diagram. In another example, channel cell blocks (which can be 4×4 squares) do not overlap each other along the length of the pin diagram. Channel cell blocks can overlap at any size as long as the polarity pins (signal areas) (P+ / P-) do not overlap with another block. A channel cell block can include at least four to at least sixteen squares.

[0014] A pin diagram may include two boundaries: a first boundary and a second boundary, the first boundary corresponding to the edge of an integrated circuit (IC) package and the second boundary corresponding to the edge of a die.

[0015] The semiconductor die includes a modem, and the PCB supports radio frequency (RF) communication. The PCB can be included in a mobile phone.

[0016] As illustrated in the example, pinouts allow circuit traces or signal lines to be formed on a single layer or geometric plane of the PCB. In this way, by utilizing PCB layers with well-mapped traces / signal lines, multiple PCB layers are not required to support communication between two dies and / or two integrated circuits or combinations thereof.

[0017] According to another example, a method for planning the connection positions between circuit elements includes: selecting a first circuit element having a first ball grid array, and determining whether the first ball grid array includes a narrow pitch. If the first ball grid array includes a narrow pitch, then a first pin map having a sparse repeating pin polarity pin pattern is selected.

[0018] Next, select a second circuit element with a second ball grid array. Then, determine whether the second ball grid array includes a narrow pitch. If the second ball grid array includes a narrow pitch, select a second pin pattern with a sparse repeating pin polarity pin pattern.

[0019] The method also includes identifying locations on printed circuit board layers, wherein circuit traces connect pins of a first pin diagram to pins of a second pin diagram, and then placing pins on the printed circuit board layers according to the selected first and second pin diagrams.

[0020] Subsequently, the circuit traces are placed on the printed circuit board layer according to the marked positions, so that the pins of the printed circuit board layer and the circuit traces establish an electrical connection between the first circuit element and the second circuit element, thereby significantly reducing crosstalk between the circuit traces on the printed circuit board layer.

[0021] According to another example, if the first ball grid array includes a wide pitch, then a first pin pattern with a densely repeating pin polarity pattern is selected. Similarly, if the second ball grid array includes a wide pitch, then a second pin pattern with a densely repeating pin polarity pattern is selected. Attached Figure Description

[0022] In the accompanying drawings, unless otherwise specified, the same reference numerals are used throughout the various views to refer to the same parts. For reference numerals with letter characters such as "102A" or "102B", the letter characters can distinguish two similar parts or elements appearing in the same figure. When it is desired that the reference numerals cover all parts with the same reference numerals in all figures, the letter characters of the reference numerals may be omitted.

[0023] Figure 1 The illustration shows a schematic cross-sectional side view of a stacked multi-chip IC package coupled to a printed circuit board (PCB) substrate in a ball grid array (BGA) flip-chip configuration;

[0024] Figure 2A Illustration Figure 1 A side view of the IC package and its electrical conductors;

[0025] Figure 2B An isometric / perspective view of an IC package is shown, and specifically, an isometric / perspective view of the empty / blank side of the IC package opposite the electrical conductor is shown.

[0026] Figure 2C The diagram shows Figure 1 Another isometric / perspective view of the package, and specifically, it shows the side of the package having conductors arranged as a ball grid array (BGA);

[0027] Figure 3 The diagram illustrates a conductor. Figure 1 and Figure 2C A more detailed bottom view of the IC package;

[0028] Figure 4 yes Figure 5 A cross-sectional view of the component shown;

[0029] Figure 5 The diagram shows Figure 4 and Figure 1 An exemplary pin diagram of the top surface of the PCB shown, wherein the pin diagram is consistent with... Figure 3 The spherical grid array shown corresponds directly to this;

[0030] Figure 6 The diagram illustrates the branching and routing of circuit traces on a PCB, which is similar to... Figure 5 The pin diagram corresponds to this;

[0031] Figure 7A The illustration is similar to Figure 5 The illustrated pin diagram is a first exemplary embodiment of a pin diagram for ball grid array (BGA) coupling;

[0032] Figure 7B The diagram shows Figure 7A A magnified view of the square channel cell block / repeating pin polarity pattern highlighted in the image;

[0033] Figure 8 The illustration is similar to Figure 5 , Figure 7A and Figure 7B A second exemplary embodiment of the pin diagram shown is a pin diagram for ball grid array (BGA) coupling;

[0034] Figure 9 The diagram shows Figure 8 A magnified view of the repeating pin polarity pattern of the square channel unit highlighted in the image;

[0035] Figure 10 The illustration is similar to Figure 5 and Figures 7A-9 A third exemplary embodiment of the pin diagram shown is a pin diagram for ball grid array (BGA) coupling;

[0036] Figure 11 The illustration is similar to Figure 5 And Figure 7- Figure 9 The fourth exemplary embodiment of the pin diagram for ball grid array (BGA) coupling shown in the figure;

[0037] Figure 12 An exemplary embodiment of a PCD, such as that in a mobile phone, is illustrated, which can be used across certain chips as shown in Figure 7- Figure 11 Pin diagram;

[0038] Figure 13 This is a functional block diagram illustrating a possible physical layout of a modem SoC die and an RFIFIC SoC; and

[0039] Figure 14 This is a logic flowchart illustrating an exemplary method for planning the connection locations between circuit elements coupled together on a single layer of a printed circuit board. Detailed Implementation

[0040] As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or superior to other aspects.

[0041] As used in this description, the terms "component," "database," "module," "system," etc., are intended to refer to computer-related entities that can be hardware, firmware, a combination of hardware and software, software, or software being executed. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, a thread of execution, a program, and / or a computer. For illustration, both applications running on a computing device and the computing device itself can be components.

[0042] First refer to Figure 1 The illustration shows a schematic cross-sectional side view of a stacked multi-chip IC package 100a coupled to a PCB substrate 114 using a ball grid array (BGA). The BGA can support how the multi-chip IC package 100a is coupled to the flip-chip arrangement of the PCB substrate 114.

[0043] As understood by those skilled in the art, a flip-chip arrangement may include the following sequence of events regarding how a package or chip 100a is coupled to a PCB substrate 114: solder balls 116 may be deposited on each pad of chip 100a in a process known as wafer bumping. Figure 1 (Not shown in the diagram, but present on the surface of substrate 125). Then, chip 100a is flipped and positioned (as shown in the diagram). Figure 1 As shown, the solder ball 116 is positioned so that it faces the pin or connector 316 of the trace on the PCB substrate 114. The solder ball 116 is then remelted (typically using hot air reflow soldering) onto the pin 316 present on the PCB substrate 114. The mounted chip 100a can be underfilled using an electrically insulating adhesive.

[0044] The secondary IC package or chip 100a includes a primary IC die A 106 (also referred to herein as the “bottom IC die”) and two (2) secondary IC dies B, C 104a, 104b, all of which may be made of semiconductor materials such as, but not limited to, silicon and / or germanium. The IC dies 106, 104a, 104b may be any type of circuit element, such as an IC, a SoC, or a processing entity, such as, but not limited to, processing circuitry (i.e., radio frequency ICs, such as modems, baseband ICs), memory circuitry, or combinations thereof.

[0045] In one respect, the first-level IC die 106 is essentially a processing circuit IC, such as a modem chip, while the second-level dies 104a and 104b can include memory circuits, such as dual data rate type 3 (DDR3) synchronous dynamic random access memory (SDRAM) circuits. Of course, in other respects, dies 106, 104a, and 104b can be other types of processing and / or memory circuits.

[0046] The primary IC die 106 includes multiple integrated circuit components (e.g., transistors, capacitors, inductors, resistors, etc.). Similarly, the secondary IC dies 104a and 104b each include multiple integrated circuit components (e.g., transistors, capacitors, inductors, resistors, etc.).

[0047] Primary IC die 106 and secondary IC dies 104a and 104b can be coupled to substrate 125. Epoxy resin and / or resin molding compound 126 encase dies 106, 104a, 104b and substrate 125 to form package 100a.

[0048] The bottom of substrate 125 can be coupled to a plurality of electrical conductors 116. The electrical conductors 116 are coupled to a layer of printed circuit board 114. Specifically, the electrical conductors 116 can be coupled to metal pins 316 positioned on the top side 115 of PCB 114. The metal pins 316 will be described in more detail below.

[0049] Electrical conductor 116 may include solder balls, and therefore, as will be understood by those skilled in the art, IC package 100a may be electrically coupled to substrate 114 (and pins 316) in a ball grid array (BGA) flip-chip manner. However, electrical conductor 116 is not limited to solder balls and may be any metal, metal alloy, or conductive element capable of readily transmitting electrical signals. For example, electrical conductor 116 may be, but is not limited to, solder bumps, pillars, pins, column bumps, and / or column bump stacks.

[0050] Now for reference Figure 2A The diagram illustrates Figure 1 A side view of the IC package 100a and its electrical conductor 116. As described above and... Figure 2C As illustrated in more detail, these electrical conductors 116 can be arranged in a ball grid array (BGA). Figure 2B The illustration shows an isometric / perspective perspective view of IC package 100a, and specifically, an isometric / perspective view of the side of IC package 100a opposite the electrical conductor 116, which is empty / blank / without any objects.

[0051] Now for reference Figure 2C The diagram illustrates Figure 1Another isometric / perspective view of package 100a is shown, and specifically, it shows one side of package 100a having conductors 116 arranged in a ball grid array (BGA). The methods and systems described in this disclosure focus on pin diagram 505 (see...). Figure 5 ), which identifies the physical location of pins 316 on a layer of the printed circuit board (PCB) 114 and conductors 116 on the package (see Figure 1 and Figure 5 ).

[0052] Now for reference Figure 3 The figure shows a conductor 116. Figure 1 and Figure 2C A more detailed bottom view of the IC package 100a. Because conductor 116 is coupled to other conductors (not visible in this view) present in the substrate 125 of the IC package 100a, conductor 116 is in a fixed position. As described above, the substrate 125 supports... Figure 1 The electrical connection between the first-stage IC die A106 and the two second-stage IC dies B104a and C104b is shown.

[0053] like Figure 1 As shown, conductor 116 is coupled to pin 316 present in PCB 114. Pin 316 and conductor 116 form a ball grid array (BGA). Within the BGA, a moat 205 may be formed. Moat 205 is an area that typically does not contain any conductor 116. Moat 205 is optional and may or may not be used depending on the type and application of IC die A 106, IC die B 104a, and IC die C 104b.

[0054] Conductors 116 are typically arranged in a predetermined manner to maximize their number. These conductors 116 can be placed on the bottom side of the IC package 100a and will be appropriately coupled to conductors of the substrate 125 within the IC package 100a and to pins of the PCB 114. The conductors 116 are typically positioned relative to each other based on the size of each conductor and on the surface area of ​​the bottom side of the IC package 100a.

[0055] Exemplary dimensions in Figure 3 The figures are shown in the diagram. This disclosure is not limited to the dimensions shown. As will be understood by those skilled in the art, smaller and larger dimensions are also within the scope of this disclosure.

[0056] According to the illustrated exemplary embodiment, each conductor 116 may include a diameter between about 0.035 mm and 0.035 mm, and specifically about 0.20 mm. However, other sizes are also possible and are included within the scope of this disclosure.

[0057] Conductors 116 are arranged in rows and columns along the bottom surface of IC package 100a. Each column of conductors 116 (see the letter markings AK-A on the top of IC package 100a) is offset relative to another column based on the diagonal distance Dc1 between conductors 116. Similarly, each row of conductors 116 (see the number markings 1-37 on one side of IC package 100a) is offset relative to another column based on the diagonal distance Dc1 between conductors 116. The diagonal distance Dc1 may have an exemplary size of approximately 0.35 mm.

[0058] Meanwhile, the distance Dc2 between conductors 116 in the same row and column can include an exemplary size of 0.496 mm. Typically, the size Dc2 will be larger than the distance Dc1.

[0059] An exemplary length dimension Lc1 between conductor 116 at position (36, AK) and conductor 116 at position (2, AK) may include an exemplary size of approximately 8.432 mm. Figure 3 In the exemplary embodiment shown, seventeen conductors 116 can span along the length dimension Lc1.

[0060] An exemplary width dimension Wc1 between conductor 16 at position (36, AK) and conductor at position (36, B) may include an exemplary size of approximately 6.944 mm. Figure 3 In the exemplary embodiment shown, fourteen conductors 116 can span along the width dimension Wc1.

[0061] An exemplary width dimension WccL between the conductor 116 at position (1, R) and the vertical geometric center line (cL) may include an exemplary size of approximately 0.124 mm. Meanwhile, an exemplary width dimension Wpe between the conductor 116 at position (1, A) and the package edge (pe) may include an exemplary size of approximately 0.304 mm.

[0062] Furthermore, the exemplary length dimension Lpe between the conductor and the package edge (pe) at location (1, A) may include an exemplary size of approximately 0.336 mm. The exemplary length dimension LccL between the conductor and the horizontal geometric center line (cL) at location (1, A) may include an exemplary size of approximately 4.464 mm.

[0063] An exemplary length dimension Lc2 between the conductor at position (37, A) and the conductor at position (1, A) may include an exemplary size of approximately 8.928 mm. In the exemplary embodiment shown, eighteen conductors 116 may span along this length dimension Lc2.

[0064] As mentioned above, Figure 3 These dimensions (and all parts of this disclosure) are given by way of example only. Other sizes larger or smaller than these dimensions are possible and are included within the scope of this disclosure.

[0065] Now for reference Figure 4 The image is Figure 5 The diagram shows a cross-sectional view of the assembly having components 106, 303a-303c, and 114. That is to say, Figure 4 The diagram also shows cross-sectional views of PCB 114, substrate 124, CE1 303a, CE2 303b and SoC D 106.

[0066] Within IC package 100a, such as Figure 4 As shown within the dashed line, there exists a first circuit element (CE1) 303a. The second circuit element (CE2) 303b and the third circuit element (CE3) 303c are... Figure 4 Invisible in the middle, but in Figure 5 As can be seen, CE1 303a, CE2 303b, and CE3 303c occupy the same area as... Figure 5 The same geometric planes are visible in the image. The IC package 100a is coupled to the top surface 115 of the printed circuit board (PCB) 114. (See image) Figure 4 As shown, the first circuit element (CE1) 303a is part of the substrate 125 and may have a portion of the BGA for the substrate 125.

[0067] Now for reference Figure 5 The image is from Figure 4 and Figure 1 The illustrated view is of the top surface 115 of the PCB (corresponding to...). Figure 4 The advantageous position 401 in the diagram illustrates an exemplary pin diagram 505 (with rows A-AK and columns 1-37). This pin diagram 505 directly corresponds to the one described above. Figure 3 The ball grid array shown.

[0068] Dashed section line 4-4 exists Figure 5 In the middle. The cross-sectional line 4-4 corresponds to... Figure 4 The cross-sectional view of IC package 100a shown.

[0069] Figure 5 The pin diagram 505 includes a square element 119 that can represent pin 316. However, other shapes besides square may be used in the pin diagram without departing from this disclosure. For example, a circular element or a circle may be used in the pin diagram instead of the square element 119 without departing from this disclosure.

[0070] like Figure 5As shown in this view, the IC package 100b has the following features: Figure 4 The first circuit element (CE1) 303a, the second circuit element (CE2) 303b, and the third circuit element (CE3) 303b shown (in) Figure 4 (Not visible in the cross-sectional view). Each circuit element (CE) 303 may include, but is not limited to, circuit traces or data paths, conductors, processing entities, including but not limited to another SoC, processing circuitry (i.e., RF ICs, such as modems, baseband ICs), memory circuitry, or any combination thereof.

[0071] according to Figure 5 In one exemplary embodiment illustrated, CE1-3 303 may include one or more interface circuits coupling the modem die 106 to the intermediate frequency (IF) integrated circuit (IC) 1077, as follows: Figure 12 and Figure 13 The three circuit elements (CEs1-3) are interconnected on / within substrate 125 (see above). Figure 1 Connected to the die uplinks (die uplinks 1-3), substrate 125 is located within package 100a and is part of SoC die 106. These interconnects (not shown) within substrate 125 are structurally similar to Figure 6 The circuit trace 602 of PCB 114 shown and described below.

[0072] The top portion 505 of the pin diagram is highlighted with a dashed line. The top portion 505 of the pin diagram corresponding to the three circuit elements (CE1-3) 303a-303c is the focus of this disclosure. Specifically, the polarity of pin 316, represented by the square pin diagram unit 119 within this top portion 505 of the pin diagram, is the focus of this disclosure. This top portion 505 of the pin diagram has at least two boundary regions: the SoC die edge 525 and the IC package edge 520.

[0073] However, it should be noted that edge 525 of the SoC die can overlap with circuit element CE1-3. Furthermore, the two boundary regions defined by edges 520 and 525 are not fixed. That is, the pin polarity pattern 505 corresponding to pin diagram and pin 316 (see...) Figure 7A , Figure 8 and Figure 9 It can be expanded beyond or contracted to fit the die package 100a and PCB 114 according to the size required for a specific application.

[0074] Now for reference Figure 6 The diagram illustrates the breakout routing of circuit trace 602 on PCB 114, which corresponds to a path similar to... Figure 5The pinout section of the 505 is similar to the pinout section of the 505. Figure 5 The outline of pin 505, indicated by dashed lines, has been placed around PCB 114 to demonstrate... Figure 5 Each square cell in the pin diagram portion 505 corresponds to the end / pin 316 of the circuit trace 602 on and / or within the PCB 114. Note that... Figure 6 The branch wiring of circuit trace 602 may or may not directly correspond to the above combination. Figure 5 The pin diagram section 505 is described.

[0075] At the end of circuit trace 602 is pin 316, similar to that described above. Figure 1 The pin 316 shown in the diagram corresponds to this. Circuit trace 602 can form signal line 602, which is coupled to... Figure 6 The circuit element CE1-3 (303a-303c) is shown by the dashed line at the top and is related to... Figure 5 This corresponds to CEs1-3 (303a-303c) shown.

[0076] exist Figure 6 In the exemplary embodiment shown, three sets of circuit traces / signal lines are present on PCB 114. The first set 1 can be coupled to the first circuit element (CE1-303a) via substrate 125 (see Figure 4 Similarly, the second group 2 can be made through substrate 125 (see...). Figure 4 The third group (group 3) can be coupled to the second circuit element (CE2-303b) through the substrate 125 (see...). Figure 4 Coupled with the third circuit element (CE3-303c), such as Figure 6 The three dashed arrows in the upper part are shown in the diagram.

[0077] The system of the present invention is not limited to the three circuit elements CE1-3 (303a-303c) illustrated. Without departing from this disclosure, fewer or additional sets of circuit traces / signal lines 602 may be provided to support fewer or more circuit elements (CE).

[0078] Signal line 602 can support data signals, clock signals, etc. For example, if signal line 602 supports communication between modem die 106 and RF intermediate frequency (IF) integrated circuit (IC) 1077 (see...) Figures 12-13 Signal line 602 can support uplink and downlink signals associated with modem 106, as well as clock signals as understood by those skilled in the art.

[0079] Typically, signal lines 602 are formed in signal pairs: the first signal line can have a positive (+) polarity, while the second signal line can have a negative (-) polarity. For example, the first signal line pair 602a1 and 602b1 can have a first signal line 602a1. The first signal line 602a1 can have a positive (+) polarity, while the second signal line 602b1 can have a negative (-) polarity. One end of the first signal line 602a1 can have a positive polarity pin [P(+)] 316. The end of the second signal line 602b1 can have a negative polarity pin [P(-)] 316.

[0080] Similarly, the second signal line pair 602a2, 602b2 can have a first signal line 602a2. The first signal line 602a2 can have a positive (+) polarity, while the second signal line 602b2 can have a negative (-) polarity. The end of the first signal line 602a2 can have a positive polarity pin [P(+)]316. The end of the second signal line 602b2 can have a negative polarity pin [P(-)]316.

[0081] These signal lines 602 can be coupled to circuit elements (CE1-3) (303a-303c), in Figure 6 The top of the page is illustrated with dashed lines. These signal lines 602 can be accessed via pin 316. Figures 1-5 The ball grid array (BGA) shown is coupled to die 106 and PEs1-3 (303a-303c) (see...) Figure 5 Some pins 316 may not have any signal lines 602 and may include electrical ground (G) relative to PCB 114, circuit elements (CE), and dies 102, 104. If the space in the pin diagram is not electrically marked, it may include blank space / planar portion of the printed circuit board (PCB). In an alternative embodiment, the space in the pin diagram without electrical markings may include a pin, but the pin may not be connected to anything / not connected to any circuit element and may be characterized as floating relative to the aforementioned electrical markings.

[0082] PCB 114 may include multiple channels L. For example, see channel L1, which is defined by two pins P1(+) and P1(-) of opposite polarity and corresponds to two signal lines / traces spanning PCB 114. See channel L2, defined by two pins P(+) and P(-) and signal line pairs 602a2 and 602b2.

[0083] Now for reference Figure 7A The diagram illustrates something similar to Figure 5 The first exemplary embodiment of pin diagram 505A for ball grid array (BGA) coupling is shown in pin diagram 505. As described above in conjunction with... Figure 6As described, each pin 316 of pin diagram 505 can be coupled to one end of a circuit trace / signal line 602 on / within PCB 114. Each pin 316 may include at least one of a positive polarity pin [P(+)], a negative polarity pin [P(-)], and a ground pin [G]. Furthermore, blank or unmarked portions of pin diagram 505 refer to empty / blank areas of PCB 114 that contain neither pins 316 nor traces / signal lines 602. In other words, empty or blank squares / cells of pin diagram 505 mean that the area includes substrate material and contains no pins 316, conductors, or circuit traces / signal lines 602.

[0084] Typically, signal line 602 and pin 316 (see...) Figure 6 This will form signal line pairs with opposite polarities. That is, for each pair of pins 316, the pair will include a positive polarity pin [P(+)] and a negative polarity pin [P(-)], where the pair will occupy a diagonally opposite square in pin diagram 505. In other words, each pin with polarity will occupy a space offset by forty-five degrees relative to the mating pin in the pin pair. And note that the polarity of the pins in any given pin pair can be swapped / reversed.

[0085] Meanwhile, ground pin G is typically not paired with other ground pin G. Ground pin G does not need to be offset by a 45-degree angle relative to another ground pin G. Although, depending on a specific pin polarity pattern, ground pins G may be offset by 45 degrees, they are generally not required to be in that orientation. Furthermore, ground pin G can be positioned within pin diagram 505 without pairing with another ground pin G.

[0086] Similar to Figure 6 The branching routing of signal line 602 shown in the figure, pin diagram 505A can support communication with three CE1-3 (303a-303b). However, fewer or more CE1-3 (303a-303b) can be coupled based on pin diagram 505 and included within the scope of this disclosure.

[0087] Pin diagram 505A may include repeating pin polarity patterns 555A1-A4. When a region comprising four pin areas by four pins is selected, this first repeating pin polarity pattern 555 may have a substantially square shape. This first repeating pin polarity pattern 555 will be referred to as a channel cell block. Pin diagram 505A has two types of channel cell blocks 555: SoC die edge type (lower) 555A1-A2 and package edge type (upper) 555A3-A4.

[0088] For the SoC die edge type of channel cell blocks 555A1-555A2, the bottom row of the 4×4 cell square includes the pin diagram cell below the SoC die edge 520. Furthermore, the SoC die edge type of channel cell blocks 555A1-555A2 may have at least four ground pins (G), which exist in twelve external locations (squares) relative to four internal locations (squares) including channel or signal pairs [P(+), P(-)].

[0089] Meanwhile, for the package edge type of channel cell blocks 555A3-555A4, the top row of the 4×4 cell square includes the pin diagram cell above the IC package edge 525. Furthermore, the package edge type of channel cell blocks 555A3-555A4 can have up to six ground pins (G), which exist in twelve external positions (squares) relative to the four internal positions (squares) including channel or signal pairs [P(+), P(-)].

[0090] Note that not all channel cell blocks 555 are in Figure 7A All of these are highlighted. As described above, the channel unit block 555 is first identified by its opposite polarity channel or signal pair pins P(+), P(-), and then the block includes a four-by-four square pin diagram unit relative to the two-by-two square unit inside the signal pair or channel L.

[0091] Now for reference Figure 7B The diagram illustrates Figure 7A The image shows an enlarged view of the first square channel unit block / repeating pin polarity pattern 555A1. According to this square channel unit block / repeating pin polarity pattern 555A1, the four innermost square units with an area of ​​2x2 pins can include pin pairs of opposite polarities P(+) and P(-), forming a channel L positioned at a 45-degree angle. Specifically, the positive pin P(+) can occupy positions R4 and C8 of the four inner squares, while the negative pin P(-) can occupy positions R5 and C9 of the four inner squares.

[0092] Relative to the twelve outer squares [R3, C7-C8; R4, C7 & C10; R5, C7 & C10; and R6, C7-C10] outside the four-by-four square repeating pin polarity pattern (channel cell block) 555A1, the pattern may include ground pins G located at positions [R3, C7]; [R3, C9]; [R4, C10]; and [R5, C7]. Although not in Figure 7A and Figure 7BAs shown, the sixth row (R6) can include two additional ground pins G, so that the channel or signal pair [P(+), P(-)] can be surrounded by a total of six ground pins G. Meanwhile, the remaining twelve outer squares can include, relative to... Figure 7A The empty / blank areas of these four ground pins G shown in the square channel cell pattern 555A1.

[0093] As mentioned above, the channel cell block 555A1 and the second block 555A2 are SoC die types because their lower rows, here being the 6th row of block 555A1, include, for example... Figure 7A The pinout cells shown are below edge 520 of the SoC die. Meanwhile, the other two channel cell blocks 555A3 and 555A4 are IC package edge types because their top row includes cells above IC package edge 525.

[0094] Now for reference Figure 8 The diagram illustrates something similar to Figure 5 and Figures 7A-7B The second exemplary embodiment of pin diagram 505A for ball grid array (BGA) coupling is shown in pin diagram 505. Figure 8 Basically similar Figure 7A .

[0095] Figure 8 The four channel unit blocks 555B1-555B4 are highlighted. Similar to... Figure 7A The channel unit block 555A described in the document consists of two channel unit blocks, 555B1-B2, which are SoC die channel unit blocks (lower type), and two channel unit blocks, 555B3-555B4, which are IC package edge type (upper type). Figure 7A and Figure 8 The main difference between the channel unit blocks 555 is that Figure 8 The polarity of the signal at pin 316 in row R4 / R5 is shifted one column to the right, while Figure 8 The polarity of the signal at pin 316 at row R1 / R2 is related to... Figure 7A Keep it the same.

[0096] See now Figure 9 The figure shows Figure 8 The enlarged view of the 555B1 square repeating channel cell block / pin polarity pattern is highlighted in the image. Figure 9 and Figure 8They are essentially similar. Therefore, only the differences between the two diagrams will be described below. According to this square repeating channel cell block / pin polarity pattern 555B, the four innermost squares with an area of ​​two by two pins can further define the channel cell, which includes pin pairs of opposite polarities P(+), P(-) positioned at a 45-degree angle.

[0097] Specifically, Figure 9 The positive terminal P(+) can occupy positions R5 and C31 of the four internal squares, while the negative terminal P(-) can occupy positions R4 and C30 of the four internal squares. This exemplary embodiment is used for Figure 9 The square repeating pin polarity pattern 555B1 and the four innermost squares of the pattern 555. Figure 7B The exemplary embodiment is exactly the opposite. In other words, within the channel unit block 555, the polarity of the signal pair [P(-), P(+)] can be exchanged / switched.

[0098] Furthermore, in some exemplary embodiments (not shown), Figure 9 The sixth row, R6, may include an additional ground pin G or a power supply pin (V) (see [reference]). Figure 10 Specifically, row R6, columns C16, C22, and C26. Like the ground pin G, the power supply pins (V) typically do not support any communication or data signals, and therefore, the power supply pins (V) are usually not placed in pairs.

[0099] See back Figure 8 , Figure 8 The lower two channel cell blocks 555B1 and 555B2 may include a SoC die edge type pattern, wherein their respective bottom rows are below the SoC die edge 520, similar to... Figure 7A The first two channel cell blocks are 555A1 and 555A2. The upper dual-channel cell blocks 555B3 and 555B4 may include IC package edge-type patterns, where the top row of each of the blocks 555 is above the IC package edge 525, similar to... Figure 7A The second dual-channel unit blocks 555A3 and 555A4.

[0100] Now refer to Figure 10 The diagram illustrates a representation with... Figure 7A The pin diagram for the 505C shows the same pin polarity. However, Figure 10The repeating pin polarity patterns of circles 1005 and "X" 1010 are shown. That is, the repeating pin polarity pattern 1005, shaped like each circle, may include four ground (G) pins centered on the third row 3. Meanwhile, the repeating pin polarity pattern 1010, shaped like each "X", may include a ground pin G forming the "center" of each "X" shape, while the remaining pins along the diagonal of each line forming the "X" shape may include a positive pin [P(+)] and a negative pin [P(-)].

[0101] exist Figure 10 In the sixth row of the pinout diagram 505C, and specifically, according to an exemplary application, in the sixteenth column of the sixth row (R6, C6); in the twenty-second column of the sixth row (R6, C22); and in the twenty-sixth column of the sixth row (R6, C26), these three locations of the pinout diagram 505C may include a ground pin (G) or a power pin (V). Like the ground pin (G), the power pin (V) typically does not transmit any communication / data signals and therefore is not paired with other pins. Figure 10 The sixth row (R6) is below the 520 edge of the die.

[0102] Now for reference Figure 11 This figure illustrates a fourth exemplary embodiment of the pinout 505D for ball grid array (BGA) coupling, similar to... Figure 5 , Figure 7A and Figure 8 Pin diagrams 505A and 505B are shown. The basic channel unit block 555E still exists. Figure 11 In the middle. And Figure 7A and Figure 8 The difference is that the basic channel unit block 555E does not overlap with the other examples mentioned above.

[0103] because Figure 11 The channel cell blocks 555E do not overlap, so there is more physical separation between signal pairs / channels. The lack of overlap between the block patterns 555E determines the “sparseness” of the entire pin pattern of the pin diagram 505D. Figure 11 Pin diagram of 505D and Figure 7A , Figure 7B , Figure 8 , Figure 9 and Figure 10 Compared to the repeating pin pattern, it is characterized by having a sparser repeating pin polarity pattern.

[0104] exist Figure 11 In this exemplary embodiment, there are three ground pin (G) rows R3-R5 highlighted by rectangle 709. These ground pin (G) rows R3-R5 help to provide additional spacing.

[0105] Compared to other exemplary embodiments, this additional spacing and ground pin (G) allow the signal pair / channel to support higher frequency signals. This is achieved when the spacing between the pins is reduced (see [example example]). Figure 3 As shown in Dc1, Dc2), these additional ground pins (G) between the cell channel blocks 555E allow the signal pairs [P(+), P(-)] to maintain a greater distance.

[0106] Note that other repeating pin polarity patterns exist in Figure 7- Figure 11 In the pin diagram 505, however, for the sake of simplicity, this article only highlights some repeating patterns.

[0107] Performance implemented using exemplary pinout 505

[0108] The pinout system described above allows circuit traces or signal lines to be formed on a single layer or geometric plane of a PCB, provided that the design rules for PCB trace and via dimensions permit such geometry. In this way, a single PCB layer with well-mapped traces / signal lines is utilized, eliminating the need for multiple PCB layers to support communication between two dies and / or two integrated circuits or combinations thereof. Therefore, the pinout system enables PCB routing to be contained within a single signal layer, thereby maximizing the board routing space on the PCB.

[0109] The pin diagram system described above can reduce crosstalk between traces / signal lines within the PCB114. For example, the pin diagram can reduce crosstalk of RF communication signals propagating at a Nyquist frequency of approximately 9 GHz by approximately 5.0 to 10.0 dB. The pin diagram system can be expanded by adding more grounding markers (G) between the rows and columns of positive and negative polarity pins [P(+), P(-)]. The pin diagram system can be expanded to multi-channel counting, and it provides a simple and intuitive guide for PCB and electronic package routing.

[0110] The pinout system can be scaled for different electronic package pitch sizes, provided that the PCB trace and via design rules are scaled or meet the requirements of the aforementioned PCB fan-out strategy. Socket platforms use sockets to exchange components for batch system-level testing. Sockets between BGA and system-level test (SLT) platform PCBs typically have additional crosstalk margin when operating at the target frequency.

[0111] The pinout system described above increases the margin of the socket platform to meet design goals (especially at these high data rates), and system-level testing is not limited by the BGA / socket interface when testing system performance. On the system SLT platform, the pinout system facilitates mass production and quality control. The pinout system can be used with industry-standard interfaces such as PCIe and USB.

[0112] Pin diagram systems are particularly useful for low-voltage radio frequency communication applications, such as portable computing devices (PCDs), like mobile phones, which operate on batteries. For example, the voltage across a pin diagram system can range from 800.0mV. An 800.0mV signal can be corrupted by a 1.0V crosstalk signal, a very low threshold. PCDs can include, but are not limited to, mobile phones, personal digital assistants (PDAs), pagers, smartphones, navigation devices, and handheld computers with wireless connectivity or links, as described above. In addition to PCDs, pin diagram systems can also be used in laptops and desktop computers.

[0113] Now for reference Figure 12 The figure illustrates an exemplary embodiment of a PCD 1000, such as a mobile phone, which can be used between specific chips (such as modem 106 and radio frequency (RF) intermediate frequency (IF) integrated circuit (IC) 1077) as shown in Figure 7- Figure 11 The pinout is shown in Figure 505. The PCD 1000 includes the SoC 1002.

[0114] In the SoC 1002 embodiment, the SoC 1002 may include a CPU 1004, a GPU 1006, a DSP 1007, an analog signal processor 1008, or other processors. The CPU 1004 may include multiple cores, such as a first core 1004A, a second core 1004B, and so on, up to an Nth core 1004N.

[0115] Modem 106 can be coupled to analog signal processor 1008. Modem can also be coupled to RF-IF IC 1077 via PCB 114 (not shown), where PCB 114 provides mating surfaces for SoC 1002 and a second SoC B containing RF IC 1077. PCB 114 may include, for example... Figure 5 And Figure 7- Figure 11 The pin diagram 505 shown is for supporting ball grid array (BGA) coupling.

[0116] PCB 114 and its pinout 505 ( Figure 12 (Not visible in the image) can be part of a serializer / deserializer (SERDES) circuit that supports RF signals between modem 106 and RF-IF IC 1077. RF switch 1056 can be coupled to RF IF IC 1077 and RF antenna 1058.

[0117] In addition, the keypad 1060, the mono headset 1062 with a microphone, and the vibrator device 1064 can be coupled to the analog signal processor 1008.

[0118] Display controller 1010 and touchscreen controller 1012 can be coupled to CPU 1004. A touchscreen display 1014 external to SoC 1002 can be coupled to display controller 1010 and touchscreen controller 1012. PCD 1000 may also include a video decoder 1016 coupled to CPU 1004. Video amplifier 1018 can be coupled to video decoder 1016 and touchscreen display 1014. Video port 1020 can be coupled to video amplifier 1018. Universal Serial Bus (“USB”) controller 1022 can also be coupled to CPU 1004, and USB port 1024 can be coupled to USB controller 1022. Subscriber Identity Module (“SIM”) card 1026 can also be coupled to CPU 1004.

[0119] One or more memories 1028, 1031 may be coupled to CPU 1004. The one or more memories may include volatile and non-volatile memories. Examples of volatile memories include static random access memory (“SRAM”) 1028 and dynamic RAM (“DRAM”) 1030 and 1031. Such memories may be external to SoC 1002, such as DRAM 1030, or internal to SoC 1002, such as DRAM 1031. A DRAM controller 1032 coupled to CPU 1004 may control the writing of data to and from DRAM 1030 and DRAM 1031. In other embodiments, such a DRAM controller may be included within a processor such as CPU 1004. CPU 1004 may execute HLOS or other software stored in any of the aforementioned memories.

[0120] A stereo audio CODEC 1034 can be coupled to an analog signal processor 1008. Additionally, an audio amplifier 1036 can be coupled to the stereo audio CODEC 1034. First stereo speakers and second stereo speakers 1038 and 1040 can be coupled to the audio amplifier 1036, respectively. Furthermore, a microphone amplifier 1042 can be coupled to the stereo audio CODEC 1034, and a microphone 1044 can be coupled to the microphone amplifier 1042. A frequency modulation (“FM”) radio tuner 1046 can be coupled to the stereo audio CODEC 1034. An FM antenna 1048 can be coupled to the FM radio tuner 1046. Additionally, stereo headphones 1050 can be coupled to the stereo audio CODEC 1034. Other devices that can be coupled to the CPU 1004 include one or more digital (e.g., CCD or CMOS) cameras 1052.

[0121] Power supply 1066 may be coupled to SoC 1002 via power management integrated circuit (“PMIC”) 1068. Power supply 1066 may include a rechargeable battery or DC power derived from an AC-DC transformer connected to an AC power source.

[0122] The SoC 1002 may have one or more internal or on-chip thermal sensors 1070A and may be coupled to one or more external or off-chip thermal sensors 1070B. The analog-to-digital converter (“ADC”) controller 1072 may convert the voltage drop generated by the thermal sensors 1070A and 1070B into a digital signal.

[0123] As shown in this exemplary embodiment of PCD 1000, the touchscreen display 1014, video port 1020, USB port 1024, camera 1052, first stereo speaker 1038, second stereo speaker 1040, microphone 1044, FM antenna 1048, stereo headphones 1050, RF switch 1056, RF antenna 1058, keypad 1060, mono headset 1062, vibrator 1064, thermal sensor 1050B, ADC controller 1052, PMIC 1068, power supply 1066, DRAM 1030, and SIM card 1026 are external to SoC 1002. However, it should be understood that in other embodiments, one or more of these devices may be included within the SoC.

[0124] Now for reference Figure 13 This figure is a functional block diagram illustrating a possible physical layout 1300 of a modem SoC die 106 and an RFIFIC 1077 SoC. According to this exemplary embodiment, a first SoC A 1002 may include the modem SoC 106 and the previously described processing entities (PE1-3). The first SoC A package 1002 may be coupled to a PCB 114 using a BGA and a first pinout 505'.

[0125] Simultaneously, the second SoC B, which includes an RF IF IC 1077 with an RF transceiver 1087, can also be coupled to PCB 114 using a BGA and a second pinout 505”. PCB 114 has circuit traces / signal lines that provide electrical connections between the modem die 106, PE1-3 located in the first SoC A, and the RF transceiver die 1087 located in the second SoC B 1077. The first and second pinouts 505”, 505” can be identical to each other, or they can be different, depending on the type of circuit elements 106, 1077 coupled to each other.

[0126] As previously stated, pinout 505 allows multiple circuit elements 106, 1077 to be coupled together using a single layer of printed circuit board 114, which has circuit traces 602 (not shown on the printed circuit board 114). Figure 14 As shown in the text, but see also Figure 6 Meanwhile, conventional solutions for coupling multiple circuit elements may require multiple layers or more of printed circuit boards 114 to couple the circuit elements together.

[0127] Now for reference Figure 14 This figure is a logic flowchart illustrating an exemplary method 1400 for planning the connection locations between integrated circuit (IC) packages or circuit elements coupled together using layers of a printed circuit board (PCB) 114. Block 1405 is the first block of method 1400.

[0128] In box 1405, select the first circuit element 1002 having the first ball grid array (see...). Figure 13 This is used to couple to a layer of the printed circuit board 114. Next, in decision box 1410, the conductor 116 of the ball grid array (BGA) is determined (see...). Figure 3 Is the spacing between them narrow? As mentioned earlier, combined with... Figure 3 The BGA conductors 116 are arranged in rows and columns along the bottom surface of the IC package 100a. Each column of conductors 116 (see the letter markings AK-A on the top of the IC package 100a) is offset relative to another column based on the diagonal distance Dc1 between the conductors 116. Similarly, each row of conductors 116 (see the number markings 1-37 on the IC package 100a) is offset relative to another column based on the diagonal distance Dc1 between the conductors 116. The diagonal distance Dc1 may have an exemplary size of approximately 0.35 mm.

[0129] Meanwhile, the distance Dc2 between conductors 116 in the same row and column can include an exemplary size of 0.496 mm. Typically, the size Dc2 will be larger than the distance Dc1. If the distance Dc1 or Dc2 is smaller than these sizes (i.e., Dc1 < 0.35 mm or Dc2 < 0.496 mm), the spacing may be referred to as "narrow". Other sizes of Dc1 and Dc2 are also possible and are included within the scope of this disclosure.

[0130] Therefore, if the query for decision box 1410 is “narrow”, then the “yes” branch follows to box 1415. If the query for decision box 1410 is not narrow, meaning that the diagonal distances Dc1 and Dc2 are greater than or equal to those described in box 1405, then the “no” branch follows to box 1415.

[0131] In box 1415, select the first pin diagram 505D with a sparser repeating pin polarity pattern (see [link]). Figure 11 The repeating pin polarity pattern includes an increased number of ground pin rows (i.e., see [link]). Figure 11 (R3-R5 rows) and / or non-overlapping channel cell blocks 555E1-551E4 ( Figure 11 The pinout of box 1415 typically corresponds to... Figure 11 The exemplary embodiments shown are illustrated above. Figure 11 As mentioned, due to Figure 11 The channel unit block 555E does not overlap with, and Figure 7A , Figure 8 , Figure 9 and Figure 10 Compared to those shown, there is more physical separation between signal pairs / channels. The lack of overlap between block patterns 555E determines the “sparseness” of the entire pin pattern of pin diagram 505D. Figure 11 Pin diagram of 505D and Figure 7A , Figure 7B , Figure 8 , Figure 9 and Figure 10 Compared to the repeating pin pattern, it is characterized by a sparser repeating pin polarity pattern. Figure 11 In an exemplary embodiment, there are three rows of ground pins (G) R3-R5, highlighted by rectangle 709. These rows of ground pins (G) R3-R5 help provide additional spacing between signal pairs / channels. Compared to other exemplary embodiments, this additional spacing and ground pins (G) allow signal pairs / channels to support higher frequency signals.

[0132] As described above, if the query for decision box 1405 is negative, meaning the BGA pitch is not narrow or the BGA has an average pitch, then the "No" branch continues to box 1420. Box 1420 features a denser repeating pin polarity pattern (with...). Figure 11 The first pin diagram (compared to the first) includes overlapping channel cell blocks, for example, selectable Figure 7A , Figure 8 and Figure 10 The overlapping channel unit blocks shown are, in other words, selectable in box 1420. Figure 7A Pin diagram 505A with overlapping channel unit blocks 555A1-A2, 555A3-A4 or pin diagram 505B with overlapping channel unit blocks 555B1-B2, 555B3-B4 or Figure 10 The pin diagram 505C has repeating pin polarity patterns 1005 and 1010.

[0133] The first pin diagram selected from box 1415 or 1420 can correspond to Figure 14 The first pin of the first circuit element 1002 is shown in Figure 505'.

[0134] Next, in box 1425, select the second circuit element 1077 having the second ball grid array (BGA) (see...). Figure 13 This is used for coupling to a layer of printed circuit board 114. The frame 1425 and subsequent frames 1430 to 1440 are identical to frames 1410-1420 (spacing 1410, sparse repeating pin polarity pattern 1415, dense repeating pin polarity pattern 1420). These frames 1430 to 1440 are used for... Figure 13 The second circuit element 1077 is the second BGA. Once the second pinout for the second BGA is determined based on box 1435 or box 1440, the next step is to identify circuit trace 602 on PCB 114 in box 1445 (see...). Figure 6 The first pin diagram 505' (see...) Figure 13 The pins of the second pin are shown in Figure 505. Figure 13 The pin connection location.

[0135] And in block 1450, pins are then placed on a single layer of a printed circuit board 114 according to the first pin diagram and the second pin diagrams 505', 505'". Next, in block 1455, circuit traces are placed on the single layer of the printed circuit board 114 according to the positions marked in block 1445, such that the pins and circuit traces of the single layer of the printed circuit board 114 are aligned with the first circuit element 1002 (see...). Figure 13 ) and second circuit element 1077 (see Figure 13 An electrical connection is established between the channels / circuit traces 602, thereby significantly reducing any potential crosstalk and / or interference between them. Method 1400 can then be repeated for the next circuit element to be coupled to the first circuit element 1002 and / or the second circuit element 1077, both of which are located on the same PCB 114.

[0136] Alternative exemplary embodiments will become apparent to those skilled in the art to which this disclosure pertains without departing from its scope. For example, in addition to mobile phone applications, other applications of the pin diagram system of the present invention include using the system of the present invention to attach PCB cards or to solder modules to larger motherboards in systems such as laptops, Internet of Things (IoT), and other similar telematics hardware / electronic package arrangements.

[0137] Implementation examples are described in the following numbered clauses:

[0138] 1. An apparatus comprising: a first semiconductor die, stacked vertically relative to layers of a printed circuit board (PCB), the first semiconductor die being coupled to the PCB via a ball grid array (BGA); a second semiconductor die, stacked vertically relative to layers of the PCB, the second semiconductor die being coupled to the PCB via a BGA; a pin map corresponding to each BGA and covering a surface area of ​​the PCB, the pin map including a plurality of electrical markings for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical markings on the pin map including one of positive polarity (P+), negative polarity (P-), or electrical ground (G); each pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern including a channel cell block having a central region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

[0139] 2. The apparatus according to Clause 1, wherein the pin diagram comprises a plurality of square cells, wherein each square cell represents an electrical mark or blank space of a pin.

[0140] 3. The apparatus according to any one of clauses 1-2, wherein the channel unit block has a positive polarity (P+) pin and a negative polarity (P-) pin, and the remaining two sub-regions of the central region include two blank spaces of the pin diagram.

[0141] 4. The apparatus according to any one of clauses 1-3, wherein the channel unit blocks overlap each other along the length dimension of the pin diagram.

[0142] 5. The apparatus according to any one of clauses 1-3, wherein the channel unit blocks do not overlap each other along the length dimension of the pin diagram.

[0143] 6. The device according to any one of clauses 1-5, wherein the pin diagram includes two boundaries: a first boundary and a second boundary, the first boundary corresponding to a first boundary of an edge of an integrated circuit (IC) package, and the second boundary corresponding to a second boundary of a die edge.

[0144] 7. The apparatus according to any one of clauses 1-6, wherein the semiconductor die includes at least one of: an integrated circuit (IC), a system-on-a-chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and memory circuitry, or a combination thereof.

[0145] 8. The apparatus according to Clause 7, wherein the PCB supports radio frequency (RF) communication.

[0146] 9. The apparatus according to Clause 8, wherein the PCB is contained within a portable computing device, the portable computing device including at least one of: a mobile phone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer having a wireless connection or link.

[0147] 10. An apparatus comprising: a pin map, a surface region corresponding to a ball grid array and covering a layer of a printed circuit board (PCB), the pin map including a plurality of electrical marks for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical marks including one of positive polarity (P+), negative polarity (P-), or electrical ground (G); and the pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern including a channel cell block having a central region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

[0148] 11. The apparatus according to Clause 10 further includes a semiconductor die stacked vertically relative to the PCB, the die being coupled to the PCB via the ball grid array (BGA).

[0149] 12. The apparatus according to any one of clauses 10-11, wherein the pin diagram comprises a plurality of square cells, wherein each square cell represents an electrical mark or blank space of a pin.

[0150] 13. The apparatus according to any one of clauses 10-12, wherein the channel unit block has a positive polarity (P+) pin and a negative polarity (P-) pin, and the remaining two sub-regions of the central region include two blank spaces of the pin diagram.

[0151] 14. The apparatus according to any one of clauses 10-13, wherein the channel unit blocks overlap each other along the length dimension of the pin diagram.

[0152] 15. The apparatus according to any one of clauses 10-13, wherein the channel unit blocks do not overlap each other along the length dimension of the pin diagram.

[0153] 16. The device according to any one of clauses 10-15, wherein the pin diagram includes two boundaries: a first boundary and a second boundary, the first boundary corresponding to an edge of an IC package and the second boundary corresponding to an edge of a die.

[0154] 17. The apparatus according to Clause 11, wherein the semiconductor die comprises at least one of the following: an integrated circuit (IC), a system-on-a-chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and memory circuitry, or a combination thereof.

[0155] 18. The apparatus according to any one of clauses 10-17, wherein the PCB supports radio frequency (RF) communication.

[0156] 19. The apparatus according to Clause 17, wherein the PCB is contained within a portable computing device, the portable computing device including at least one of: a mobile phone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer having a wireless connection or link.

[0157] 20. The apparatus according to Clause 18, wherein the PCB is included within a portable computing device, the portable computing device including at least one of: a mobile phone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer having a wireless connection or link.

[0158] 21. An apparatus comprising: an integrated circuit component vertically stacked relative to layers of a printed circuit board (PCB) for propagating high-speed communication signals, the integrated circuit component being coupled to the PCB via a ball grid array (BGA); a pin map corresponding to the BGA and covering a surface area of ​​the PCB, the pin map including a plurality of electrical marks for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical marks including one of positive polarity (P+), negative polarity (P-), or electrical ground (G); the pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern including a channel cell block having a central region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

[0159] 22. The apparatus according to Clause 21, wherein the integrated circuit component includes semiconductor dies stacked vertically relative to the PCB.

[0160] 23. The apparatus according to any one of clauses 21-22, wherein the pin diagram comprises a plurality of square cells, wherein each square cell represents an electrical mark or blank space of a pin.

[0161] 24. The apparatus according to any one of clauses 21-23, wherein the channel unit block has a positive polarity (P+) pin and a negative polarity (P-) pin, and the remaining two sub-regions of the central region include two blank spaces of the pin diagram.

[0162] 25. The apparatus according to any one of clauses 21-24, wherein the channel unit blocks overlap each other along the length dimension of the pin diagram.

[0163] 26. The apparatus according to any one of clauses 21-24, wherein the channel unit blocks do not overlap each other along the length dimension of the pin diagram.

[0164] 27. The device according to any one of clauses 21-26, wherein the pin diagram includes two boundaries: a first boundary and a second boundary, the first boundary corresponding to an edge of an IC package and the second boundary corresponding to an edge of a die.

[0165] 28. The apparatus according to Clause 22, wherein each semiconductor die includes at least one of the following: an integrated circuit (IC), a system-on-a-chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and memory circuitry, or a combination thereof.

[0166] 29. An apparatus according to any one of clauses 21-28, wherein the PCB supports radio frequency (RF) communication.

[0167] 30. The apparatus pursuant to Clauses 21-29, wherein the PCB is included within a portable computing device, the portable computing device comprising at least one of: a mobile phone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer having a wireless connection or link.

[0168] 31. A method comprising: selecting a first circuit element having a first ball grid array; determining whether the first ball grid array includes a narrow pitch; if the first ball grid array includes a narrow pitch, selecting a first pin pattern having a sparse repeating pin polarity pin pattern; selecting a second circuit element having a second ball grid array; determining whether the second ball grid array includes a narrow pitch; if the second ball grid array includes a narrow pitch, selecting a second pin pattern having a sparse repeating pin polarity pin pattern; identifying locations on a layer of a printed circuit board, wherein circuit traces connect pins of the first pin pattern to pins of the second pin pattern; placing pins on a layer of the printed circuit board according to the selected first and second pin patterns; placing circuit traces on a layer of the printed circuit board according to the identified locations, such that the pins and circuit traces on the printed circuit board layer establish an electrical connection between the first circuit element and the second circuit element, thereby significantly reducing crosstalk between circuit traces on a layer of the printed circuit board.

[0169] 32. The method according to Clause 31 further includes: if the first ball grid array includes a wide pitch, selecting a first pin pattern having a densely repeating pin polarity pattern.

[0170] 33. The method according to Clause 31 further includes: if the second ball grid array includes a wide pitch, selecting a second pin pattern having a densely repeating pin polarity pattern.

[0171] 34. The method according to Clause 31, wherein the first pin diagram and the second pin diagram comprise non-overlapping channel cell blocks.

[0172] 35. The method according to clause 31 or 34, wherein the first pin diagram and the second pin diagram include rows of ground pins positioned adjacent to each other.

[0173] 36. The method according to clause 31 or 32, wherein the first pin diagram includes overlapping channel cell blocks.

[0174] 37. The method according to Clause 33, wherein the second pin diagram includes overlapping channel cell blocks.

[0175] 38. The method according to clause 34 or 36, wherein each channel unit block has a positive polarity (P+) pin and a negative polarity (P-) pin, and the remaining two sub-regions of the central region include two blank spaces of the pin diagram.

[0176] 39. The method according to clauses 31-38, wherein each circuit element comprises at least one of the following: an integrated circuit (IC), a system-on-a-chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and memory circuitry, or a combination thereof.

[0177] 40. The method according to clauses 31-39, wherein the printed circuit board layer is included in a portable computing device, the portable computing device including at least one of: a mobile phone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer having a wireless connection or link.

[0178] Therefore, although the selected aspects have been described and detailed, it should be understood that various substitutions and changes may be made therein without departing from the scope of this disclosure, as defined in the appended claims.

Claims

1. An apparatus comprising: a first semiconductor die vertically stacked with respect to layers of a printed circuit board (PCB), the first semiconductor die coupled to the PCB with a ball grid array (BGA); a second semiconductor die vertically stacked with respect to the layers of the PCB, the second semiconductor die coupled to the PCB with a BGA; a pin map corresponding to each BGA and covering a surface area of the PCB, the pin map including a plurality of electrical designations for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical designations on the pin map including one of a positive polarity (P+), a negative polarity (P-), or electrical ground (G); each pin map including a first repeating pin polarity pattern; the first repeating pin polarity pattern including a channel cell block having a center region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

2. The apparatus of claim 1, wherein the pin map includes a plurality of square cells, wherein each square cell represents the electrical designation or a blank space of a pin.

3. The apparatus of claim 1, wherein the channel cell block has one positive polarity (P+) pin and one negative polarity (P-) pin, and the remaining two sub-regions of the center region include two blank spaces of the pin map.

4. The apparatus of claim 3, wherein the channel cell blocks overlap each other along a length dimension of the pin map.

5. The apparatus of claim 3, wherein the channel cell blocks do not overlap each other along a length dimension of the pin map.

6. The apparatus of claim 1, wherein the pin map includes two boundaries: a first boundary corresponding to an integrated circuit (IC) package edge and a second boundary corresponding to a die edge.

7. The apparatus of claim 1, wherein the semiconductor die includes at least one of an integrated circuit (IC), a system on a chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and a memory circuit, or a combination thereof.

8. The apparatus of claim 7, wherein the PCB supports radio frequency (RF) communications.

9. The apparatus of claim 8, wherein the PCB is included within a portable computing device including at least one of a mobile telephone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer with a wireless connection or link.

10. An apparatus comprising: a pin map corresponding to a ball grid array and covering a surface area of layers of a printed circuit board (PCB), the pin map including a plurality of electrical designations for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical designations including one of a positive polarity (P+), a negative polarity (P-), or electrical ground (G); and The pin map includes a first repeating pin polarity pattern; the first repeating pin polarity pattern includes a channel cell block having a center region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

11. The apparatus of claim 10, further comprising a semiconductor die vertically stacked relative to the PCB, the die coupled to the PCB with the ball grid array (BGA).

12. The apparatus of claim 10, wherein the pin map includes a plurality of square cells, wherein each square cell represents the electrical marking of a pin or a blank space.

13. The apparatus of claim 10, wherein the channel cell block has one positive polarity (P+) pin and one negative polarity (P-) pin, and the remaining two sub-regions of the center region include two blank spaces of the pin map.

14. The apparatus of claim 13, wherein the channel cell blocks overlap each other along a length dimension of the pin map.

15. The apparatus of claim 13, wherein the channel cell blocks do not overlap each other along a length dimension of the pin map.

16. The apparatus of claim 10, wherein the pin map includes two boundaries: a first boundary corresponding to an IC package edge and a second boundary corresponding to a die edge.

17. The apparatus of claim 11, wherein the semiconductor die includes at least one of: an integrated circuit (IC), a system on a chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and a memory circuit, or a combination thereof.

18. The apparatus of claim 17, wherein the PCB supports radio frequency (RF) communications.

19. The apparatus of claim 17, wherein the PCB is included within a portable computing device including at least one of: a mobile telephone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer with a wireless connection or link.

20. The apparatus of claim 18, wherein the PCB is included within a portable computing device including at least one of: a mobile telephone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer with a wireless connection or link.

21. An apparatus comprising: an integrated circuit component vertically stacked relative to a layer of a printed circuit board (PCB) for propagating high speed communication signals, the integrated circuit component coupled to the PCB with a ball grid array (BGA); a pin map corresponding to the BGA and covering a surface area of the PCB, the pin map including a plurality of electrical markings for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical markings including one of positive polarity (P+), negative polarity (P-), or electrical ground (G); a pin map corresponding to the BGA and covering a surface area of the PCB, the pin map including a plurality of electrical markings for each pin in the pin map and a plurality of blank spaces within the pin map; each of the plurality of electrical markings including one of positive polarity (P+), negative polarity (P-), or electrical ground (G); The pin map includes a first repeating pin polarity pattern; the first repeating pin polarity pattern includes a channel unit block having a center region defined by four pin map cells, two of the four pin map cells including two pins corresponding to a signal channel within the PCB.

22. The apparatus of claim 21, wherein the integrated circuit components include semiconductor dies stacked vertically with respect to the PCB.

23. The apparatus of claim 21, wherein the pin map includes a plurality of square cells, wherein each square cell represents the electrical designation of a pin or a blank space.

24. The apparatus of claim 21, wherein the channel unit block has one positive polarity (P+) pin and one negative polarity (P-) pin, and the remaining two sub-regions of the center region include two blank spaces of the pin map.

25. The apparatus of claim 24, wherein the channel unit blocks overlap each other along a length dimension of the pin map.

26. The apparatus of claim 24, wherein the channel unit blocks do not overlap each other along a length dimension of the pin map.

27. The apparatus of claim 21, wherein the pin map includes two boundaries: a first boundary corresponding to an IC package edge and a second boundary corresponding to a die edge.

28. The apparatus of claim 22, wherein each semiconductor die includes at least one of the following: an integrated circuit (IC), a system on a chip (SoC), a serializer / deserializer (SERDES) interface, a modem, a baseband IC, and a memory circuit, or a combination thereof.

29. The apparatus of claim 28, wherein the PCB supports radio frequency (RF) communications.

30. The apparatus of claim 29, wherein the PCB is included within a portable computing device including at least one of the following: a mobile telephone, a personal digital assistant (PDA), a pager, a smartphone, a navigation device, and a handheld computer with a wireless connection or link.

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