Silicon carbide semiconductor device

Abstract

The present disclosure relates to a silicon carbide semiconductor device, comprising: a p-type second well region provided in an upper portion of a semiconductor layer; an n-type second impurity region provided in the upper portion; a p-type second well contact region provided in an upper portion of the second well region and joined to the second impurity region at a side surface; a field insulating film provided on the second well region; a second contact portion penetrating the field insulating film and making an ohmic contact with the second impurity region and the second well contact region and being electrically connected to a first main electrode; a boundary portion gate insulating film provided from an edge portion of the second impurity region on a boundary side between an element region and a non-element region to an edge portion of a first impurity region in a first well region adjacent to the boundary; a boundary portion gate electrode thereon; and a second main electrode, wherein the second well contact region extends from below the second contact portion to the element region side, and the second impurity region extends from below the second contact portion to the non-element region side.

Description

Technical Field

[0001] The present disclosure relates to a silicon carbide semiconductor device, and particularly to a silicon carbide semiconductor device having a gate insulating film. Background Art

[0002] As a switching element used in an inverter circuit or the like, a vertical power semiconductor device is widely used, and particularly, a power semiconductor device having a MOS (Metal Oxide Semiconductor) structure is widely used. Typically, an Insulated Gate Bipolar Transistor (IGBT) and a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used.

[0003] An n-type MOSFET, which is one of silicon carbide semiconductor devices using silicon carbide as a semiconductor material, can reduce the power loss of an inverter circuit by serving as a switching element of the inverter circuit. The silicon carbide has a bandgap approximately three times greater than that of silicon (Si).

[0004] Typically, the n-type MOSFET has an n-type drift layer and a p-type well provided thereon. When the MOSFET switches from the on state to the off state, the drain voltage of the MOSFET, that is, the voltage of the drain electrode, rises rapidly, changing from approximately 0 V to several hundred V. As a result, a displacement current occurs via the parasitic capacitance existing between the p-type well and the n-type drift layer. The displacement current generated on the drain electrode side flows to the drain electrode, and the displacement current generated on the source electrode side flows to the source electrode via the p-type well. In addition, when the MOSFET switches from the off state to the on state, a displacement current flows in the direction opposite to that when switching from the on state to the off state via the p-type well.

[0005] In Patent Document 1, a well contact hole connected to the source electrode is provided through a field insulating film having a film thickness thicker than that of the gate insulating film on the outermost peripheral p-type well located below the gate pad. Thus, a structure is disclosed in which most of the displacement current flowing in the large-area p-type well located below the gate pad flows to the source electrode via the well contact hole, suppressing the occurrence of a high electric field between the p-type well directly under the gate insulating film on the opposite side of the well contact hole compared to the large-area p-type well, and preventing the breakdown of the gate insulating film.

[0006] Prior Art Documents

[0007] Patent Documents

[0008] Patent Document 1: International Publication No. WO2011 / 125274 SUMMARY OF THE INVENTION

[0009] According to the technology disclosed in Patent Document 1, on the p-type well end side of the outermost periphery of the well contact hole, in the portion where the thickness changes from the field insulating film to the gate insulating film, a height difference is provided between the well contact hole and the p-type well end side of the outermost periphery. Therefore, a distance needs to be provided between the well contact hole and the p-type well end side of the outermost periphery. Thus, since the displacement current flowing from the p-type well end side of the outermost periphery to the well contact hole generates an electric field between the potential generated in the p-type well of the outermost periphery and the potential of the gate electrode, the electric field is applied to the gate insulating film.

[0010] Most of the displacement current generated in the p-type well of the outermost periphery flows to the large-area p-type well on the side opposite to the p-type well end side of the outermost periphery of the well contact hole. Therefore, usually, a high voltage does not occur at the p-type well end of the outermost periphery, and a high electric field is not generated in the gate insulating film.

[0011] However, recently, a further increase in dV / dt, which is the variation of the drain voltage V with respect to time t, is required. For example, in the case where a large dV / dt of 20 V / nsec or more is required, the distance between the well contact hole and the p-type well end side of the outermost periphery cannot be ignored, and a non-negligible amount of displacement current flows from the p-type well end side of the outermost periphery to the well contact hole, resulting in a high voltage at the p-type well end of the outermost periphery, and there is a possibility that the gate insulating film may be broken down.

[0012] The present disclosure is made to solve the above-described problems, and an object thereof is to provide a silicon carbide semiconductor device that can suppress the electric field generated in the gate insulating film even when a large dV / dt is applied.

[0013] The silicon carbide semiconductor device of the present disclosure has an element region in which semiconductor elements are formed and a non-element region other than the element region, and in the element region, a main current flows in the thickness direction of the silicon carbide substrate. The device includes: a semiconductor layer of a first conductivity type provided on a first main surface of the silicon carbide substrate; a first well region of a second conductivity type provided in an upper portion of the semiconductor layer in the element region; a first impurity region of the first conductivity type provided in an upper portion of the first well region; a first well contact region of the second conductivity type provided in an upper portion of the first well region and joined to the first impurity region at a side surface; a gate insulating film provided on an edge portion of the first impurity region, on the first well region, and on the semiconductor layer; a gate electrode provided on the gate insulating film; a first contact portion in ohmic contact with the first impurity region and the first well contact region and electrically connected to a first main electrode provided above the semiconductor layer; a second well region of the second conductivity type provided in an upper portion of the semiconductor layer in the non-element region; a second impurity region of the first conductivity type provided in an upper portion of the second well region; a second well contact region of the second conductivity type provided in an upper portion of the second well region and joined to the second impurity region at a side surface; a field insulating film provided on the second well region; at least one second contact portion penetrating the field insulating film, in ohmic contact with the second impurity region and the second well contact region, and electrically connected to the first main electrode; a boundary portion gate insulating film provided from an edge portion of the second impurity region on the boundary side between the element region and the non-element region to an edge portion of the first impurity region in the first well region adjacent to the boundary; a boundary portion gate electrode provided on the boundary portion gate insulating film; and a second main electrode provided on a second main surface of the silicon carbide substrate opposite to the first main surface. The second well contact region extends from below the at least one second contact portion to the element region side, and the second impurity region extends from below the at least one second contact portion to the non-element region side.

[0014] According to the silicon carbide semiconductor device of the present disclosure, in the case of switching from an off state to an on state, due to the formation of the second impurity region, more displacement current flowing in from the at least one second contact portion can flow on the non-element region side compared to the at least one second contact portion. Therefore, the displacement current flowing on the element region side compared to the second contact portion can be reduced, the potential difference between the end portion of the second well region and the boundary portion gate electrode can be suppressed, and the dielectric breakdown of the boundary portion gate insulating film can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a top view schematically showing a top view structure of the silicon carbide semiconductor device according to Embodiment 1.

[0016] Figure 2 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 1.

[0017] Figure 3 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 1.

[0018] Figure 4 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 1.

[0019] Figure 5 It is a partial top view showing the structure of the silicon carbide semiconductor device of Embodiment 1.

[0020] Figure 6 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 1.

[0021] Figure 7 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0022] Figure 8 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0023] <![CDATA[ Figure 9 ]] It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0024] Figure 10 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0025] Figure 11 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0026] Figure 12 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0027] Figure 13 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0028] Figure 14 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0029] Figure 15 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0030] Figure 16 It is a cross-sectional view for explaining the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0031] Figure 17 It is a cross-sectional view showing the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0032] Figure 18 It is a cross-sectional view showing the manufacturing method of the silicon carbide semiconductor device of Embodiment 1.

[0033] Figure 19 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 2.

[0034] Figure 20 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 2.

[0035] Figure 21 It is a partial top view showing the structure of the silicon carbide semiconductor device of Embodiment 3.

[0036] Figure 22 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 3.

[0037] Figure 23 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 4.

[0038] Figure 24 It is a cross-sectional view showing the structure of the silicon carbide semiconductor device of Embodiment 4. Detailed Embodiments

[0039] <Introduction>

[0040] In the following description, the "element region" refers to the region through which the main current flows in the on-state of the semiconductor element. Further, hereinafter, the "outer side" refers to the direction toward the outer periphery of the semiconductor element, and the "inner side" refers to the direction opposite to the "outer side".

[0041] In addition, the accompanying drawings are schematic diagrams, and the sizes of the images shown in different accompanying drawings and the mutual relationships of the positions are not necessarily correctly described and can be appropriately changed. In the following description, the same reference numerals are attached to the same constituent elements for illustration, and their names and functions are also the same. Therefore, detailed descriptions thereof may sometimes be omitted. In this specification, in cases where it is described as "on ~" and "covering ~", there is no hindrance to the presence of intervening substances between the constituent elements. For example, in the case of describing "B provided on A" or "A covering B", it can mean that another constituent element C is provided between A and B, and it can also mean that no other constituent element C is provided between A and B. In the following description, terms such as "upper", "lower", "side", "bottom", "front", or "back" that indicate specific positions and directions may sometimes be used, but these terms are appropriately used to make the content of the embodiments easy to understand and are not related to the directions in actual implementation.

[0042] In addition, terms such as "MOS" were previously used for metal-oxide-semiconductor junction structures. However, especially in MOS field-effect transistors (MOSFETs) having an MOS structure, from the viewpoints of recent integration and improvement of manufacturing processes, the materials of the gate insulating film and the gate electrode have been improved.

[0043] For example, in MOSFETs, mainly from the viewpoint of self-matching formation of source / drain, polysilicon is used as the material of the gate electrode instead of metal. In addition, from the viewpoint of improving electrical characteristics, a material with a high dielectric constant is used as the material of the gate insulating film, but this material is not necessarily limited to oxides.

[0044] Therefore, the term "MOS" is not necessarily adopted only for metal-oxide-semiconductor stacked structures, and such a limitation is not assumed in this specification. That is, in view of common technical knowledge, here "MOS" has the meaning of widely including not only the abbreviation derived from its etymology but also conductor-insulator-semiconductor stacked structures.

[0045] Hereinafter, embodiments will be described with reference to the accompanying drawings. In addition, in the following accompanying drawings, the same or corresponding parts are attached with the same reference numerals and the description thereof will not be repeated.

[0046] In addition, in Embodiments 1 to 4 described below, as an example of a silicon carbide semiconductor device, a vertical n-type MOSFET in which the main current flows in the thickness direction of the substrate will be described.

[0047] <Embodiment 1>

[0048] <Device Structure>

[0049] Figure 1 FIG. 1 is a top view schematically showing a top view structure of an n-type silicon carbide MOSFET 100 according to Embodiment 1 of the present disclosure. In addition, in all embodiments Figure 1 the top view structures are common.

[0050] In addition, regarding the n-type silicon carbide MOSFET 100, a planar gate type will be described, but the application of the present disclosure is not limited to the planar gate type and can also be applied to a trench gate type. In addition, as long as it has a MOS structure, it is not limited to MOSFETs and can also be applied to IGBTs.

[0051] As Figure 1 shown, the n-type silicon carbide MOSFET 100 has a quadrilateral outer shape, and gate wirings 103 are provided on its outer edge. In addition, at the center of the main surface of the n-type silicon carbide MOSFET 100, a cell arrangement region CR is provided, and a plurality of unit cells UC, which are the minimum units of the MOS structure, are arranged in the cell arrangement region CR.

[0052] The shape of the cell arrangement region CR in a top view forms a quadrilateral with the center of one side recessed inward, and a gate pad 102 is provided so as to enter the portion recessed inward of the cell arrangement region CR. In addition, the cell arrangement region CR is separated from the gate pad 102 and the gate wirings 103.

[0053] A gate voltage is applied to the gate pad 102 from an external control circuit (not shown), and the gate voltage applied here is supplied to the gate electrode (not shown) of the unit cell UC through the gate wirings 103.

[0054] In addition, in the cell arrangement region CR, a source pad 101 (source electrode) that connects the sources of the respective unit cells in parallel is provided, and the source pad 101 is provided so as to cover substantially the entire surface of the cell arrangement region CR. In addition, in Figure 1 the unit cell UC is shown in the source pad 101 for convenience.

[0055] Figure 2 is Figure 1 a cross-sectional view in the direction of the arrow at the C-C line in FIG. 2, and is a cross-sectional view schematically showing the structure of the unit cell UC. As Figure 2 shown, the n-type silicon carbide MOSFET 100 is provided on a silicon carbide substrate 1 that contains n-type (first conductivity type) impurities at a relatively high concentration.

[0056] On the first main surface of the silicon carbide substrate 1, a drift layer 2 (semiconductor layer), which is a semiconductor layer containing n-type impurities at a relatively low concentration, is provided. The drift layer 2 is, for example, an epitaxial growth layer formed by epitaxial growth.

[0057] In the upper part of the drift layer 2, a first well region 3 containing p-type (second conductivity type) impurities is provided. In the upper part of the first well region 3, a first well contact region 6 containing p-type impurities at a relatively high concentration is selectively provided. Moreover, a first source region 5 (first impurity region) containing n-type impurities at a relatively high concentration is provided so as to be in contact with two side surfaces of the first well contact region 6. In addition, the drift layer 2 between adjacent first well regions 3 becomes a JFET (Junction Field Effect Transistor) region 4.

[0058] In addition, the depth of the first well region 3 from the outermost surface of the drift layer 2 is formed deeper than the depth of the first source region 5 from the outermost surface of the drift layer 2. Further, the depth of the first well contact region 6 from the outermost surface of the drift layer 2 is formed to be equal to or deeper than the depth of the first source region 5 from the outermost surface of the drift layer 2, but does not exceed the first well region 3.

[0059] A gate insulating film 8 is formed on the drift layer 2, and a gate electrode 9 is provided on the gate insulating film 8. The gate electrode 9 is provided at the edge portions of the JFET region 4, the first well region 3, and the first source region 5.

[0060] Moreover, an interlayer insulating film 29 is provided on the drift layer 2 including above the gate electrode 9, but a first source contact portion 7 (first contact portion) is provided so as to be in contact with a part of the first well contact region 6 and the first source region 5. A silicide film SD made of, for example, nickel silicide is provided at the bottom of the first source contact portion 7, and the first well contact region 6 and a part of the first source region 5 are covered with the silicide film SD. The first well contact region 6 and the first source region 5 are electrically connected to a source pad 101 via the silicide film SD and the first source contact portion 7. In addition, a drain electrode 104 is provided on the second main surface of the silicon carbide substrate 1 on the side opposite to the first main surface.

[0061] The silicide film SD is not limited to nickel silicide, and aluminum silicide, titanium silicide can also be used. When forming the source pad 101, the first source contact portion 7 can be formed by burying a metal such as nickel, aluminum, or titanium, which is a material for the source pad 101, in the contact hole.

[0062] The impurity concentration of the drift layer 2 is preferably 1.0×10 14 cm -3 or more and 1.0×10 17 cm -3Hereinafter, the impurity concentration of the JFET region 4 is preferably formed to be lower than that of the first well region 3. This is to make the depletion layer caused by the pn junction formed by the JFET region 4 and the first well region 3 extend more toward the JFET region 4 side. The impurity concentration of the first well region 3 is preferably 1.0×10 16 cm -3 or more and 1.0×10 20 cm -3 or less. The impurity concentration of the first source region 5 is preferably 1.0×10 17 cm -3 or more and 1.0×10 21 cm -3 or less. The impurity concentration of the first well contact region 6 is preferably 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less.

[0063] Figure 3 is Figure 1 a cross-sectional view in the direction of the arrow at the A-A line in

[0064] As Figure 3 shown, the structure of the element region is the same as that shown in Figure 2 In the non-element region, a second well region 13 containing a p-type impurity is provided in the upper part of the drift layer 2. In the upper part of the second well region 13, a second source region 15 (second impurity region) containing an n-type impurity at a relatively high concentration and a p-type second well contact region 16 that is in contact with the second source region 15 and has an impurity concentration higher than that of the second well region 13 are selectively provided. The second source region 15 is formed to have a size that occupies most of the upper part of the second well region 13 in the planar direction. The second well contact region 16 is provided on the side closer to the element region than the second source region 15 in the remaining part of the upper part of the second well region 13, and is provided to extend from the pn junction part below the second source contact part 17 (second contact part) to below the boundary gate electrode 19.

[0065] The drift layer 2 between the first well region 3 adjacent to the second well region 13 and the second well region 13 among the plurality of first well regions 3 in the element region becomes the outermost peripheral JFET region 14, and the boundary between the element region and the non-element region is defined as the outermost peripheral JFET region 14.

[0066] In the non-element region, a field insulating film 28 is formed on the second well region 13, and a second source contact portion 17 is provided which penetrates the field insulating film 28 and is electrically connected to the second source region 15 and the second well contact region 16. Further, on the second well region 13 at the boundary between the element region and the non-element region and on the first well region 3, a boundary portion gate electrode 19 is provided via a boundary portion gate insulating film 18. In addition, the boundary portion gate electrode 19 extends onto the field insulating film 28 above the second source region 15. In Figure 3 this, the gate electrode 9 in the element region and the boundary portion gate electrode 19 are not continuous, but are continuous in a top view.

[0067] An interlayer insulating film 29 is provided on the drift layer 2 including the gate electrode 9 and the boundary portion gate electrode 19, and the gate electrode 9, the boundary portion gate electrode 19, and the source pad 101 are electrically separated by the interlayer insulating film 29. The second source contact portion 17 also penetrates the interlayer insulating film 29 and is electrically connected to the second source region 15 and the second well contact region 16. Further, a gate contact portion 27 is provided so as to penetrate the interlayer insulating film 29 and reach the boundary portion gate electrode 19 on the field insulating film 28, and the boundary portion gate electrode 19 and the gate electrode 9 are electrically connected to the gate wiring 103 via the gate contact portion 27.

[0068] A protective film PF is provided on the gate wiring 103 in the non-element region, on the source pad 101, and on a part of the upper portion of the source pad 101 in the element region. The protective film PF is formed of an insulating film.

[0069] At the bottom of the second source contact portion 17, a silicide film SD made of, for example, nickel silicide is provided, and a part of the second source region 15 and the second well contact region 16 is covered with the silicide film SD. The second well contact region 16 and the second source region 15 are electrically connected to the source pad 101 via the silicide film SD and the second source contact portion 17. In addition, the silicide film SD is not limited to nickel silicide, and aluminum silicide, titanium silicide, etc. can also be used. When forming the source pad 101, the second source contact portion 17 can be formed by burying a metal such as nickel, aluminum, or titanium which becomes the material of the source pad 101 in the contact hole.

[0070] The impurity concentration of the second well region 13 is preferably 1.0×10 16 cm -3 or more and 1.0×10 20 cm -3 or less. The impurity concentration of the second source region 15 is preferably 1.0×10 17 cm -3 or more and 1.0×10 21 cm -3 or less. The impurity concentration of the second well contact region 16 is preferably 1.0×10 18cm -3 or more and 1.0×10 22 cm -3 or less. By setting the concentration within such a range, a silicon carbide semiconductor device having a desired rating can be obtained.

[0071] In addition, the length of the second well contact region 16 extending from the pn junction portion below the second source contact portion 17 to the element region side is preferably 1.0 μm or more and 100 μm or less. By setting the range in this way, a margin in the size design of the silicon carbide semiconductor device can be obtained.

[0072] Figure 4 is Figure 1 a cross-sectional view taken along line B-B in Figure 4 and schematically shows the structure of the element region and the region where the gate pad 102 as a non-element region is formed. As Figure 3 shown, the structures of the element region and the non-element region are the same as those

[0073] Figure 5 schematically shows Figure 1 the top view of the structure of the element region and the non-element region in region X in

[0074] As Figure 5 shown, the top view shape of the unit cell UC in the element region is square and arranged in a matrix, but this is an example and is not limited to this shape, and it can also be rectangular or polygonal.

[0075] In the unit cell UC having a square top view shape, the first source region 5 surrounds the periphery of the first well contact region 6 having a square outer shape, and further, the outside thereof is surrounded by the first well region 3.

[0076] The JFET region 4 is formed between the unit cells UC, and the corners between the unit cells UC adjacent in the diagonal direction are connected to each other through the first well region 3.

[0077] In the non-element region, the second well contact region 16 is provided in a continuous manner with the second well region 13, and the second source region 15 is provided in a continuous manner with the second well contact region 16.

[0078] The second well contact region 16 is continuously formed so as to reach below a plurality of second source contact portions 17 in a top view, and similarly, the second source region 15 is continuously provided so as to reach below a plurality of second source contact portions 17 in a top view.

[0079] Figure 6 isFigure 5 The cross-sectional view in the direction indicated by the arrow at the D-D line in Figure 5 is a cross-sectional view schematically showing the structures of the element region and the non-element region. As Figure 6 shown, a plurality of second source contact portions 17 are separately provided, and between the plurality of second source contact portions 17, as

[0080] <Manufacturing Method>

[0081] Next, an example of the manufacturing method of the n-type silicon carbide MOSFET 100 will be described using Figures 7 to 18 which is a cross-sectional view sequentially showing the manufacturing processes.

[0082] First, as Figure 7 shown, on the first main surface of the n-type and low-resistance silicon carbide substrate 1 having a (0001) plane orientation and a 4H polytype on the first main surface, an n-type drift layer 2 of silicon carbide is epitaxially grown by Chemical Vapor Deposition (CVD). The n-type impurity concentration of the drift layer 2 is, for example, set to 1×10 14 cm -3 ~1×10 17 cm -3 , and the thickness of the drift layer 2 is, for example, set to 5 μm to 50 μm.

[0083] Next, an implantation mask (not shown) is formed on the drift layer 2 by photoresist or the like, and Al (aluminum), which is a p-type impurity, is ion-implanted to form a p-type first well region 3 and a second well region 13 in the upper portion of the drift layer 2. The depth of the Al ion implantation is set to a depth not exceeding the thickness of the drift layer 2, for example, 0.5 to 3 μm. In addition, the impurity concentration of the ion-implanted Al is, for example, set to 1×10 16 cm -3 ~1×10 20 cm -3 , which is higher than the n-type impurity concentration of the drift layer 2. After the Al is ion-implanted, the implantation mask is removed. Here, although the first well region 3 and the second well region 13 are formed in the same process, they may also be formed in separate processes.

[0084] Next, in Figure 8In the process shown, an implantation mask (not shown) is formed on the drift layer 2 using a photoresist or the like, and N (nitrogen), which is an n-type impurity, is ion-implanted. An n-type first source region 5 is formed in the upper part of the first well region 3, and a second source region 15 is formed in the upper part of the second well region 13. The ion implantation depth of N is shallower than the thicknesses of the first well region 3 and the second well region 13. In addition, the impurity concentration of the ion-implanted N is set to, for example, 1×10 17 cm -3 ~1×10 21 cm -3 , which is higher than the p-type impurity concentration of the first well region 3 and the second well region 13, respectively. After the N ion implantation, the implantation mask is removed. Here, the first source region 5 and the second source region 15 are formed in the same process, but they can also be formed in separate processes.

[0085] Next, in the Figure 9 process shown, an implantation mask (not shown) is formed on the drift layer 2 using a photoresist or the like, and Al, which is a p-type impurity, is ion-implanted. A p-type first well contact region 6 is formed in the upper part of the first well region 3, and a second well contact region 16 is formed in the upper part of the second well region 13. The first well contact region 6 is formed from the outermost surface of the first source region 5 to a depth where it is electrically connected to the first well region 3. The second well contact region 16 is formed from the outermost surface of the second source region 15 to a depth where it is electrically connected to the second well region 13. The first well contact region 6 is provided to obtain good electrical contact with the first source contact portion 7 that electrically connects the first well region 3 and the source pad 101.

[0086] The p-type impurity concentrations of the first well contact region 6 and the second well contact region 16 are preferably higher than the p-type impurity concentrations of the first well region 3 and the second well region 13, respectively. After the Al ion implantation, the implantation mask is removed. Here, the first well contact region 6 and the second well contact region 16 are formed in the same process, but they can also be formed in separate processes.

[0087] Next, in the Figure 10In the process shown, an implantation mask RM1 is formed on the drift layer 2 using a photoresist or the like, and N, which is an n-type impurity, is ion-implanted to form high-concentration regions with a high concentration of the n-type impurity within the JFET region 4 and within the outermost peripheral JFET region 14, so that the n-type impurity concentration in the JFET region 4 and the outermost peripheral JFET region 14 is higher than the n-type impurity concentration in the drift layer 2. However, the impurity concentration of the ion-implanted N is preferably lower than the p-type impurity concentration in the first well region 3. The reason is that by relatively reducing the impurity concentration in the JFET region 4 and the outermost peripheral JFET region 14 with respect to the first well region 3, when a reverse bias is applied to the pn junction formed between the first well region 3 and the JFET region 4 and the outermost peripheral JFET region 14, the depletion layer extends to the JFET region 4 and the outermost peripheral JFET region 14 side.

[0088] After the ion implantation of N, the implantation mask RM1 is removed. In addition, in the present embodiment, as an example, the JFET region 4 and the outermost peripheral JFET region 14 with an impurity concentration higher than that of the drift layer 2 are formed by n-type impurity implantation, but it is not necessarily n-type impurity implantation, and p-type impurity implantation can also be used. In addition, the impurity concentration in the JFET region 4 and the outermost peripheral JFET region 14 can also be the same as the impurity concentration in the drift layer 2.

[0089] Next, in Figure 11 the process shown, an n-type or p-type epitaxial layer EP is epitaxially grown on the drift layer 2. The thickness of the epitaxial layer EP can be set to 10 to 500 nm. In addition, the epitaxial layer EP is provided as an epitaxial channel layer in which a channel is formed inside, but it is not a necessary structure, and is omitted in the drawings shown in Figures 2 to 4 and below.

[0090] Next, in Figure 12 the process shown, a field insulating film 28 is formed on the drift layer 2 by a reduced-pressure CVD method, and an etching mask RM2 is formed on the field insulating film 28 using a photoresist or the like. Then, the field insulating film 28 is partially etched and removed. The removed portion is the portion where the gate insulating film 8 and the boundary gate insulating film 18 are formed later. After that, the etching mask RM2 is removed.

[0091] Next, in Figure 13 the process shown, the surface of the drift layer 2 is thermally oxidized to form a gate insulating film 8 with a desired thickness.

[0092] Next, in Figure 14In the process shown, on the gate insulating film 8, a conductive polysilicon film is formed by reduced-pressure CVD method, and it is patterned by etching to form the gate electrode 9 and the boundary gate electrode 19. Further, the gate insulating film 8 not covered by the gate electrode 9 and the boundary gate electrode 19 is removed by etching or the like. Here, the gate insulating film 8 located under the boundary gate electrode 19 becomes the boundary gate insulating film 18.

[0093] Next, in Figure 15 the process shown, an interlayer insulating film 29 is formed by reduced-pressure CVD method on the drift layer 2 including on the gate electrode 9 and the boundary gate electrode 19.

[0094] Next, in Figure 16 the process shown, a first source contact hole 7C that penetrates the interlayer insulating film 29 and the gate insulating film 8 to reach the first well contact region 6 and the first source region 5, and a second source contact hole 17C that penetrates the interlayer insulating film 29 and the gate insulating film 8 to reach the second well contact region 16 and the second source region 15 are formed. Further, a gate contact hole 27C that penetrates the interlayer insulating film 29 to reach the gate electrode 9 is formed.

[0095] Next, in Figure 17 the process shown, by sputtering method or the like, a metal film MF mainly composed of nickel (Ni) is formed on the interlayer insulating film 29, and heat treatment is performed at a temperature of 600 °C or higher and 1100 °C or lower to react the metal film MF mainly composed of Ni with silicon carbide to form a silicide film SD. Next, the metal film MF remaining on the interlayer insulating film 29 other than the silicide film SD is removed by wet etching. Through this silicide film SD, an ohmic contact is formed on the bottom surfaces of the first source contact hole 7C and the second source contact hole 17C.

[0096] Next, in Figure 18 the process shown, on the second main surface (back surface) of the silicon carbide substrate 1, a metal film mainly composed of Ni is formed and heat-treated to form a back contact portion (not shown) on the back surface of the silicon carbide substrate 1. Thereafter, on the front surface of the silicon carbide substrate 1 on which the interlayer insulating film 29 is formed, a metal layer such as Al is formed by sputtering method or evaporation method, and is processed into a predetermined shape by photolithography technology to form the first source contact portion 7, the second source contact portion 17, and the gate contact portion 27, and a source pad 101 connected to the first source contact portion 7 and the second source contact portion 17 and a gate wiring 103 connected to the gate contact portion 27 are formed. At this time, a gate pad 102 connected to the gate wiring 103 is also formed ( Figure 4)。In addition, a metal layer such as Al is formed on the back contact portion on the back surface of the silicon carbide substrate 1 by sputtering or evaporation to form the drain electrode 104. Then, a protective film PF is formed of an insulating film or the like so as to cover the gate wiring 103 in the non-element region, the source pad 101, and a part of the upper portion of the source pad 101 in the element region. Figure 3 ),thus completing the n-type silicon carbide MOSFET 100.

[0097] <Effect>

[0098] Next, the effects obtained by the structure of the n-type silicon carbide MOSFET 100 of Embodiment 1 will be described. In the n-type silicon carbide MOSFET 100, for example, as Figure 3 shown, the second well contact region 16 is provided to extend from the pn junction portion below the second source contact portion 17 to the element region side, and the second source region 15 extends from the pn junction portion below the second source contact portion 17 to the non-element region side.

[0099] In addition, as Figure 5 shown, the second well contact region 16 is continuously formed so as to reach below a plurality of second source contact portions 17 in a plan view. Similarly, the second source region 15 is continuously provided so as to reach below a plurality of second source contact portions 17 in a plan view. Therefore, when the n-type silicon carbide MOSFET 100 switches from the off state to the on state, the displacement current flowing in from the second source contact portion 17 can be dispersed, and concentration of the displacement current can be avoided.

[0100] The second source contact portion 17 is made of a metal such as nickel, aluminum, or titanium, and a silicide film SD of silicon carbide and metal is formed at the bottom of the second source contact portion 17, thereby forming good ohmic contacts with both the second source region 15 and the second well contact region 16.

[0101] Here, when the ohmic contact portions of the second source contact portion 17 are formed for the p-type second well contact region 16 and the n-type second source region 15 by the same process, the contact resistance value per unit area (contact differential resistance value) between the second source contact portion 17 and the second well contact region 16 is greater than the contact differential resistance value between the second source contact portion 17 and the second source region 15.

[0102] Therefore, in order to suppress the potential drop in the ohmic contact portion between the second source contact portion 17 and the second well contact region 16, it is preferable to increase the area of the second well contact region 16 below the second source contact portion 17 as much as possible. Specifically, it is preferable that the area of the second well contact region 16 below the second source contact portion 17 is 1 time or more and 100 times or less the area of the second source region 15 below the second source contact portion 17.

[0103] This is also shown in Figure 5 that the area of the second well contact region 16 below the second source contact portion 17 is more than twice the area of the second source region 15 below the second source contact portion 17. Therefore, it is possible to suppress a potential drop in a portion of the second source contact portion 17 that is in ohmic contact with the second well contact region 16.

[0104] In addition, although the contact differential resistance value between the second source contact portion 17 and the second well contact region 16 increases, it has the advantage of simplifying the manufacturing process.

[0105] In addition, the impurity concentration of the second source region 15 is set to be 1.0×10 17 cm -3 or more and 1.0×10 21 cm -3 or less, and more preferably set to be 1×10 19 cm -3 or more and 1×10 20 cm -3 or less. In addition, the impurity concentration of the second well contact region 16 is set to be 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less, and more preferably set to be 1.0×10 19 cm -3 or more and 1.0×10 21 cm -3 or less.

[0106] Here, the sheet resistance value of the second source region 15 is lower than the sheet resistance value of the second well contact region 16. Thus, current easily flows through the second source region 15.

[0107] By adopting the structure described above, when the n-type silicon carbide MOSFET 100 switches from the off state to the on state, for example, when a large dV / dt (time variation of voltage) of 20 V / nsec or more is applied between the source and the drain, a larger proportion of the displacement current flowing in from the second source contact portion 17 can flow through the second source region to the non-element region side beyond the second source contact portion 17, and the displacement current flowing to the element region side beyond the second source contact portion 17 can be suppressed. Therefore, it is possible to reduce the voltage generated at the end portion (the end of the second well region 13) on the element region side of the second well region 13, the potential difference between the end of the second well region 13 and the boundary gate electrode 19 is suppressed, the dielectric breakdown of the boundary gate insulating film 18 is suppressed, and the reliability as a semiconductor device is improved.

[0108] <Embodiment 2>

[0109] Figure 19 is a cross-sectional view showing the structure of the n-type silicon carbide MOSFET 200 of Embodiment 2, corresponding to the cross-sectional view in the direction indicated by the arrow at line A-A in Figure 1 . As shown in Figure 19 , in the n-type silicon carbide MOSFET 200, the portion of the second well contact region 16 extending from the pn junction portion below the second source contact portion 17 to the element region side extends only directly below the field insulating film 28 and does not reach directly below the boundary portion gate electrode 19.

[0110] Figure 20 is Figure 1 the cross-sectional view in the direction indicated by the arrow at line B-B in Figure 20 , and is a cross-sectional view schematically showing the structure of the element region and the formation region of the gate pad 102 as a non-element region. As shown in Figure 19 , the structures of the element region and the non-element region are the same as the structures shown in

[0111] Thus, in the n-type silicon carbide MOSFET 200 of Embodiment 2, since the second well contact region 16 does not reach below the boundary portion gate electrode 19, the boundary portion gate insulating film 18 is not formed on the high-concentration second well contact region 16, and the film quality of the boundary portion gate insulating film 18 is improved. That is, in a high-concentration impurity implantation region, the crystal structure is broken down, so the homogeneity of the boundary portion gate insulating film 18 formed thereon is reduced. However, in the structure of the n-type silicon carbide MOSFET 200, this does not occur, and the film quality evaluated by breakdown voltage and leakage current is improved. Therefore, the suppression effect of dielectric breakdown of the boundary portion gate insulating film 18 becomes higher, and the reliability of the semiconductor device is further improved.

[0112] <Embodiment 3>

[0113] Figure 21 is a top view showing the structure of the element region and the non-element region of the n-type silicon carbide MOSFET 300 of Embodiment 3, corresponding to the top view in region X in [[ID=,30]] Figure 1 . In addition, similar to Figure 5 , for ease of explanation, the insulating film and electrodes on the drift layer 2 are omitted, and only the upper portion structure of the drift layer 2 is shown. In addition, in Figure 21 , for structures that are the same as the structures described using Figure 5 , the same reference numerals are added, and repeated explanations are omitted.

[0114] As shown in Figure 21As shown, in the n-type silicon carbide MOSFET 300, in a part of the second well contact region 16, the length of the part extending from the junction with the second source region 15 to the element region side is shorter than the length of the part extending from the pn junction portion below the second source contact portion 17 to the element region side. Moreover, corresponding to the amount by which the length of the second well contact region 16 is shortened, the length of the second source region 15 is formed to be long. In a plan view, a shape is formed in which the second well contact region 16 is partially recessed toward the element region side and the second source region 15 is partially protruded.

[0115] In addition, in Figure 21 , the part where the second well contact region 16 is recessed and the second source region 15 is protruded is only one place between two second source contact portions 17. However, typically, a plurality of second source contact portions 17 are provided along the gate wiring 103 in the non-element region, so the part where the second well contact region 16 is recessed and the second source region 15 is protruded can be provided respectively between the second source contact portions 17.

[0116] Figure 22 is Figure 21 a cross-sectional view in the direction of the arrow at the D-D line in Figure 22 As shown, in the n-type silicon carbide MOSFET 300, the length of the second well contact region 16 is formed shorter than Figure 3 the length of the second well contact region 16 of the n-type silicon carbide MOSFET 100 extending from the junction with the second source region 15 to the element region side shown, and correspondingly the second source region 15 is formed to be long.

[0117] By partially shortening the second well contact region 16 in this way and correspondingly lengthening the second source region 15, when the n-type silicon carbide MOSFET 300 switches from the off state to the on state, a larger proportion of the displacement current flowing in from the second source contact portion 17 can flow through the lengthened second source region 15 to the non-element region side farther than the second source contact portion 17, and the displacement current flowing to the element region side farther than the second source contact portion 17 can be further suppressed. Therefore, the voltage generated at the end portion (second well region 13 end) on the element region side of the second well region 13 can be further reduced, the potential difference between the second well region 13 end and the boundary portion gate electrode 19 is further suppressed, the suppression effect of the dielectric breakdown of the boundary portion gate insulating film 18 becomes higher, and the reliability of the semiconductor device is further improved.

[0118] <Embodiment 4>

[0119] Figure 23 is a cross-sectional view showing the structure of the n-type silicon carbide MOSFET 400 of Embodiment 4, and is the same as Figure 1is equivalent to the cross-sectional view taken in the direction of the arrow at the A-A line in Figure 23 As shown, in the n-type silicon carbide MOSFET 400, a portion of the second well contact region 16 that extends from the pn junction portion below the second source contact portion 17 to the element region side is provided at the end of the second well region 13 (the end of the second well region 13).

[0120] Figure 24 is Figure 1 the cross-sectional view taken in the direction of the arrow at the B-B line in Figure 24 As shown, the structures of the element region and the formation region of the gate pad 102 as a non-element region are schematically shown. As Figure 23 shown, the structures of the element region and the non-element region are the same as those

[0121] Thus, in the n-type silicon carbide MOSFET 400 of the fourth embodiment, since the second well contact region 16 is provided at the end of the second well region 13, when the n-type silicon carbide MOSFET 400 switches from the off state to the on state, the voltage generated at the end of the second well region 13 can be effectively reduced.

[0122] That is, the sheet resistance value of the second well contact region 16 is lower than that of the second well region 13, so the voltage generated at the end of the second well contact region 16 can be made lower than the voltage generated at the end of the second well region 13. As a result, the potential difference between the end of the second well region 13 and the boundary portion gate electrode 19 is further suppressed, and the effect of suppressing the dielectric breakdown of the boundary portion gate insulating film 18 becomes higher, and the reliability of the semiconductor device is further improved.

[0123] Although the present disclosure has been described in detail, the above description is only an example in all aspects, and the present disclosure is not limited thereto. It should be understood that countless variations that are not illustrated can be conceived without departing from the scope of the present disclosure.

[0124] In addition, the present disclosure can freely combine the respective embodiments within the disclosed scope, or appropriately deform or omit the respective embodiments.

Claims

1. A silicon carbide semiconductor device having an element region in which semiconductor elements are formed and a non-element region outside the element region, and in which a main current flows in the thickness direction of the silicon carbide substrate, the silicon carbide semiconductor device comprising: A semiconductor layer of a first conductivity type provided on a first main surface of the silicon carbide substrate; A first well region of a second conductivity type provided in an upper portion of the semiconductor layer in the element region; A first impurity region of a first conductivity type provided in an upper portion of the first well region; A first well contact region of a second conductivity type provided in an upper portion of the first well region and joined to the first impurity region at a side surface; A gate insulating film provided on an edge portion of the first impurity region, on the first well region, and on the semiconductor layer; A gate electrode provided on the gate insulating film; A first contact portion making an ohmic contact with the first impurity region and the first well contact region and electrically connected to a first main electrode provided above the semiconductor layer; A second well region of a second conductivity type provided in an upper portion of the semiconductor layer in the non-element region; A second impurity region of a first conductivity type provided in an upper portion of the second well region; A second well contact region of a second conductivity type provided in an upper portion of the second well region and joined to the second impurity region at a side surface; A field insulating film provided on the second well region; At least one second contact portion penetrating the field insulating film, making an ohmic contact with the second impurity region and the second well contact region, and electrically connected to the first main electrode; A boundary portion gate insulating film provided from an edge portion of the second impurity region on the boundary side between the element region and the non-element region to an edge portion of the first impurity region in the first well region adjacent to the boundary; A boundary portion gate electrode provided on the boundary portion gate insulating film; And A second main electrode provided on a second main surface of the silicon carbide substrate opposite to the first main surface, The second well contact region extending from below the at least one second contact portion to the element region side, The second impurity region extending from below the at least one second contact portion to the non-element region side.

2. The silicon carbide semiconductor device according to claim 1, wherein The at least one second contact portion is a plurality of second contact portions, The second well contact region is continuously provided so as to reach below the plurality of second contact portions in a plan view, The second impurity region is continuously provided so as to reach below the plurality of second contact portions in a plan view.

3. The silicon carbide semiconductor device according to claim 1, wherein The second well contact region extends from below the at least one second contact portion to directly below the boundary portion gate insulating film.

4. The silicon carbide semiconductor device according to claim 1, wherein The second well contact region is provided to have a length that does not reach directly below the boundary portion gate insulating film from below the at least one second contact portion.

5. The silicon carbide semiconductor device according to claim 2, wherein In the second well contact region, the length of the portion extending from the junction with the second impurity region between the plurality of second contacts to the element region side is shorter than the length of the portion extending from the junction with the second impurity region below the at least one second contact to the element region side.

6. The silicon carbide semiconductor device according to claim 1, wherein, The second well contact region extends from below the at least one second contact to the end of the second well region on the element region side.

7. The silicon carbide semiconductor device according to claim 1, wherein, The area of the second well contact region in ohmic contact with the at least one second contact is larger than the area of the second impurity region in ohmic contact with the at least one second contact.

8. The silicon carbide semiconductor device according to claim 1, wherein, The area of the second well contact region in ohmic contact with the at least one second contact is 1 times or more and 100 times or less the area of the second impurity region in ohmic contact with the at least one second contact.

9. The silicon carbide semiconductor device according to claim 1, wherein, The impurity concentration of the first conductivity type in the second impurity region is 1.0×10 17 cm -3 or more and 1.0×10 21 cm -3 or less.

10. The silicon carbide semiconductor device according to claim 1, wherein, The impurity concentration of the first conductivity type in the second impurity region is 1.0×10 19 cm -3 or more and 1.0×10 20 cm -3 or less.

11. The silicon carbide semiconductor device according to claim 1, wherein, The impurity concentration of the second conductivity type in the second well contact region is 1.0×10 18 cm -3 or more and 1.0×10 22 cm -3 or less.

12. The silicon carbide semiconductor device according to claim 1, wherein, The impurity concentration of the second conductivity type in the second well contact region is 1.0×10 19 cm -3 or more and 1.0×10 21 cm -3 or less.

13. The silicon carbide semiconductor device according to claim 1, wherein, In the second well contact region, the length of the portion extending from the junction with the second impurity region below the at least one second contact to the element region side is 1.0 μm or more and 100 μm or less.

14. The silicon carbide semiconductor device according to claim 1, wherein, The sheet resistance value of the second impurity region is lower than the sheet resistance value of the second well contact region.

15. The silicon carbide semiconductor device according to claim 1, wherein, The contact differential resistance value between the second impurity region and the at least one second contact is lower than the contact differential resistance value between the second well contact region and the at least one second contact.

16. The silicon carbide semiconductor device according to claim 1, wherein, The time variation of the voltage applied between the first main electrode and the second main electrode is 20 V / nsec or more.

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