Dual-mode beidou time service and distribution device and method based on localization platform

Abstract

The application relates to a dual-mode Beidou timing and distribution device and method based on a localization platform, characterized by comprising a circuit board, wherein a Beidou integrated module, an FPGA module, a single-chip microcomputer, a plurality of level conversion circuit modules, a level driving circuit module and a DC / DC power conversion circuit module are arranged on the circuit board. The application can realize dual-mode Beidou timing and distribution.

Description

Technical Field

[0001] This invention belongs to the field of dual-mode BeiDou timing and distribution technology, and relates to a dual-mode BeiDou timing and distribution device and method, especially a dual-mode BeiDou timing and distribution device and method based on a domestic platform. Background Technology

[0002] With the completion of my country's BeiDou-3 satellite navigation system, satellite positioning, navigation, and timing technology has evolved from meeting military and political needs to widely serving all sectors of the national economy and social life. Overall, although the deployment of the BeiDou satellite navigation system started relatively late, its development has been very rapid. The BeiDou satellite navigation system can provide not only all types of open passive services found in other satellite navigation systems, but also authorized short message services and two-way active positioning, navigation, and timing services; the two-way active positioning, navigation, and timing services offer higher precision positioning and timing performance; active positioning and navigation accuracy can reach 10 meters, and active timing accuracy can reach 20 ns. The BeiDou satellite navigation system is an independent satellite navigation system developed and deployed independently by my country, free from the constraints of any other country. Besides its performance, application security is also a major advantage.

[0003] However, although BeiDou time synchronization has been applied in frequency synchronization networks, time synchronization networks, and wireless communication networks in the current communication field, its share is still very small compared with traditional GPS time synchronization. Its promotion and application in the communication field still has great prospects and development potential.

[0004] In the current context of domestic production, higher demands are placed on independent controllability at both the system and module levels. Currently, China's domestic technology for BeiDou timing and distribution on a fully domestically produced platform is still in its early stages and cannot meet the increasingly diverse and customized application needs.

[0005] Therefore, this invention proposes a dual-mode BeiDou timing and distribution device and method based on a domestically developed platform, which will provide stronger support for the development of the domestically developed BeiDou timing field and also conforms to the future trend of related technology development. A search revealed no published patent documents identical or similar to this invention. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and propose a dual-mode BeiDou timing and distribution device and method based on a domestic platform, which can realize dual-mode BeiDou timing and distribution.

[0007] The present invention solves its practical problem by adopting the following technical solution:

[0008] A dual-mode BeiDou timing and distribution device based on a domestic platform includes: a circuit board on which a BeiDou integrated module, an FPGA module, a microcontroller, multiple level conversion circuit modules, a level driving circuit module, and a DC / DC power conversion circuit module are arranged;

[0009] The input terminal of the FPGA module is connected to the microcontroller and is used to select and distribute the input and output channels of time code information, ephemeris information and second pulse signal. It also controls and implements functions such as self-testing, turning time code output on and off, turning second pulse output on and off, ephemeris query, and switching between self-time synchronization and external host time synchronization modes based on the signals sent by the microcontroller.

[0010] The microcontroller is used to parse the protocol of external instructions and send control signals to the FPGA module according to the protocol to assist the FPGA in realizing the control functions required by the protocol.

[0011] The circuit board has a 6UCPCI structure. The time code information, ephemeris information and second pulse signal are all input and output through the CPCI connector and its corresponding level conversion circuit module. The external commands are input to the microcontroller through the CPCI connector and the corresponding level conversion circuit module in sequence, and are then processed by the microcontroller and input to the FPGA module.

[0012] The output of the Beidou integrated module is connected to the FPGA module through a corresponding level conversion circuit module. It is used to collect Beidou-3 and GPS satellite parameters and send out time code information, ephemeris information and second pulse signal.

[0013] Furthermore, the level conversion circuit module includes a TTL level conversion 422 serial port level circuit and / or a TTL level conversion 232 serial port level circuit;

[0014] Moreover, the input terminal of the level driving circuit is connected to the FPGA module, and its output terminal is connected to the CPCI connector, which is used to convert the amplitude of the power pulse output by the FPGA module into a 28VIO level and then output it to the CPCI connector.

[0015] Furthermore, the input terminal of the DC / DC power conversion circuit module is connected to an external power source via a CPCI connector to receive an external 5V voltage and convert it into 3.3V and 1.8V voltages for powering the various chips in the circuit.

[0016] A dual-mode BeiDou timing and distribution method based on a domestically developed platform includes the following steps:

[0017] Step 1: The microcontroller parses the external instructions to determine whether to use the single-board self-time synchronization mode or the external host time synchronization mode for subsequent processing.

[0018] Step 2: If the single-board self-time synchronization mode is adopted, the onboard domestic Beidou integrated module provides time code information, ephemeris information and second pulse signal. After level conversion and control instruction processing by the microcontroller, the signal is input to the FPGA for processing. One channel of time code information or ephemeris information and one channel of second pulse are output. After level conversion circuit, the signal is output to CPCI connector. At the same time, 18 additional channels of second pulse are output. After level driving circuit, they are converted to 28V pulse amplitude and output to CPCI connector.

[0019] If the external host timing mode is used, the external host provides time code information, ephemeris information and second pulse signal through a 422 level serial port. After level conversion and control instruction processing by the microcontroller, the signal is input to the FPGA for processing. One channel of time code information or ephemeris information and one channel of second pulse are output. After level conversion circuit, they are output to CPCI connector. At the same time, 18 additional channels of second pulse are output. After level driving circuit, they are converted to 28V pulse amplitude and output to CPCI connector.

[0020] Advantages and beneficial effects of the present invention:

[0021] 1. This invention proposes a dual-mode BeiDou timing and distribution device based on a domestically developed platform. It can acquire parameters from up to 18 BeiDou-3 and GPS satellites and distribute time code information, ephemeris information, and second pulse signals on the domestic platform. It supports both board-based self-timing and external host timing modes, allowing switching between them as needed. Simultaneously, it can distribute the second pulse signal to 18 output channels to achieve time synchronization for multiple devices. Furthermore, this method supports external command control, enabling customizable functions such as self-testing, enabling / disabling time code output, enabling / disabling second pulse output, ephemeris query, and switching between board-based self-timing and external host timing modes by recognizing externally input commands.

[0022] 2. This invention uses FPGA and microcontroller for heterogeneous processing, which greatly enhances the flexibility and scalability of external control. The external instruction set can be expanded according to specific needs to achieve more customized functional requirements, while effectively improving the stability of the system. In addition, this invention uses domestically produced components, which meets the future trend of independent and controllable development. Attached Figure Description

[0023] Figure 1 This is a structural diagram of the dual-mode BeiDou timing and distribution device based on a domestically developed platform according to the present invention. Detailed Implementation

[0024] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings:

[0025] A dual-mode BeiDou timing and distribution device based on a domestic platform includes: a circuit board on which a BeiDou integrated module, an FPGA module, a microcontroller, multiple level conversion circuit modules, a level driving circuit module, and a DC / DC power conversion circuit module are arranged;

[0026] The input terminal of the FPGA module is connected to the microcontroller and is used to select and distribute the input and output channels of time code information, ephemeris information and second pulse signal. It also controls and implements various functions such as self-testing, turning time code output on and off, turning second pulse output on and off, ephemeris query, and switching between board self-time synchronization and external host time synchronization modes based on the signals sent by the microcontroller.

[0027] The microcontroller is used to parse the protocol of external instructions and send control signals to the FPGA module according to the protocol to assist the FPGA in realizing the control functions required by the protocol.

[0028] The circuit board has a 6UCPCI structure. The time code information, ephemeris information and second pulse signal are all input and output through the CPCI connector and its corresponding level conversion circuit module. The external commands are input to the microcontroller through the CPCI connector and the corresponding level conversion circuit module in sequence, and are then processed by the microcontroller and input to the FPGA module.

[0029] The output of the Beidou integrated module is connected to the FPGA module through a corresponding level conversion circuit module, which is used to collect Beidou-3 and GPS satellite parameters and send out time code information, ephemeris information and second pulse signal;

[0030] The level conversion circuit module includes a TTL level conversion 422 serial port level circuit and / or a TTL level conversion 232 serial port level circuit;

[0031] The input terminal of the level driving circuit is connected to the FPGA module, and its output terminal is connected to the CPCI connector. It is used to convert the amplitude of the power pulse output by the FPGA module into a 28VIO level and then output it to the CPCI connector.

[0032] The input terminal of the DC / DC power conversion circuit module is connected to an external power source via a CPCI connector to receive an external 5V voltage and convert it into 3.3V and 1.8V voltages for powering the chips in the circuit.

[0033] The composition and function of each module of the present invention will be further explained below:

[0034] In this embodiment, the dual-mode BeiDou timing and distribution device based on a domestic platform includes a circuit board, an FPGA program, and a microcontroller program.

[0035] The circuit board is based on a domestically produced Beidou integrated module, a domestically produced FPGA chip, and a domestically produced microcontroller chip. It is also equipped with signal level conversion circuit, level driving circuit, and DC / DC power conversion circuit to realize dual-mode Beidou time synchronization and distribution.

[0036] The FPGA program mainly implements the selection and distribution of input / output channels for time code information, ephemeris information, and second pulse signals. Based on the received microcontroller signals, it controls and implements various functions such as self-testing, enabling and disabling time code output, enabling and disabling second pulse output, ephemeris query, and switching between self-time synchronization and external host time synchronization modes. The microcontroller program mainly implements protocol parsing of external instructions and sends control signals to the FPGA according to the protocol to assist the FPGA in realizing the control functions required by the protocol.

[0037] In this embodiment, the circuit board has a 6UCPCI structure, and the time code information, ephemeris information, second pulse signal and external commands are all input and output through the CPCI connector;

[0038] In this embodiment, the domestically developed BeiDou integrated module is used to collect BeiDou-3 and GPS satellite parameters and transmit time code information, ephemeris information, and second pulse signals. The module supports BeiDou B1A, B3A, B3AE, B1C, B1I, and B3I, and has single-frequency and multi-system joint positioning functions. It supports narrowband interference resistance and high-dynamic applications, providing high-precision position, velocity, and time information with higher availability and integrity. It also features high-precision 1PPS time synchronization and supports multi-channel serial port output of time code information. The module mainly consists of three parts: a radio frequency (RF) unit, a baseband signal processing unit, and an interface unit. The downlink RNSS and S-frequency signals from the satellite are spatially lost to the multi-frequency antenna, amplified by the antenna's low-noise amplifier, and then enter the RF unit through the RF port. The multiplexer divides the signals into B2, B3, and B1 frequencies. After filtering by a power divider, the signals enter the integrated chip to complete B1, B2, and B3 filtering and intermediate frequency amplification before outputting an analog intermediate frequency. In addition, the RF unit generates the 80MHz sampling clock required by the system. The baseband signal processing unit samples the intermediate frequency analog signal using an AD converter to generate a digital signal. This digital signal is then searched, acquired, and demodulated in the positioning and calculation chip to complete the RNSS navigation, positioning, and timing calculations. The interface unit consists of a power supply and interface circuitry, providing power to each circuit module and implementing interface conversion functions.

[0039] In this embodiment, the FPGA chip is a domestically produced SMQ4VLX25 series chip from Shenzhen Guowei Electronics Co., Ltd.

[0040] In this embodiment, the domestically produced microcontroller is the GD32F103 series chip from Beijing GigaDevice Technologies Co., Ltd.

[0041] In this embodiment, the level conversion circuit includes a TTL level to 422 serial port level conversion circuit and a TTL level to 232 serial port level conversion circuit; used to realize communication between interfaces with different level. The 232 conversion chip used is the SM3232 chip from Shenzhen Guowei, which converts TTL levels to 232 serial port levels with a maximum transmission rate of 120kbps; the 422 conversion chip used is the SM490 chip from Shenzhen Guowei, which converts TTL levels to 422 serial port levels with a maximum transmission rate of 2.5Mbps.

[0042] In this embodiment, the level driving circuit includes two NPN transistors; the second pulse signal is input to the base of transistor 1, the emitter of transistor 1 is grounded, the collector of transistor 1 is connected to the base of transistor 2, the emitter of transistor 2 is grounded, and the collector of transistor 2 is connected to a 28V level and outputs it. When the second pulse is high or low, transistor 2 is in the on and off states, respectively, thereby converting the output pulse amplitude into a 28V IO level for output.

[0043] In this embodiment, external commands are input using 422 serial port level and protocol;

[0044] In this embodiment, the external host time synchronization is input using 422 serial port level and protocol;

[0045] In this embodiment, the FPGA program includes functions such as time code information forwarding, ephemeris information forwarding, second pulse multiplexing, and receiving and responding to control commands parsed by the microcontroller. The FPGA receives TTL-level serial port time code information, TTL-level serial port ephemeris information, and second pulse signals sent by the domestic Beidou integrated module or an external host. After level conversion and processing by the microcontroller's parsed control commands, the time code information and ephemeris information are multiplexed and output to the CPCI connector via the same 422-level serial port. The second pulse signal is forwarded into 19 channels, with one channel output to the CPCI connector via the 422-level serial port and the other 18 channels output to the level drive circuit for processing. Simultaneously, after processing by the microcontroller's parsed control commands, the FPGA can switch between self-time synchronization and external host time synchronization modes.

[0046] In this embodiment, the microcontroller program includes functions such as receiving external commands, parsing the commands according to protocols, and sending the parsed control commands to the FPGA. The microcontroller calls the serial port processing unit to receive external commands input through the 422 level serial port, parses the valid data bits of the message, and converts them into I / O signals for output to the FPGA. This allows the FPGA to control the corresponding function simply by controlling the high and low levels of the I / O signals. Simultaneously, the microcontroller also identifies the frame header, frame tail, frame length, and CRC checksum of the message, effectively avoiding crosstalk from coupled invalid signals and improving system stability.

[0047] The working process and working principle of this invention are as follows:

[0048] During operation, the microcontroller first parses external instructions to determine whether to use either the board's own time synchronization or the external host's time synchronization mode for subsequent processing.

[0049] If the single-board self-time synchronization mode is adopted, the onboard domestic Beidou integrated module provides time code information, ephemeris information, and second pulse signals. After level conversion and control command processing by the microcontroller, these signals are input to the FPGA for processing. The FPGA outputs one channel of time code information or ephemeris information and one channel of second pulse, which is then output to the CPCI connector after level conversion. Simultaneously, 18 additional second pulses are output, converted to 28V pulse amplitude by a level drive circuit before being output to the CPCI connector. The FPGA, by receiving control commands from the microcontroller, can perform various functions such as self-testing, enabling and disabling time code output, enabling and disabling second pulse output, ephemeris lookup, and switching between single-board self-time synchronization and external host time synchronization modes.

[0050] If an external host time synchronization mode is used, the external host provides time code information, ephemeris information, and second pulse signals via a 422 level serial port. After level conversion and processing by the microcontroller's control instructions, these signals are input to the FPGA for processing. The FPGA outputs one channel of time code information or ephemeris information and one channel of second pulse, which is then output to the CPCI connector after level conversion. Additionally, 18 second pulses are output, converted to 28V pulse amplitude by a level drive circuit before being output to the CPCI connector. The FPGA, by receiving the control instructions from the microcontroller, can perform various functions such as self-testing, enabling / disabling time code output, enabling / disabling second pulse output, ephemeris lookup, and switching between board-based self-time synchronization and external host time synchronization modes.

[0051] In summary, this invention proposes a dual-mode BeiDou timing and distribution method based on a domestically developed platform. This method can acquire parameters from up to 18 BeiDou-3 and GPS satellites and distribute time code information, ephemeris information, and second pulse signals on the domestic platform. It supports both board-based self-timing and external host timing modes, allowing switching between them as needed. Furthermore, it can distribute the second pulse signal to 18 output channels to achieve time synchronization for multiple devices. In addition, this method supports external command control, enabling customizable functions such as self-testing, enabling / disabling time code output, enabling / disabling second pulse output, ephemeris query, and switching between board-based self-timing and external host timing modes by recognizing externally input commands.

[0052] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0053] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0054] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0055] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

Claims

1. A dual-mode BeiDou timing and distribution device based on a domestically developed platform, characterized in that: include: The circuit board contains a Beidou integrated module, an FPGA module, a microcontroller, multiple level conversion circuit modules, a level drive circuit module, and a DC / DC power conversion circuit module. The input terminal of the FPGA module is connected to the microcontroller and is used to select and distribute the input and output channels of time code information, ephemeris information and second pulse signal. It also controls and implements functions such as self-testing, turning time code output on and off, turning second pulse output on and off, ephemeris query, and switching between self-time synchronization and external host time synchronization modes based on the signals sent by the microcontroller. The microcontroller is used to parse the protocol of external instructions and send control signals to the FPGA module according to the protocol to assist the FPGA in realizing the control functions required by the protocol. The circuit board has a 6UCPCI structure. The time code information, ephemeris information and second pulse signal are all input and output through the CPCI connector and its corresponding level conversion circuit module. The external commands are input to the microcontroller through the CPCI connector and the corresponding level conversion circuit module in sequence, and are then processed by the microcontroller and input to the FPGA module. The output of the Beidou integrated module is connected to the FPGA module through a corresponding level conversion circuit module. It is used to collect Beidou-3 and GPS satellite parameters and send out time code information, ephemeris information and second pulse signal.

2. The dual-mode BeiDou timing and distribution device based on a domestically developed platform according to claim 1, characterized in that: The level conversion circuit module includes a TTL level conversion 422 serial port level circuit and / or a TTL level conversion 232 serial port level circuit.

3. The dual-mode BeiDou timing and distribution device based on a domestically developed platform according to claim 1, characterized in that: The input terminal of the level driving circuit is connected to the FPGA module, and its output terminal is connected to the CPCI connector. It is used to convert the amplitude of the power pulse output by the FPGA module into a 28VIO level and then output it to the CPCI connector.

4. The dual-mode BeiDou timing and distribution device based on a domestically developed platform according to claim 1, characterized in that: The input terminal of the DC / DC power conversion circuit module is connected to an external power source via a CPCI connector to receive an external 5V voltage and convert it into 3.3V and 1.8V voltages for powering the chips in the circuit.

5. A dual-mode BeiDou timing and distribution method based on a domestically developed platform, characterized in that: Includes the following steps: Step 1: The microcontroller parses the external instructions to determine whether to use the single-board self-time synchronization mode or the external host time synchronization mode for subsequent processing. Step 2: If the single-board self-time synchronization mode is adopted, the onboard domestic Beidou integrated module provides time code information, ephemeris information and second pulse signal. After level conversion and control instruction processing by the microcontroller, the signal is input to the FPGA for processing. One channel of time code information or ephemeris information and one channel of second pulse are output. After level conversion circuit, the signal is output to CPCI connector. At the same time, 18 additional channels of second pulse are output. After level driving circuit, they are converted to 28V pulse amplitude and output to CPCI connector. If the external host timing mode is used, the external host provides time code information, ephemeris information and second pulse signal through a 422 level serial port. After level conversion and control instruction processing by the microcontroller, the signal is input to the FPGA for processing. One channel of time code information or ephemeris information and one channel of second pulse are output. After level conversion circuit, they are output to CPCI connector. At the same time, 18 additional channels of second pulse are output. After level driving circuit, they are converted to 28V pulse amplitude and output to CPCI connector.

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