Breakpoint triggering method for FPGA prototype verification
By introducing a breakpoint triggering system into FPGA prototype verification and using real-time signal matching to generate trigger conditions, the problem of limited trigger conditions in embedded logic analyzers is solved, enabling rapid location of internal FPGA signals and improving verification efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 无锡亚科鸿禹电子有限公司
- Filing Date
- 2022-12-13
- Publication Date
- 2026-08-04
AI Technical Summary
In existing FPGA prototype verification, when using an embedded logic analyzer to observe internal signals, the triggering conditions are limited and complex, making it difficult to locate erroneous signals and resulting in low efficiency.
A breakpoint triggering system based on FPGA prototype verification is provided, including prototype verification debugging software, trigger condition generation module, trigger module and sampling module. By acquiring the matching of the measured signal and the preset signal in real time, the system generates and adjusts the trigger condition signal to achieve efficient breakpoint triggering.
Quickly locate target signal points inside the FPGA, reduce prototype verification and debugging time, improve verification efficiency, and is applicable to all FPGA debugging and verification tools.
Smart Images
Figure CN115934196B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of FPGA technology, and in particular to a breakpoint triggering method for FPGA prototype verification. Background Technology
[0002] Prototype verification is a verification method for SoCs based on FPGAs, typically following front-end RTL design and RTL simulation. Both FPGA and ASIC front-end code are developed using Verilog HDL, so theoretically, ASIC code can run on the FPGA platform. This verification method aims to confirm the correctness of chip functionality as much as possible before tape-out. Its purpose is to reproduce the chip's real-world usage scenarios as closely as possible before tape-out, achieving thorough verification of chip functionality and ensuring the reliability and stability of functional modules.
[0003] In related technologies, during the prototype verification process, after the user downloads the design to the FPGA and starts running it, various errors inevitably occur. At this point, it is necessary to observe the internal signals of the FPGA to locate the errors. In addition, most users utilize the embedded logic analyzer provided by the FPGA manufacturer to observe the internal signals of the FPGA.
[0004] Using an FPGA-embedded logic analyzer to observe internal FPGA signals has many drawbacks: taking Xilinx's ILA (integrated logic analyzer) as an example, the basic trigger conditions of ILA can only be set to four types: "AND", "NAND", "OR", and "NOR". This is very disadvantageous for quickly locating internal FPGA error signals. Although ILA's advanced flip-flop modes can implement some of the complex trigger conditions described in this article, it requires users to write flip-flop state machine code, which is not convenient for chip debugging. Summary of the Invention
[0005] This application provides a breakpoint triggering system and triggering method based on FPGA prototype verification, which solves the problem of low efficiency in FPGA prototype verification.
[0006] On the one hand, a breakpoint triggering system based on FPGA prototype verification is provided, including prototype verification debugging software, trigger condition generation module, trigger module, sampling module and chip under test;
[0007] The prototype verification and debugging software is used to send trigger information to the trigger condition generation module according to a preset signal, and to send trigger condition codes to the trigger module; wherein, the trigger information includes a preset signal and a target number of trigger condition signals, and the trigger condition codes are generated based on the operation logic of the trigger information;
[0008] The trigger condition generation module acquires the test signal output by the internal logic of the chip under test in real time, and updates the trigger condition signal according to the matching result of the test signal and the preset signal.
[0009] The triggering module is used to determine the target trigger signal output from the triggering condition code according to the triggering condition signal; the sampling module receives the target trigger signal in real time, and triggers the breakpoint sampling of the chip under test according to the level signal value of the target trigger signal, so that the prototype verification and debugging software can analyze the sampling signal triggered by the breakpoint and locate the target signal point of the logic under test.
[0010] The signal under test is output by the chip under test according to its internal test logic; the number of trigger condition signals is the same as the number of test types of the signal under test, and they correspond one-to-one.
[0011] Specifically, the measured signal and the preset signal include n sets of level signals of the measured type, each set of the measured type consists of several level signals, and the n trigger condition signals output by the trigger condition generation module correspond to the level signals of the n sets of the measured type in sequence.
[0012] The trigger condition generation module takes the received test signal and the n sets of test type level signals contained in the preset signal as inputs, compares the same test type level signals, and outputs the corresponding trigger condition signal.
[0013] Specifically, when the level signal of the i-th group of the measured type of the measured signal and the level signal of the i-th group of the preset type of the preset signal satisfy a preset relationship, the trigger condition generation module adjusts the i-th trigger condition signal to the target signal value and sends it to the trigger module; the preset relationship includes "equal to", "not equal to", "less than", "less than or equal to", "greater than", and "greater than or equal to".
[0014] Specifically, the triggering module selects the target triggering signal from the triggering condition codes based on a combination of n triggering condition signals.
[0015] Specifically, the trigger condition code includes 2 n There are n level signals, and the value of each level signal is generated according to n trigger condition codes and their logical operations; the trigger module includes a multiplexer, with 2 n The input is a path level signal, and the output is selected based on a binary number composed of n trigger condition signals.
[0016] Specifically, when all n level signals of the n trigger condition codes are adjusted to the target signal value, the target trigger signal output by the trigger module is high level, triggering the breakpoint and acquiring the level signal of the logic under test through the sampling module, which is then used by the prototype verification and debugging software to analyze the sampled signal;
[0017] When the target trigger signal is low, the breakpoint is not triggered.
[0018] Specifically, logical operations include at least the "AND", "OR", "NOT", "NAND", "NOR", "XOR", and "XNOR" operations.
[0019] On the other hand, a breakpoint triggering method based on FPGA prototyping is provided, which is applied to a breakpoint triggering system based on FPGA prototyping, including:
[0020] S1, a preset signal is determined based on the test type of the chip under test, and the trigger information and trigger condition code acting on the trigger module are determined according to the number of test types contained in the preset signal; the trigger information includes the preset signal and a target number of trigger condition signals, and the trigger condition code is generated based on the operation logic of the trigger information;
[0021] S2, the triggering module receives the trigger condition code sent by the prototype verification and debugging software and the trigger condition signal sent by the trigger condition generation module, determines the target trigger signal from the trigger condition code according to the combination of the trigger condition signals and outputs it;
[0022] S3, the trigger condition generation module acquires the test signal output by the logic under test in real time, and matches the test signal with the preset signal sent by the prototype verification and debugging software;
[0023] S4, when the level signal of the i-th group of the tested type of the tested signal and the level signal of the i-th group of the preset type of the preset signal satisfy the preset relationship, the level signal of the i-th trigger condition code is adjusted to the target signal value and sent to the trigger module;
[0024] S5, when the n sets of electrical signals of the logic under test are consistent with the n sets of electrical signals of the preset signal, the trigger condition generation module adjusts all the trigger condition signals to the target level signal, the trigger module outputs a high-level target signal value, triggers the breakpoint, and collects the level signal of the logic under test through the sampling module.
[0025] The beneficial effects of the technical solution provided in this application include at least the following: Based on the prototype verification and debugging software, the operational logic and corresponding trigger condition codes are set according to the type and quantity of the tested signal, and the trigger condition codes are associated with the tested type. The added trigger module adjusts the trigger condition signal in real time according to the tested signal and the preset signal, and selects the trigger condition code according to the signal combination, using it as the target trigger signal. In this way, when the sampling module detects a high-level target trigger signal, it triggers breakpoint sampling, and sends the sampled signal output by the tested logic to the prototype verification and debugging software for analysis. Compared with the traditional method of observing the internal signals of an FPGA using an embedded logic analyzer, this trigger condition implementation scheme can conveniently and quickly locate the signal observation point desired by the user, greatly reducing the time required in the prototype verification and debugging stage, and is applicable to all FPGA debugging and prototype verification tools. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of a breakpoint triggering system based on FPGA prototype verification.
[0027] Figure 2 This is a schematic diagram of the trigger module in a breakpoint triggering system;
[0028] Figure 3 A flowchart of a breakpoint triggering method for FPGA prototype verification. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.
[0030] In this article, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0031] Considering the numerous shortcomings of using an FPGA-embedded logic analyzer to observe internal FPGA signals, this application provides a breakpoint triggering system based on FPGA prototype verification, specifically as follows: Figure 1 As shown.
[0032] The system includes prototype verification and debugging software, a trigger condition generation module, a trigger module, a sampling module, and a chip under test (DUT). The DUT is an FPGA chip with built-in logic under test.
[0033] The prototype verification and debugging software is the software debugging component, connected to the trigger module, trigger condition generation module, and sampling module. Its main function is to send trigger information to the trigger condition generation module based on preset signals, and to send trigger condition codes to the trigger module based on the signal under test. The trigger information includes preset signals and a target number of trigger condition signals, used by the trigger condition generation module to generate trigger condition signals that act on the trigger module. In this solution, the trigger condition signals are set to low level by default. The trigger condition codes are composed of combinations of trigger condition signals and logic signals, aiming to output a target trigger signal to the trigger module and, under appropriate conditions, implement a breakpoint triggering mechanism to obtain the sampled signal.
[0034] The trigger information specifies the number of trigger condition signals, which is the type of signal under test. In actual testing, the preset signals can include several sets of level signals, specifically address level signals, data level signals, and check signals, etc. The number of bits for each type of level signal is determined based on the actual situation; for example, address bits and data bits may consist of 16-bit or 32-bit level signals. The specific number of test types depends on the actual chip type and debugging content; this embodiment does not limit this. After setting the preset signals, the trigger condition generation module needs to collect the test signals output by the logic under test, match the two, and determine whether to update the trigger condition signals.
[0035] The tested signal and the preset signal include n sets of level signals of the tested types to be detected, each set of tested types consisting of several level signals. The preset signal is a target trigger signal designed to detect the chip, under which breakpoint triggering is performed. The number of trigger condition signals output by the trigger condition generation module is the number of tested types contained in the tested signal (both n). The design idea of this scheme is: the trigger condition generation module takes the received tested signal and the n sets of level signals of the tested types contained in the preset signal as inputs, and compares the level signals of the same tested type. The comparison output is the corresponding trigger condition code. That is, when the level signal of the i-th tested type of the tested signal is the same as the level signal of the i-th preset type of the preset signal, the trigger condition generation module adjusts the i-th trigger condition signal to the target signal value and sends it to the trigger module.
[0036] In one possible implementation, the trigger condition signal is represented as ABCD, where level A corresponds to the fourth type of the measured signal, level B corresponds to the third type, level C corresponds to the second type, and level D corresponds to the first type. When the fourth type level signal matches a preset signal value, level A is pulled high (high level is the target level signal). The adjusted trigger condition signal is then sent to the trigger module.
[0037] In one possible implementation, the trigger condition generation module can have a built-in comparator to extract and compare the level signals of the measured signal and preset signals corresponding to the measured type. If they match, a high level is output, which is the trigger condition signal corresponding to the measured type. For example, if the preset signal for the data signal is 11111111 and the preset signal for the address signal is 11110000, then whenever the level signal corresponding to the measured signal is detected to be the same as the preset signal, the type matching is successful.
[0038] The trigger module internally uses a multiplexer that takes the trigger condition code as the level signal input. It selects the path based on the trigger condition signal, and the output target trigger signal is a single-level signal, either high (1) or low (0). The high level signal is the breakpoint trigger signal, used to trigger the breakpoint and locate the target signal point.
[0039] The selection path of the multiplexer is determined by the decimal number of the combination of n trigger condition signals. For example, if the ABCD signal is represented as 0000, it means that the first path of the multiplexer is selected, and 1010 means the eleventh path. The trigger module uses the first trigger condition code or the eleventh trigger condition code as the target trigger signal.
[0040] It should be noted that the generation and number of trigger condition codes are determined by the operational logic of the prototype verification and debugging software, and this operational logic needs to be determined based on the user-defined prediction signals. For example, the trigger condition signals may be designed with AND, OR, NOT, NAND, NOR, XOR, XNOR, and other complex logical combinations. The trigger condition codes are then determined based on the n trigger condition signals and the designed operational logic. Figure 2 The diagram shows the structure of the trigger module, where Breakcode[i] represents the input signals of the trigger condition code, a, b, and c represent the input operation logic, and Trigger pulse is the output trigger signal.
[0041] For example, if the trigger condition signal is ABCD, and the operation logic is A&&B||C&&D, then the trigger condition code is obtained from the truth table constructed by the ABCD operation. That is, the trigger condition code contains 2... n There are n level signals, and the value of each level signal is generated based on n trigger condition codes and their logical operations. See Table 1 below.
[0042] Table 1 Truth Table of A&&B||C&&D
[0043] 1 0 0 0 0 0 2 0 0 0 1 0 3 0 0 1 0 0 4 0 0 1 1 1 5 0 1 0 0 0 6 0 1 0 1 0 7 0 1 1 0 0 8 0 1 1 1 1 9 1 0 0 0 0 10 1 0 0 1 0 11 1 0 1 0 0 12 1 0 1 1 1 13 1 1 0 0 1 14 1 1 0 1 1 15 1 1 1 0 1 16 1 1 1 1 1
[0044] Combination Figure 2The schematic diagram of the trigger module given in the document assumes that the default trigger condition code ABCD is 0000, in which case the output trigger signal is 0 and no breakpoint is triggered. The specific operation logic is determined according to the test item and detection type, and this embodiment does not limit it. When all n level signals of the n trigger condition codes are adjusted to the target signal value, the target trigger signal output by the trigger module is high level, triggering the breakpoint and collecting the level signal of the logic under test through the sampling module for analysis of the sampled signal by the prototype verification and debugging software. When the target trigger signal is low level, no breakpoint is triggered. It should be noted that there are multiple cases where the trigger pulse is high level in this truth table. This is defined according to the specific design needs. Special operators can also be designed to change the signal value of the operation result, and the target level value can also be set to low level or any high or low level according to actual needs. This solution does not limit it. When the preset signal of the tested signal is qualified and there is a matching item, after changing a certain level signal value, the updated n trigger condition decoders are sent to the trigger module again for selection. The sampling module will start the sampling model and perform analysis once the first output target trigger signal is high.
[0045] Figure 3 This is a flowchart of a breakpoint triggering method based on FPGA prototype verification provided in an embodiment of this application, applied to... Figure 1 The breakpoint triggering system based on FPGA prototype verification includes the following steps:
[0046] S1. Determine the preset signal based on the test type of the chip under test, and determine the trigger information and trigger condition code that act on the trigger module according to the number of test types contained in the preset signal.
[0047] The initialization phase primarily determines the composition of the preset and measured signals based on the selected test type. The voltage level width and corresponding target voltage level for each test type are determined according to the actual situation. Then, the operational logic and corresponding triggering information are determined based on the number of test types required.
[0048] Compared to traditional state machine programming methods, this solution only requires users to set the number of trigger conditions. Then, using these pre-defined trigger conditions, users can perform arbitrarily complex logical operations to generate new trigger conditions, such as (A&&B)||(!A&&C)||(C&&!D)&&(A&&D), etc. The prototype verification and debugging software then processes these expressions to generate the default trigger condition codes required for triggering and sends them to... Figure 2 In the structure.
[0049] S2, the trigger module receives the trigger condition code sent by the prototype verification and debugging software and the trigger condition signal sent by the trigger condition generation module, determines the target trigger signal from the trigger condition code based on the combination of the trigger condition signals and outputs it.
[0050] S3, the trigger condition generation module acquires the test signal output by the logic under test in real time, and matches the test signal with the preset signal sent by the prototype verification and debugging software.
[0051] S4. When the level signal of the i-th group of the measured type of the measured signal and the level signal of the i-th group of the preset type of the preset signal satisfy the preset relationship, the level signal of the i-th trigger condition code is adjusted to the target signal value and sent to the trigger module.
[0052] The preset relationships include "equal to", "not equal to", "less than", "less than or equal to", "greater than", and "greater than or equal to". For example, the acquired test signal will be matched with the preset signal according to the test type. As long as the corresponding level signal meets the preset relationship, the corresponding level value will be set as the target signal value by pulling it up or down. At the same time, the updated trigger condition signal will be sent to the trigger module to trigger the breakpoint.
[0053] In some specific embodiments, the comparator built into this module can be configured with multiple logical operations, such as satisfying "M==N", "M!=N", "M" and "M" with a preset signal (N). <N”、“M<=N”、“M> When =N", the corresponding level value is pulled high or low. The specific comparison logic operation is set according to the actual situation.
[0054] S5, when the n sets of electrical signals of the logic under test are consistent with the n sets of electrical signals of the preset signal, the prototype verification and debugging software will adjust all n level signals of the trigger condition code to the target level signal. The trigger module will output a high-level trigger signal through the set operation logic to trigger the breakpoint and locate the target signal point.
[0055] In summary, based on the prototype verification and debugging software, the operational logic and corresponding trigger condition codes are set according to the type and quantity of the tested signals, and the trigger condition codes are associated with the tested types. The added trigger condition module adjusts the trigger condition signals in real time according to the tested signals and preset signals, and selects the trigger condition codes based on signal combinations, using them as the target trigger signals. This solution supports arbitrarily complex logical operations to form complex logical expressions. After all tested types are matched, the target signal point that the user wants to observe inside the FPGA is located based on the trigger breakpoint signal of the trigger signal. Compared with the traditional method of observing signals inside the FPGA using an embedded logic analyzer, this trigger condition implementation scheme can conveniently and quickly locate the target signal point, greatly reducing the time required in the prototype verification and debugging stage, and is applicable to all FPGA debugging and prototype verification tools.
[0056] The preferred embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above. The devices and structures not described in detail should be understood as being implemented in a conventional manner in the art. Any person skilled in the art can make many possible changes and modifications, or equivalent changes to equivalent embodiments without departing from the technical solution of the present invention. This does not affect the substantive content of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.
Claims
1. A breakpoint triggering system based on FPGA prototype verification, characterized in that, It includes prototype verification and debugging software, trigger condition generation module, trigger module, sampling module, and chip under test; The prototype verification and debugging software is used to send trigger information to the trigger condition generation module according to a preset signal, and to send trigger condition codes to the trigger module; wherein, the trigger information includes a preset signal and a target number of trigger condition signals, and the trigger condition codes are generated based on the operation logic of the trigger information; The trigger condition generation module acquires the test signal output by the internal logic of the chip under test in real time, and updates the trigger condition signal according to the matching result of the test signal and the preset signal. The triggering module is used to determine and output the target trigger signal from the triggering condition code according to the triggering condition signal; the sampling module receives the target trigger signal in real time, and triggers the breakpoint sampling of the chip under test according to the level signal value of the target trigger signal, so that the prototype verification and debugging software can analyze the sampling signal triggered by the breakpoint and locate the target signal point of the logic under test. The signal under test is output by the chip under test according to its internal test logic; the number of trigger condition signals is the same as the number of test types of the signal under test, and they correspond one-to-one.
2. The breakpoint triggering system according to claim 1, characterized in that, The measured signal and the preset signal include n sets of level signals of the measured type. Each set of measured type consists of several level signals. The n trigger condition signals output by the trigger condition generation module correspond to the level signals of the n sets of measured types in sequence. The trigger condition generation module takes the received test signal and the n sets of test type level signals contained in the preset signal as inputs, compares the same test type level signals, and outputs the corresponding trigger condition signal.
3. The breakpoint triggering system according to claim 2, characterized in that, When the level signal of the i-th group of the measured type of the measured signal satisfies the preset relationship with the level signal of the i-th group of the preset type of the preset signal, the trigger condition generation module adjusts the i-th trigger condition signal to the target signal value and sends it to the trigger module; the preset relationship includes "equal to", "not equal to", "less than", "less than or equal to", "greater than", and "greater than or equal to".
4. The breakpoint triggering system according to claim 3, characterized in that, The triggering module selects the target trigger signal from the triggering condition codes based on a combination of n triggering condition signals.
5. The breakpoint triggering system according to claim 4, characterized in that, The trigger condition code includes There are n level signals, and the value of each level signal is generated according to the n trigger condition codes and their operation logic; The triggering module includes a multiplexer to... The input is a level signal, and the target trigger signal is selected and output according to a binary number composed of n trigger condition signals.
6. The breakpoint triggering system according to claim 5, characterized in that, When all n trigger condition signals are adjusted to the target signal value, the target trigger signal output by the trigger module is high level, triggering the breakpoint and acquiring the level signal of the logic under test through the sampling module, which is used by the prototype verification and debugging software to analyze the sampled signal; When the target trigger signal is low, the breakpoint is not triggered.
7. The breakpoint triggering system according to any one of claims 1-6, characterized in that, The operational logic includes at least the "AND", "OR", "NOT", "NAND", "NOR", "XOR", and "XNOR" operations.
8. A breakpoint triggering method based on FPGA prototyping, applied to the breakpoint triggering system based on FPGA prototyping as described in any one of claims 1-7, characterized in that, include: S1, determine a preset signal based on the test type of the chip under test, and determine the trigger information and trigger condition code acting on the trigger module according to the number of test types contained in the preset signal. The triggering information includes a preset signal and a target number of triggering condition signals, and the triggering condition code is generated based on the computational logic of the triggering information; S2, the triggering module receives the trigger condition code sent by the prototype verification and debugging software and the trigger condition signal sent by the trigger condition generation module, determines the target trigger signal from the trigger condition code according to the combination of the trigger condition signals and outputs it; S3, the trigger condition generation module acquires the test signal output by the logic under test in real time, and matches the test signal with the preset signal sent by the prototype verification and debugging software; S4, when the level signal of the i-th group of the tested type of the tested signal and the level signal of the i-th group of the preset type of the preset signal satisfy the preset relationship, the i-th trigger condition signal is adjusted to the target signal value and sent to the trigger module; S5, when the n sets of electrical signals of the logic under test are consistent with the n sets of electrical signals of the preset signal, the trigger condition generation module adjusts all the trigger condition signals to the target level signal, the trigger module outputs a high-level target signal value, triggers the breakpoint, and collects the level signal of the logic under test through the sampling module.