A method for accelerating database hash operation based on ARM platform
By optimizing database hash operations on the ARM platform and utilizing SIMD technology and a custom conversion library, the x86 AVX and SSE instruction sets are converted to the ARM Neon instruction set, solving the problem of low hash operation efficiency on the domestic ARM platform and achieving more efficient hash query and table creation performance.
Patent Information
- Application Number
- CN202211660181.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-23
- Publication Date
- 2026-01-02
- Estimated Expiration
- 2042-12-23
AI Technical Summary
Traditional relational databases are slow in querying scenarios with large data volumes and high real-time requirements. Existing optimization solutions mainly target the query optimizer and storage engine's Compilation and SIMD technologies, but their effectiveness is limited. In particular, hash operations are inefficient on domestic ARM platforms.
This paper proposes an optimization method for hash operations based on the ARM platform. The optimization algorithm for database hashing is achieved by implementing the AVX and SSE instruction sets of x86. The algorithm is then converted to the Neon instruction set of ARM using a custom conversion library. The algorithm is vectorized using SIMD technology, including predefined bitmasks and basic operations, loop processing logic, and the AvxToNeon framework is extended to implement the conversion module ATN.
It improves the execution speed of database hash operations on the ARM platform, reduces the number of CPU instruction calls, and enhances the efficiency of hash queries and hash table creation.
Smart Images
Figure CN115934725B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of computer database and basic algorithm transplantation, and particularly relates to a design method for accelerating database hash operation based on an ARM platform. BACKGROUND
[0002] With the continuous progress of the development level of the Internet, the data scale is increasingly large, and various enterprises begin to use emerging technologies such as big data and artificial intelligence to continuously improve the modernization level of governance and decision-making. Traditional relational databases mostly use row storage data, and in order to balance ACID, the query speed is not too advantageous, and it is more suitable for real-time update and frequent deletion scenarios. However, the rapid growth of data and the high requirement for real-time data analysis have led to the fact that traditional relational databases no longer meet the use requirements. At present, databases based on online analytical processing (OLAP) technology are more suitable for read-write scenarios because they naturally use column storage.
[0003] Databases using column storage are more commonly used in scenarios requiring high data query speed, such as real-time data analysis. However, as business scenarios become more complex and the requirement for real-time database query is higher, various optimization schemes have emerged.
[0004] The database query process can be roughly divided into the following steps: SQL connector, SQL parser, query optimizer, storage engine, and return query result. The optimization schemes currently emerging in the industry mainly optimize the query optimizer and the execution engine. The optimization of the query optimizer mainly formulates a more reasonable query path for the query. The optimization of the storage engine can be divided into two parts: one direction is the Compilation optimization, that is, data-centered assembly generation; the other direction is the vectorization scheme based on SIMD technology. In general, both have their advantages and disadvantages, the former has less materialization generation, so it is more suitable for compute-intensive scenarios; the latter performs better when accessing large hash tables for aggregation queries, so it is more suitable for memory-intensive scenarios.
[0005] SIMD (Single Instruction, Multiple Data) technology is a parallel computing technology in computer science that allows a processor to execute multiple data operations at once. SIMD technology can improve the overall performance of a computer because it allows each individual processor core to handle multiple data simultaneously. Currently, many processors support SIMD technology, including Intel's AVX instruction set and Apple's Neon instruction set.
[0006] At present, the domestic platform mainly takes ARM platform as the main body. Hash operation is an important part of database connection operator. The vector optimization of database hash operation by using SIMD technology can improve the execution speed of database connection operator on domestic ARM platform. SUMMARY
[0007] The purpose of the present application is to design a method for accelerating database hash operation based on ARM platform. The present application provides a method for obtaining the final database hash operation based on ARM Neon instruction set optimization by implementing X86 based on AVX instruction set and SSE instruction set optimization database hash algorithm, and then converting through self-defined conversion library. The steps of the described method are as follows Figure 1 , comprising:
[0008] 1. The implementation method of hash query and hash table building based on SIMD technology
[0009] The linear probing method is selected as the basic algorithm for hash query and hash table building. Linear probing is a common strategy adopted by computer programs to solve hash table conflicts. On this basis, the hash query and hash table building method based on SIMD technology is designed and implemented.
[0010] The SIMD implementation of the hash query and hash table building method of the present application is based on the AVX and SSE instruction sets of the X86 system. In order to construct the original scalar instruction into a vector instruction, the present application needs to be appropriately processed in the algorithm. The entire algorithm includes the following contents:
[0011] (1) Predefine the number of bit mask channels and bit masks. Before the entire algorithm starts, the appropriate vector channel size, i.e. the number of vector channels, needs to be selected in advance and set to W, which is 256 in the present application. The number of vector channels is the number of data that can be processed at a time by single instruction multiple data instructions. The bit mask is a vector with W channels, and its value can only be true or false.
[0012] (2) Predefine the basic operation. The operations allowed to be used in the database hash algorithm are abstracted as 6 basic operations. Among the 6 basic operations, two important concepts, data source and vector, are involved. The data source can be data stored on the hard disk or in the memory, while the vector is data stored in the memory. In general, the process of copying data from the data source to the vector is called loading, and the process of copying data from the vector to the data source is called storage. The vector can be processed by single instruction multiple data stream through direct calling of SIMD related instruction set functions. The 6 basic operations include:
[0013] ● Vector load (vector load): given data source and data source at any position, the calculation result is the target vector.
[0014] Specific process is described as W data from this data source this position is sequentially loaded to the target vector.
[0015] • Vector store: Given data source arbitrary position and data vector, the result is the target data source. The specific process is described as copying the W data of the data vector to the W data from the target data source this position, and covering the original data.
[0016] • Gather: Given index vector, bit mask and data source, the calculation result is the target vector. The initial value of the index vector is the index subscript of the corresponding data of the data source. The specific process is described as follows: for the kth channel, if the kth channel of the bit mask is false, do not operate; if the kth channel of the bit mask is true, read the value of the kth channel of the index vector, denoted as index, and find the value of the position with subscript index in the data source, and save it to the kth channel of the target vector.
[0017] • Scatter: Given index vector, data vector and bit mask, the calculation result is the target data source. The specific process is described as follows: for the kth channel, if the kth channel of the bit mask is false, do not operate;
[0018] If the kth channel of the bit mask is true, read the value of the kth channel of the index vector, denoted as index, and then fill the kth data value of the data vector into the position with subscript index of the target data source.
[0019] • Selective load: Given data source arbitrary position i, data source and bit mask, the calculation result is the target vector. The specific process is described as follows: for the kth channel, if the kth channel of the bit mask is false, do not operate; if the kth channel of the bit mask is true, save the data of the i+k-1th position of the data source to the kth channel of the target vector.
[0020] • Selective store: Given data source arbitrary position i, data vector and bit mask, the calculation result is the target data source. The specific process is described as follows: for the kth channel, if the kth channel of the bit mask is false, do not operate; if the kth channel of the bit mask is true, store the data at the kth channel of the data vector to the i+k-1th position of the data source.
[0021] (3) Loop processing logic. The algorithm generally adopts the way of loop processing for hash query and hash table building. The summary logic is as follows:
[0022] • First, by using vector load operation, the key group and value group of the input group are stored into the respective temporary target vector by processing the key group, value group and vector bitmask of the input table.
[0023] • Then, by integrating the above results, the hash table size and the given hash function, the hash vector with channel size W can be obtained.
[0024] • Finally, by using 6 basic operations respectively, the hash query and hash table building process can be performed by looking up the corresponding hash table position of the hash vector.
[0025] In addition, it should be noted that when performing hash query, if the corresponding position of the hash table is found to have an element and is equal to the matched element, the corresponding record needs to be performed. However, this does not end here. Only when the corresponding position of the hash table is found to be empty, the search of this element ends.
[0026] The advantages and beneficial effects of the present vector algorithm are: by calling AVX instruction set and SSE instruction set, the scalar algorithm processing is changed to vector algorithm, so that the CPU processes data in vector parallel mode, the number of CPU instructions called in the execution process is reduced, and the execution speed of hash query and hash table building is improved.
[0027] 2. Custom conversion library and conversion process
[0028] The SIMD instruction set of X86 generally uses AVX and SSE instruction sets, while the SIMD instruction set of ARM generally uses Neon instruction set.
[0029] Currently, Huawei has implemented a framework AvxToNeon for converting AVX instruction set to ARM platform, which has implemented the conversion of part of the instructions. However, when designing the SIMD implementation method of hash query and hash table building based on AVX version, the AVX instructions used are more complex. AvxToNeon still cannot meet the use requirements of the present application. Therefore, on this basis, the present application extends the framework of AvxToNeon and customizes a new conversion module ATN.
[0030] From a more fine-grained perspective, the part involved in the AvxToNeon framework is mainly the function conversion of AVX and AVX512 instruction sets to Neon instruction set. The ATN module is still developed based on the AvxToNeon framework, which mainly includes the function conversion of part of AVX instruction set and part of SSE instruction set to Neon instruction set.
[0031] The ATN mainly includes the following contents:
[0032] (1)Self-defined implementation function. The main implementation manner of the ATN module is to regard the AVX and SSE instruction set functions as self-defined inline functions in the ARM environment, and then use the instruction set functions of Neon to implement the corresponding functions. Specifically, the __m128i_mm_and_si128() function is an X86 AVX instruction set function, which is not available in ARM. In the present application, this function is regarded as a self-defined inline function in ARM, and the vandq_s32() function of Neon instruction set is used to construct and implement it. Finally, the __m128i_mm_and_si128() function achieves the same effect on X86 and ARM.
[0033] (2) Unified packaging. In the previous step, the implementation of part of the AVX instruction set and part of the SSE instruction set on the ARM platform is provided. Therefore, all the implementation functions need to be packaged into a header file to provide a unified calling interface for the program calling the ATN module.
[0034] The conversion process of the present application is relatively simple, mainly including the following contents:
[0035] (1) Calling process. The above-mentioned vector program normally running on X86 is imported into the ARM platform, and the calling path of the header file is changed through the header file calling mode. That is, #include "atn.h" is used in the program.
[0036] (2) Compilation mode. Further, when compiling the vector hash query and hash table building algorithm on the ARM platform, the appropriate compilation parameters are used for compilation. If the source file is hash.c and the target file is target, the ARM platform compilation instruction is as follows:
[0037]
[0038] The advantages and beneficial effects of the present self-defined conversion library and conversion process are: the range of conversion functions of the original framework library is enriched and improved, so that the conversion function library is expanded from the AVX instruction set to the SSE instruction set; through the simple import process, the X86 SIMD vector code can be quickly run on ARM after a short conversion, reducing the coding amount of the developer. BRIEF DESCRIPTION OF DRAWINGS
[0039] Figure 1 : Specific steps of hash operation based on SIMD and transplantation to ARM platform
[0040] Figure 2 : Schematic diagram of scalar and SIMD operation comparison DETAILED DESCRIPTION
[0041] The hardware environment of the application is an X86 host and an ARM host, the CPU of the X86 host is Intel(R) Core(TM) i5-4590, the memory is 8GB RAM, the 64-bit operating system, and the SIMD instruction set is AVX and SSE. The CPU of the ARM host is HUAWEI, Kunpeng 920, the 64-bit operating system, and the SIMD instruction set is Neon.
[0042] The software environment of the application is that the X86 takes Ubuntu 20.04 as a platform, the ARM takes Kylinv2101.ky10.aarch64 as a platform, and both use C language development. The GCC version of the X86 is 9.4.0. The GCC version of the ARM is 7.3.0.
[0043] In order to make the purpose, technical solution of the application more clear and clear, the application will be further described in detail below combined with the drawings. It should be understood that the specific embodiments described herein are only used to explain the application and do not limit the protection scope of the application.
[0044] The implementation process of the application mainly includes three parts, the first part is to realize the hash query method based on SIMD technology, the second part is to realize the hash table building method based on SIMD technology, and the third part is to realize the custom conversion library and conversion process.
[0045] 1. Realize the hash query method based on SIMD technology
[0046] The hash query based on SIMD technology involved in this embodiment includes the following steps:
[0047] Conditions: suppose there are R table and S table. Find the corresponding content of S table on the hash table based on R table and save it.
[0048]
[0049] The init() function in the algorithm needs to initialize the following contents: the vector channel size is initialized to W, the current position i of the S table is 0, the current position j of the output table is 0, the bit mask m is initialized to true, and the offset vector Q is 0. Define the key hash table as Tk, define the value hash table as Tv, define the input key group as Sk, define the input value group as Sv. Define the output key group RSk, define the output value group RSvr related to R, and define the output value group RSvs related to S;
[0050] The final output result is three parts, the record key group Rsk, the output value group Rsv, and the output value group Rs vs. In the process of searching the hash table, the corresponding key is found and the search is not immediately ended, and only when the empty bucket is found, the search of the corresponding element is ended. This is because the keys in the hash bucket may be repeated, resulting in the same key in several consecutive positions.
[0051] 2. Hash table building method based on SIMD technology
[0052] The embodiment relates to a hash table building method based on SIMD technology, and the specific method comprises the following contents.
[0053] Condition: assuming that we want to build a hash table for the R table.
[0054]
[0055] The init() function in the algorithm needs to initialize the following contents: the vector channel size is initialized as W, the record vector L is initialized as a sequence value from 1 to W, the current position of the R table is 0, the bit mask m is initialized as true, and the offset vector Q is 0. The key group of the R table is defined as Rk, and the value group of the R table is defined as Rv; the hash table of the record key group is defined as Tk, and the hash table of the record value group is defined as Tv.
[0056] The final output result is two parts, the hash table Tk of the record key group and the hash table Tv of the value group. L and Lb in the algorithm play an important role in preventing conflicts. The conflict here refers to the fact that multiple elements in the same vector group are mapped to the same empty position of the hash table. If it can be ensured that the input keys are unique, the vector K can be scattered to the hash table, and then the corresponding positions of the hash table are aggregated, and then compared with the vector K. In this case, the algorithm can save the time of one scattering operation.
[0057] 3. Custom conversion library implementation and conversion process
[0058] The various SIMD instruction sets involved in the embodiment are the AVX instruction set of X86, the SSE instruction set, and the Neon instruction set of the ARM system. The scalar can only perform one operation at a time, the SIMD instruction set adopts a controller to control multiple processing processes, and simultaneously executes the same operation on each column of data in a data set to realize spatial parallelism, and the calculation mode is as shown in the following formula. Figure 2
[0059] The conversion library involved in the embodiment mainly involves the AvxToNeon framework library and the custom implementation library ATN. The ATN module mainly extends the conversion of the basic functions not involved in the original framework library, and mainly includes the conversion of part of the AVX instruction set and part of the SSE instruction set to the Neon instruction set function. The important conversion functions of the AVX instruction set and the SSE instruction set involved, some examples are as follows:
[0060]
[0061] The main implementation mode of the embodiment is to regard the AVX and SSE instruction set functions as custom inline functions in the ARM environment, and then use the Neon instruction set function to implement the corresponding function. The implementation process is as follows:
[0062]
[0063] Algorithm input: a, b
[0064] Algorithm output: res_m128i
[0065] Description: The input variables a and b are both 128 bits, and the output is a union structure variable. Essentially, the __m128i_mm_and_si128() function is an AVX instruction set function and cannot be used on ARM. The purpose is to input two 128-bit variables and return the binary AND result of the corresponding position of 128 bits. Therefore, the embodiment uses the Neon instruction set function vandq_s32() in ARM to implement the corresponding implementation. The effect of the __m128i_mm_and_si128() function is the same in the implementation of X86 and ARM.
[0066] The specific conversion process of the embodiment is to import the normally running vector hash query and hash table building program on X86 into the ARM platform, change the header file library call path through the header file call mode. The specific content of the imported file is as follows:
[0067]
[0068] When compiling the vector hash query and hash table building algorithm of X86 and ARM platforms, the corresponding and appropriate compilation parameters should be used for compilation. The source file name of the embodiment is hash.c, and the target file name is target. The X86 compilation format is as follows:
[0069]
[0070] The compilation format of the embodiment on the ARM platform is as follows:
Claims
1. A method for accelerating database hash operation based on ARM platform, characterized in that, The implementation steps are: (1) According to the existing linear detection method of hash query scalar algorithm, through vectorization transformation, the hash query algorithm based on SIMD technology is realized, including the following contents; The number of vector bit mask channels needs to be determined according to the specific business scenario, and needs to be determined before the algorithm starts; 6 basic operations allowed to be used in the algorithm need to be defined, specifically, vector loading, vector storage, aggregation, scattering, selective loading, and selective scattering, the subsequent algorithm is completed based on the 6 basic operations; After the hash query finds the corresponding position of the hash table with elements, and is equal to the matched elements, the corresponding record needs to be recorded, but still needs to continue to find until the empty position is found to end; (2) According to the existing linear detection method of hash table scalar algorithm, the hash table algorithm based on SIMD technology is realized; (3) According to the existing AvxToNeon library, the custom ATN conversion module is expanded to realize the conversion from AVX instruction set and SSE instruction set to Neon instruction set; (4) Through the quick conversion process, the above hash query and hash table algorithm based on AVX instruction set and SSE instruction set are converted into ARM architecture algorithm based on Neon instruction set: the vector hash query and hash table program running normally on X86 is imported into the ARM platform, and the header file library call path is changed through the header file call; When compiling the vector hash query and hash table algorithm of the ARM platform, use the corresponding compilation parameters for compilation.
2. The method of claim 1, wherein, The hash table algorithm based on SIMD technology specifically includes: (1) Assuming that the number of vector channels is W, a temporary vector needs to be initialized in advance and assigned to 1 to W, which is used for subsequent conflict detection; (2) During the hash table building process, the vector scattering and aggregation need to be performed once, which is used to detect the conflict of the same vector insertion.
3. The method of claim 1, wherein, The custom ATN conversion module is expanded, and the contents are as follows: (1) Analyze the existing basic conversion functions in the AvxToNeon framework library; (2) The ATN module mainly expands the conversion of the basic functions not involved in the original library, mainly including the conversion of part of the AVX instruction set and part of the SSE instruction set to the Neon instruction set function; (3) The main implementation method of the ATN module is to regard the AVX and SSE instruction set functions as custom functions in the ARM environment, and then use the Neon instruction set function to realize the corresponding function; (4) The implemented ATN conversion function is encapsulated into the corresponding header file.