Methods, devices, and media for generating functional safety protection circuit design documents

Abstract

A method, apparatus, and medium for generating functional safety protection circuit design files are disclosed. The method includes: copying a protected circuit design file to obtain reference circuit design code; determining port connection information of a code set including the reference circuit design code and a preset circuit design code based on port identifiers and port types in the protected circuit design file; determining second bit width definition information of the code set based on the first bit width definition information of the protected circuit design file and the port connection information of the code set; and generating a first functional safety protection circuit design file corresponding to the protected circuit design file based on the code set, port connection information, and second bit width definition information. This disclosure achieves automatic and efficient generation of functional safety protection circuit design files without extensive manual intervention, enabling the protection of the protected circuit, thereby shortening the integrated circuit design cycle and saving development costs.

Description

Technical Field

[0001] This disclosure relates to integrated circuit technology, and in particular to a method, apparatus and medium for generating functional safety protection circuit design documents. Background Technology

[0002] Automotive-grade chips need to meet functional safety requirements. Therefore, the design process for automotive-grade chips necessitates the creation of functional safety circuits for the control circuits. Currently, the functional safety circuit design mechanism involves designers manually writing functional safety protection circuit design documents for each of the numerous control circuits within the integrated circuit. Given the large number of control circuits in automotive-grade chips, manually implementing protection mechanisms for these circuits not only incurs a massive workload but also increases the risk of incorrect circuit implementation. Furthermore, the inconsistent circuit structures written by different designers pose a significant challenge to functional safety verification. Summary of the Invention

[0003] To address the technical problems of current functional safety design mechanisms, which are mainly implemented manually, resulting in high workload and low efficiency, this disclosure is proposed. Embodiments of this disclosure provide a method, apparatus, and medium for generating functional safety protection circuit design documents.

[0004] According to one aspect of the present disclosure, a method for generating a functional safety protection circuit design document is provided, comprising:

[0005] Copy the design file of the protected circuit to obtain the reference circuit design code;

[0006] Based on the port identifier and port type in the protected circuit design file, determine the port connection information of the code set including the reference circuit design code and the preset circuit design code;

[0007] Based on the first bit width definition information of the protected circuit design file and the port connection information of the code set, the second bit width definition information of the code set is determined;

[0008] Based on the code set, the port connection information, and the second bit width definition information, a first functional safety protection circuit design file corresponding to the protected circuit design file is generated.

[0009] According to another aspect of the present disclosure, an apparatus for generating functional safety protection circuit design documents is provided, comprising:

[0010] The copy module is used to copy the protected circuit design file to obtain the reference circuit design code;

[0011] The first determining module is used to determine the port connection information of the code set, including the reference circuit design code and the preset circuit design code obtained by the copying module, based on the port identifier and port type in the protected circuit design file.

[0012] The second determining module is used to determine the second bit width definition information of the code set based on the first bit width definition information of the protected circuit design file and the port connection information determined by the first determining module.

[0013] The generation module is used to generate a first functional safety protection circuit design file corresponding to the protected circuit design file based on the code set, the port connection information determined by the first determining module, and the second bit width definition information determined by the second determining module.

[0014] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program for executing the above-described method for generating functional safety protection circuit design documents.

[0015] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising:

[0016] processor;

[0017] Memory used to store the processor's executable instructions;

[0018] The processor is configured to read the executable instructions from the memory and execute the instructions to implement the above-mentioned method for generating functional safety protection circuit design documents.

[0019] Based on the method for generating functional safety protection circuit design files provided in the above embodiments of this disclosure, reference circuit design code can be automatically generated for the protected circuit design file, and port connection information and second bit width definition information can be automatically determined for the code set including the reference circuit design code and the preset circuit design code. In this way, the code set, port connection information, and second bit width definition information can be used to generate the first functional safety protection circuit design file corresponding to the protected circuit design file. Thus, by adopting the functional safety design mechanism in the embodiments of this disclosure, functional safety protection circuit design files can be automatically and efficiently generated without a large amount of manual intervention, so as to protect the protected circuit accordingly, thereby shortening the integrated circuit design cycle and saving development costs.

[0020] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0021] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0022] Figure 1 This is a structural diagram of the functional safety protection circuit in an embodiment of this disclosure.

[0023] Figure 2 This is a flowchart illustrating a method for generating a functional safety protection circuit design document provided in an exemplary embodiment of this disclosure.

[0024] Figure 3 This is a flowchart illustrating a method for generating a functional safety protection circuit design document provided in another exemplary embodiment of this disclosure.

[0025] Figure 4-1 This is a flowchart illustrating a method for generating a functional safety protection circuit design document, provided in yet another exemplary embodiment of this disclosure.

[0026] Figure 4-2 This is a flowchart illustrating a method for generating a functional safety protection circuit design document, provided in yet another exemplary embodiment of this disclosure.

[0027] Figure 5 This is a flowchart illustrating a method for generating a functional safety protection circuit design document, provided in yet another exemplary embodiment of this disclosure.

[0028] Figure 6 This is a flowchart illustrating a method for generating a functional safety protection circuit design document, provided in yet another exemplary embodiment of this disclosure.

[0029] Figure 7 This is a flowchart illustrating a method for generating a functional safety protection circuit design document, provided in yet another exemplary embodiment of this disclosure.

[0030] Figure 8 This is a schematic diagram of the structure of a device for generating a functional safety protection circuit design document provided in an exemplary embodiment of this disclosure.

[0031] Figure 9 This is a schematic diagram of the structure of a device for generating a functional safety protection circuit design document provided in another exemplary embodiment of this disclosure.

[0032] Figure 10 This is a schematic diagram of the structure of a device for generating functional safety protection circuit design documents, provided in yet another exemplary embodiment of this disclosure.

[0033] Figure 11 This is a schematic diagram of the structure of a device for generating functional safety protection circuit design documents, provided in yet another exemplary embodiment of this disclosure.

[0034] Figure 12 This is a schematic diagram of the structure of a device for generating functional safety protection circuit design documents, provided in yet another exemplary embodiment of this disclosure.

[0035] Figure 13 This is a schematic diagram of the structure of a device for generating functional safety protection circuit design documents, provided in yet another exemplary embodiment of this disclosure.

[0036] Figure 14 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0037] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0038] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0039] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0040] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0041] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0042] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0043] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0044] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0045] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0046] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0047] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0048] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0049] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0050] Application Overview

[0051] Integrated circuits are an important component of intelligent vehicles. Once an integrated circuit fails due to functional safety issues, it may have serious consequences for people, equipment, and the environment. Therefore, the biggest problem facing automobile manufacturers is how to avoid potential risks during the integrated circuit design phase. Thus, functional safety design during the integrated circuit design phase is of paramount importance.

[0052] In the process of developing this disclosure, the inventors discovered that the current functional safety design mechanism involves designers manually writing functional safety protection circuit design documents for each of the numerous control circuits in an integrated circuit. It is readily apparent that the current functional safety design mechanism, which relies on manual implementation of control circuit protection, suffers from high workload and low efficiency, thus lengthening the integrated circuit design cycle and increasing development costs.

[0053] Exemplary System

[0054] A control circuit in an integrated circuit can be used as Figure 1 To protect the protected circuit 10 shown, a corresponding functional safety protection circuit can be set in the integrated circuit.

[0055] like Figure 1 As shown, the functional safety protection circuit may include: a reference circuit 11, a comparison circuit 12, a result register circuit 13, an input delay timing circuit 14, an output delay timing circuit 15, and a gate circuit 16.

[0056] The reference circuit 11 and the protected circuit 10 can be the same circuit, and the reference circuit 11 and the protected circuit 10 can share the same input data.

[0057] The comparison circuit 12 can compare whether the output data of the reference circuit 11 is the same as the output data of the protected circuit 10 to obtain the comparison result.

[0058] The result register circuit 13 can register and output the comparison results obtained by the comparison circuit 12 in an ordered manner.

[0059] The input delay timing circuit 14 can perform input delay timing processing on the reference circuit 11, and the output delay timing circuit 15 can perform output delay timing processing on the protected circuit 10. The delay timing values ​​used for the input delay timing processing and the output delay timing processing can be the same.

[0060] The gate circuit 16 can provide clock signals to the reference circuit 11, the comparison circuit 12, the result register circuit 13, the input delay beat circuit 14, and the output delay beat circuit 15 respectively.

[0061] Since the reference circuit 11 and the protected circuit 10 are the same circuit and share the same input data, theoretically, the output data of the reference circuit 11 and the output data of the protected circuit 10 should be the same. That is, the comparison result obtained by the comparison circuit 12 should be used to characterize that the output data of the reference circuit 11 and the output data of the protected circuit 10 are the same. In this way, the actual comparison result obtained by the reference comparison circuit 12 can determine whether the protected circuit 10 has a fault.

[0062] If the comparison result actually obtained by the comparison circuit 12 is used to characterize the output data of the reference circuit 11 as the same as the output data of the protected circuit 10, it means that the actual situation is consistent with the theoretical situation. Therefore, it can be determined that the protected circuit 10 has not failed and can work normally.

[0063] If the comparison result actually obtained by the comparison circuit 12 is used to characterize the output data of the reference circuit 11 and the output data of the protected circuit 10, it means that the actual situation does not match the theoretical situation. Therefore, it can be determined that the protected circuit 10 has a fault and cannot work normally. At this time, it is necessary to report the fault and repair the protected circuit 10.

[0064] The structure and working principle of the functional safety protection circuit corresponding to the protected circuit 10 have been introduced above. By adopting the above structure and working principle, the protection of the protected circuit 10 can be effectively achieved.

[0065] During the integrated circuit design phase, a first functional safety protection circuit design file can be generated using the method for generating functional safety protection circuit design files provided in the embodiments of this disclosure. The function of the first functional safety protection circuit design file is to provide a reliable reference for the circuit manufacturing plant, so that the circuit manufacturing plant can construct a physical hardware circuit based on the first functional safety protection circuit design file as the functional safety protection circuit corresponding to the protected circuit 10.

[0066] It should be noted that the design file for the first functional safety protection circuit can be derived from several design codes, such as: reference circuit design code, preset comparator circuit design code, preset result register circuit design code, preset input delay timing circuit design code, preset output delay timing circuit design code, and preset gate control circuit design code; among them, the reference circuit design code can be combined with... Figure 1 The reference circuit 11 in the code corresponds to the preset comparator circuit design code. Figure 1 The comparison circuit 12 in the code corresponds to the preset result register circuit design code. Figure 1 The result register circuit 13 corresponds to the preset input delay timing circuit design code. Figure 1 The input delay beat circuit 14 corresponds to the preset output delay beat circuit design code; Figure 1 The output delay beat circuit 15 corresponds to the preset gate circuit design code. Figure 1 The gate circuit 16 in the middle corresponds to this.

[0067] The correspondence between the reference circuit design code and reference circuit 11 can be understood as follows: the reference circuit design code defines the circuit structure of reference circuit 11 (e.g., what ports are included, what circuit modules are included, how the circuit modules are connected, what electronic components are included in the circuit modules, etc.) and its operational logic (what processing is performed on the input data, from which port to output data based on the processing results, what kind of data is output, etc.). Based on the reference circuit design code, the circuit manufacturing plant can construct a physical hardware circuit as reference circuit 11. The correspondence between other circuit design codes and other circuits can be understood by referring to the explanation of the correspondence between the reference circuit design code and reference circuit 11, and will not be elaborated further here.

[0068] Optionally, any design code involved in the embodiments of this disclosure can be program code written in a preset programming language, including but not limited to C, C++, Java, etc.

[0069] Exemplary methods

[0070] Figure 2 This is a flowchart illustrating a method for generating a functional safety protection circuit design document according to an exemplary embodiment of this disclosure. Figure 2 The method shown includes steps 210, 220, 230 and 240, which are explained below.

[0071] Step 210: Copy the protected circuit design file to obtain the reference circuit design code.

[0072] Optionally, the protected circuit design file can be... Figure 1 The protected circuit 10 corresponds to the protected circuit design file. The correspondence between the protected circuit design file and the protected circuit 10 can be found in the explanation of the correspondence between the circuit design code and the circuit above, and will not be repeated here.

[0073] Since the reference circuit design code is obtained by copying the protected circuit design file, the reference circuit design code and the protected circuit design file can be the same.

[0074] Step 220: Based on the port identifier and port type in the protected circuit design file, determine the port connection information of the code set including the reference circuit design code and the preset circuit design code.

[0075] Optionally, the protected circuit design file may include: multiple port identifiers (which are related to...) Figure 1The protected circuit 10 has multiple ports that correspond one-to-one with each other, and multiple port identifiers that correspond to the port types. The port identifiers include, but are not limited to, port names and port numbers. The port types include, but are not limited to, MCLK (clock type), RST (reset type), IN (input type), OUT (output type), CONST (constant type), NODLY (no delay type), NOCMP (no comparison type), etc.

[0076] In step 220, multiple port identifiers and multiple port types corresponding to the multiple port identifiers can be extracted from the protected circuit design file, and based on the extracted multiple port identifiers and multiple port types, port connection information including the code set of the reference circuit design code and the preset circuit design code can be determined.

[0077] Preset circuit design code can be circuit design code that designers have written and stored in advance to form functional safety protection circuit design documents.

[0078] The port connection information of the code set can be used to indicate the connection status between ports for the circuits corresponding to each design code included in the code set.

[0079] In an optional example, if among the multiple port types extracted from the protected circuit design file there is a port type that is different from MCLK, RST, IN, OUT, CONST, NODLY, and NOCMP, it can be determined that the port type does not conform to the rules, and a port abnormality prompt message will be output to notify the designer to handle the abnormality.

[0080] Step 230: Based on the first width definition information of the protected circuit design file and the port connection information of the code set, determine the second width definition information of the code set.

[0081] Optionally, the protected circuit design file may include: a first width definition information, which can be used to indicate: the port bit width of each port and the signal bit width between ports for the multiple ports included in the protected circuit 10.

[0082] In step 230, the first bit width definition information can be extracted from the protected circuit design file. Referring then to the port connection information determined in step 220, the second bit width definition information of the code set can be determined. This second bit width definition information indicates the port bit width of each port and the signal bit width between ports within the circuit corresponding to each design code in the code set. For clarity, the method for determining the second bit width definition information will be illustrated below with examples.

[0083] Step 240: Based on the code set, port connection information, and second bit width definition information, generate the first functional safety protection circuit design file corresponding to the protected circuit design file.

[0084] In step 240, the code set, port connection information, and second bit width definition information can be encapsulated to generate a first functional safety protection circuit design file corresponding to the protected circuit design file, so as to ensure the hierarchy and readability of the first functional safety protection circuit design file, thereby facilitating subsequent product development.

[0085] Of course, in step 240, the first functional safety protection circuit design file can be generated without encapsulation, as long as the first functional safety protection circuit design file includes the code set, port connection information and second bit width definition information.

[0086] Based on the method for generating functional safety protection circuit design files provided in the above embodiments of this disclosure, reference circuit design code can be automatically generated for the protected circuit design file, and port connection information and second bit width definition information can be automatically determined for the code set including the reference circuit design code and the preset circuit design code. In this way, the code set, port connection information, and second bit width definition information can be used to generate the first functional safety protection circuit design file corresponding to the protected circuit design file. Thus, by adopting the functional safety design mechanism in the embodiments of this disclosure, the generation of functional safety protection circuit design files can be automatically and efficiently realized without a lot of manual intervention, so as to realize the protection of the protected circuit 10, thereby shortening the integrated circuit design cycle and saving development costs.

[0087] In one optional example, the preset circuit design code includes: preset delay pausing circuit design code;

[0088] exist Figure 2 Based on the illustrated embodiments, as Figure 3 As shown, before step 220, the method further includes steps 212, 214 and 216.

[0089] Step 212: Determine the delay timing parameters in the design file of the protected circuit.

[0090] Optionally, the protected circuit design file may include: the keyword Dx. If x in Dx is equal to 0, it can be determined that no delay pausing is required when protecting the protected circuit 10. If x in Dx is not equal to 0, it can be determined that delay pausing is required when protecting the protected circuit 10, and the delay pausing parameter is x. For example, if x is 1, the delay pausing parameter is determined to be 1. The delay pausing may include: input delay pausing and output delay pausing.

[0091] Step 214: Set the delay timer value of the preset delay timer circuit design code according to the delay timer parameters.

[0092] Optionally, the preset delay pacing circuit design code may include: preset input delay pacing circuit design code and preset output delay pacing circuit design code; wherein, both the preset input delay pacing circuit design code and the preset output delay pacing circuit design code can be pre-written and stored design codes, and both the preset input delay pacing circuit design code and the preset output delay pacing circuit design code have a region for filling the delay pacing value (hereinafter referred to as the target region); the preset input delay pacing circuit design code can correspond to the input delay pacing process, and the preset output delay pacing circuit design code can correspond to the output delay pacing process.

[0093] In step 214, the target areas of both the preset input delay beat circuit design code and the preset output delay beat circuit design code can be filled with the delay beat parameters determined in step 212 to achieve the setting of the delay beat value.

[0094] Step 216: Determine the target to which the delay beat value indicated by the preset delay beat mode is applied.

[0095] Optionally, the preset delay timing mode can be used to indicate the object to which the delay timing value is applied. The object to which the delay timing value is applied can include: an input application object and an output application object; wherein, the input application object can be one of the reference circuit design code and the protected circuit design file, and the output application object can be the other of the reference circuit design code and the protected circuit design file.

[0096] If the input target is the reference circuit design code and the output target is the protected circuit design file, this indicates that the input delay timing processing is applied to the reference circuit design code. Figure 1 The reference circuit 11 in the middle, the target of the output delay and timing processing is Figure 1 The protected circuit 10 in the example. Conversely, if the input application target is the protected circuit design file and the output application target is the reference circuit design code, this indicates that the input delay timing processing is applied to the protected circuit design file. Figure 1 The protected circuit 10 in the middle, the target of the output delay and timing processing is Figure 1 Reference circuit 11 in the diagram.

[0097] Step 220 includes step 2202.

[0098] Step 2202: Determine the port connection information based on the port identifier and port type in the protected circuit design file, as well as the object to which the delay beat value is applied.

[0099] It should be noted that, Figure 1 The input delay timing circuit 14 is used to perform input delay timing processing on the reference circuit 11. Figure 1 The output delay and timing circuit 15 is used to perform output delay and timing processing on the protected circuit 10. Correspondingly, the input data of the reference circuit 11 first passes through the input delay and timing circuit 14 before reaching the reference circuit 11, and the output data of the protected circuit 10 first passes through the output delay and timing circuit 15 before reaching the comparator circuit 12. Conversely, if... Figure 1 The input delay timing circuit 14 is used to perform input delay timing processing on the protected circuit 10. Figure 1 The output delay beat circuit 15 is used to perform output delay beat processing on the reference circuit 11. Then the input data of the reference circuit 11 does not need to go through the input delay beat circuit 14 and directly reaches the reference circuit 11. The output data of the protected circuit 10 does not need to go through the output delay beat circuit 15 and directly reaches the comparator circuit 12. Obviously, due to the change in the target of the input delay beat processing and the output delay beat processing, the connection between ports in the functional safety protection circuit also needs to be adjusted.

[0100] In view of this, in the embodiments of this disclosure, the port identifier and port type in the protected circuit design file, as well as the object to which the delay pausing value is applied, can be used together to determine the port connection information. This ensures that the determined port connection information is compatible with the preset delay pausing method, thereby ensuring that the objects of input delay pausing and output delay pausing for the constructed functional safety protection circuit are compatible with the preset delay pausing method. Furthermore, the introduction of delay pausing helps to introduce some differences in processing timing when the reference circuit 11 and the protected circuit 10 process the same input data, thus more effectively determining whether the protected circuit 10 has a fault, and thereby more effectively protecting the protected circuit 10.

[0101] In an optional example, the preset circuit design code further includes: preset comparator circuit design code, and the preset delay pausing circuit design code includes: preset input delay pausing circuit design code and preset output delay pausing circuit design code;

[0102] Step 2202 includes:

[0103] In response to the input application object of the delayed beat value being the reference circuit design code, based on the port identifier and port type in the protected circuit design file, a pair of port identifiers is determined for the preset input delayed beat circuit design code and the reference circuit design code to obtain a first port identifier pair; a pair of port identifiers is determined for the reference circuit design code and the preset comparison circuit design code to obtain a second port identifier pair.

[0104] In response to the fact that the output application object in the application object of the delay beat value is the protected circuit design file, based on the port identifier and port type in the protected circuit design file, a pair of port identifiers is determined for the protected circuit design file and the preset output delay beat circuit design code to obtain a third port identifier pair; a pair of port identifiers is determined for the preset output delay beat circuit design code and the preset comparison circuit design code to obtain a fourth port identifier pair;

[0105] Based on the first port identifier pair, the second port identifier pair, the third port identifier pair, and the fourth port identifier pair, determine the port connection information.

[0106] In one optional implementation, based on the port identifiers and port types in the protected circuit design file, paired port identifiers are determined for the preset input delay timing circuit design code and the reference circuit design code to obtain a first port identifier pair, including:

[0107] Based on the first port identifier and the first port type corresponding to the first port identifier in the protected circuit design file, a second port identifier corresponding to the first port identifier is determined for the reference circuit design code;

[0108] The design code for the preset input delay timing circuit determines the third port identifier that is paired with the second port identifier;

[0109] The first port identifier pair is determined based on the second port identifier and the third port identifier.

[0110] Optionally, based on the first port identifier and the first port type corresponding to the first port identifier in the protected circuit design file, a second port identifier corresponding to the first port identifier is determined for the reference circuit design code, including:

[0111] Determine the first preset string corresponding to the first port type;

[0112] The first port identifier is concatenated with the first preset string using the first preset connector to obtain the first connection result;

[0113] Based on the first connection result, determine the second port identifier.

[0114] Here, you can pre-set the mapping between port types and preset strings. See Table 1 below for details:

[0115] Port type Preset string MCLK String 1 RST String 2 IN String 3 OUT String 4 CONST String 5 NODLY String 6 NOCMP String 7

[0116] Table 1

[0117] Optionally, the first preset connector can be "-", "—", "&", etc., which will not be listed here.

[0118] In one example, the first port identifier is X1, and the first port type corresponding to the first port identifier is IN. Referring to Table 1, the first preset string is string 3. Assuming the first preset connector is "—", the first concatenation result obtained by concatenating the first port identifier with the first preset string using the first preset connector is "X1—string 3". Then, "X1—string 3" can be directly used as the second port identifier. Alternatively, the first concatenation result can be concatenated with the first port type using the first preset connector, and the concatenation result can be used as the first port identifier. In this case, the second port identifier is "X1—string 3—IN".

[0119] In this way, by utilizing the correspondence between port type and preset string, and through simple information connection processing, the second port identifier can be obtained efficiently and reliably from the first port identifier and the first port type.

[0120] If the second port identifier is known, the third port identifier that matches the second port identifier can be determined for the preset input delay clapping circuit design code.

[0121] Optionally, the third port identifier can be the same as the second port identifier. For example, if both the second and third port identifiers are "X1—String 3", then the first port identifier pair can be represented as: X1—String 3 (输入延迟打拍电路) &X1—String 3 (参考电路) .

[0122] Optionally, the third port identifier and the second port identifier can be different and have a specific relationship. Assuming the second port identifier is "X1—string 3", a string "match" to indicate the pairing can be connected after the second port identifier using a first preset connector. In this case, the third port identifier can be "X1—string 4—match", and the first port identifier pair can be represented as: X1—string 3—match. (输入延迟打拍电路) &X1—String 3 (参考电路) .

[0123] The above provides an example of how to obtain the first port identifier pair. The method for obtaining the second port identifier pair is similar to that for obtaining the first port identifier pair. The embodiments of this disclosure will not elaborate on the method for obtaining the second port identifier pair.

[0124] The following example illustrates how to obtain the third port identifier pair.

[0125] In one example, the protected circuit design file contains a fourth port identifier, X2. The second port type corresponding to the fourth port identifier is OUT. Referring to Table 1, the preset string corresponding to the second port type is string 4. Therefore, X2 can be concatenated with string 4 using "-" to obtain "X2—string 4". X2 and "X2—string 4" can serve as paired port identifiers for the protected circuit design file and the preset output delay timing circuit design code. Thus, the third port identifier pair can be represented as: X2 (被保护电路) &X2—String 4 (输出延迟打拍电路) Alternatively, X2 and "X2—string4—match" can be used as paired port identifiers to determine the protected circuit design file and the preset output delay timing circuit design code. Then, the third port identifier pair can be represented as: X2 (被保护电路) &X2—String 4—match (输出延迟打拍电路) .

[0126] The following example illustrates how to obtain the fourth port identifier pair.

[0127] The preset output delay timing circuit design code can include: Figure 1 The port identifier of the output port of the reference circuit 11 in the code, the preset comparator circuit design code may include: Figure 1 The port identifiers of the two input ports of the comparator circuit 12 are as follows. Here, the port identifier of the output port of the reference circuit 11 can be extracted from the preset output delay beat circuit design code, and the port identifier of one input port of the comparator circuit 12 can be extracted from the preset comparator circuit design code. Thus, two port identifiers can be obtained. Based on these two port identifiers, the paired port identifiers determined by the reference circuit design code and the preset comparator circuit design code can be assigned to obtain the second port identifier pair.

[0128] Assuming the port identifier of the output port of the reference circuit 11 extracted from the preset output delay timing circuit design code is X3, and the port identifier of one input port of the comparator circuit 12 extracted from the preset comparator circuit design code is X4, then the second port identifier pair can be represented as: X3 (参考电路) &X 4 (比较电路) Alternatively, if the circuit name in the protected circuit design file is B, the second port identifier pair can be represented as: B—X3 (参考电路) &B—X4 (比较电路) .

[0129] After obtaining the first to fourth port identifier pairs, port connection information including the first to fourth port identifier pairs can be generated. Of course, the port connection information can also include other port identifier pairs besides these, as detailed in the following description.

[0130] In this way, port connection information can be clearly indicated. Figure 1 The wiring configuration between the protected circuit 10, reference circuit 11, comparator circuit 12, input delay beat circuit 14, and output delay beat circuit 15 is illustrated. For example, a first port identifier pair can indicate that the output port of the input delay beat circuit 14 is connected to the input port of the reference circuit 11; a second port identifier pair can indicate that the output port of the reference circuit 11 is connected to one input port of the comparator circuit 12; a third port identifier pair can indicate that the output port of the protected circuit 10 is connected to the input port of the output delay beat circuit 15; and a fourth port identifier pair can indicate that the output port of the output delay beat circuit 15 is connected to another input port of the comparator circuit 12. This helps ensure that the circuit manufacturing plant correctly connects these circuits when constructing the physical hardware circuit, thereby ensuring the correctness and reliability of the final functional safety protection circuit.

[0131] In one optional example, based on the port identifiers and port types in the protected circuit design file, paired port identifiers are determined for the preset input delay timing circuit design code and the reference circuit design code, resulting in a first port identifier pair, including:

[0132] The first type of port identifier is determined from the port identifiers in the design file of the protected circuit. The port type corresponding to each port identifier in the first type of port identifier is the first preset input type.

[0133] The first type of port identifier is determined to meet the preset input delay timing condition. Based on the first type of port identifier and the port type corresponding to each port identifier in the first type of port identifier, the paired port identifiers are determined for the preset input delay timing circuit design code and the reference circuit design code, thus obtaining the first port identifier pair.

[0134] Optionally, the port type in the embodiments of this disclosure may include two preset input types, namely a first preset input type and a second preset input type; wherein, the first preset input type may be IN, where IN indicates that input delay and timing processing is required; and the second preset input type may be NODLY, where NODLY indicates that input delay and timing processing is not required.

[0135] In the embodiments of this disclosure, multiple port identifiers can be extracted from the protected circuit design file, and from the extracted port identifiers, port identifiers corresponding to port type IN can be determined. These port identifiers can form a first type of port identifier, which can be considered to meet the preset input delay timing condition. Alternatively, from the extracted port identifiers, port identifiers corresponding to port type NODLY can be determined. These port identifiers can form a second type of port identifier, which can be considered to not meet the preset input delay timing condition.

[0136] For each port identifier in the first type of port identifier that meets the preset input delay timing conditions, the paired port identifier can be determined by using the port identifier and the port type corresponding to the port identifier, and the corresponding first port identifier pair can be obtained. In this way, when the first type of port identifier includes more than one port identifier, more than one first port identifier pair can be obtained.

[0137] For each port identifier in the second type of port identifier that does not meet the preset input delay timing condition, it is not necessary to determine the corresponding first port identifier pair for that port identifier.

[0138] In the embodiments of this disclosure, by determining a first type of port identifier from the port identifiers in the protected circuit design file, determining that the first type of port identifier meets the preset input delay timing condition, and using only the first type of port identifier and its corresponding port type for obtaining the first port identifier pair, the functional safety protection circuit can be made to target only... Figure 1 The input data of a specific input port of the reference circuit 11 is processed by input delay and pacing, instead of processing the input data of all input ports. This allows for delay and pacing accurate to the input port level, thus enabling more precise and targeted protection of the protected circuit 10.

[0139] In one optional example, based on the port identifiers and port types in the protected circuit design file, paired port identifiers are determined for the protected circuit design file and the preset output delay timing circuit design code, resulting in a third port identifier pair, including:

[0140] The third type of port identifier is determined from the port identifiers in the protected circuit design file. The port type corresponding to each port identifier in the third type of port identifier is the first preset output type.

[0141] The third type of port identifier is determined to meet the preset output result comparison conditions. Based on the third type of port identifier and the port type corresponding to each port identifier in the third type of port identifier, the paired port identifiers are determined for the protected circuit design file and the preset output delay timing circuit design code, thus obtaining the third port identifier pair.

[0142] Optionally, the port type in the embodiments of this disclosure may include two preset output types, namely a first preset output type and a second preset output type; wherein, the first preset output type may be OUT, which indicates that the comparison of output data is required; the second preset output type may be NOCMP, which indicates that the comparison of output data is not required.

[0143] In the embodiments of this disclosure, multiple port identifiers can be extracted from the protected circuit design file, and from the extracted port identifiers, each port type corresponding to the port type OUT can be determined. These port types can form a third type of port identifier, which can be considered to meet the preset output result comparison conditions. Additionally, from the extracted port identifiers, each port type corresponding to the port type NOCMP can be determined. These port types can form a fourth type of port identifier, which can be considered to not meet the preset output result comparison conditions.

[0144] For each port identifier in the third type of port identifier that meets the preset output result comparison conditions, the paired port identifier can be determined by using the port identifier and the port type corresponding to the port identifier, and the corresponding third port identifier pair can be obtained. In this way, when the third type of port identifier includes more than one port identifier, more than one third port identifier pair can be obtained.

[0145] For each port identifier in the fourth type of port identifier that does not meet the preset output result comparison conditions, there is no need to determine the corresponding third port identifier pair for that port identifier.

[0146] In the embodiments of this disclosure, by determining a third type of port identifier from the port identifiers in the protected circuit design file, determining that the third type of port identifier meets the preset output result comparison conditions, and using only the third type of port identifier and its corresponding port type for obtaining the third port identifier pair, the functional safety protection circuit can ensure that only the third type of port identifier and its corresponding port type are used to obtain the third port identifier pair. Figure 1 The output data of a specific output port of the reference circuit 11 is compared with the corresponding output data of the protected circuit 10, without having to compare the output data of all output ports of the reference circuit 11. This allows for protection accurate to the output port level, thus enabling more precise and targeted protection of the protected circuit 10.

[0147] In one optional example, the preset circuit design code also includes: preset gating circuit design code and preset result register circuit design code;

[0148] Based on the port identifiers and port types in the protected circuit design file, and the object to which the delay beat value is applied, the port connection information is determined, including:

[0149] Based on the port identifiers and port types in the protected circuit design file, the paired port identifiers are determined for the preset gated circuit design code and the reference circuit design code, resulting in the fifth port identifier pair;

[0150] The port identifiers are paired with the preset comparator circuit design code and the preset result register circuit design code to obtain the sixth port identifier pair;

[0151] Based on the first circuit identifier in the protected circuit design file, pairing port identifiers are determined for the preset gate circuit design code and the preset input delay timing circuit design code to obtain the seventh port identifier pair; pairing port identifiers are determined for the preset gate circuit design code and the preset output delay timing circuit design code to obtain the eighth port identifier pair; pairing port identifiers are determined for the preset gate circuit design code and the preset comparator circuit design code to obtain the ninth port identifier pair; and pairing port identifiers are determined for the preset gate circuit design code and the preset result register circuit design code to obtain the tenth port identifier pair.

[0152] Based on the first port identifier pair, the second port identifier pair, the third port identifier pair, and the fourth port identifier pair, the port connection information is determined, including:

[0153] Based on the first port identifier pair, the second port identifier pair, the third port identifier pair, the fourth port identifier pair, the fifth port identifier pair, the sixth port identifier pair, the seventh port identifier pair, the eighth port identifier pair, the ninth port identifier pair, and the tenth port identifier pair, the port connection information is determined.

[0154] It should be noted that the method for obtaining the fifth port identifier pair can be the same as the example for obtaining the first port identifier pair described above, and the method for obtaining the sixth port identifier pair can be the same as the example for obtaining the fourth port identifier pair described above. They will not be repeated here.

[0155] Optionally, the first circuit identifier may include: the circuit name in the protected circuit design file.

[0156] Optionally, Figure 1The gate circuit 16 can include two output ports. Assuming the circuit name in the protected circuit design file is B, the port identifiers corresponding to these two output ports can be determined as "B-gate-1" and "B-gate-2". For the port identifier "B-gate-1", the corresponding port identifier can be determined for the preset input delay timing circuit design code. The determined port identifier can be "B-gate-1" or "B-gate-1-match". In this case, the seventh port identifier pair can be represented as: B-gate-1 (门控电路) &B—gate—1 (输入延迟打拍电路) Alternatively, the seventh port identifier pair can be represented as: B—gate-1 (门控电路) &B—gate—1—match (输入延迟打拍电路) .

[0157] Additionally, for the port identifier "B—gate-2", a corresponding port identifier can be determined for the preset output delay timing circuit design code. The determined port identifier can be "B—gate—2.1" or "B—gate—2.1—match". In this case, the eighth port identifier pair can be represented as: B—gate—2.1 (门控电路) &B—gate—2.1 (输出延迟打拍电路) Alternatively, the eighth port identifier pair can be represented as: B—gate-1 (门控电路) &B—gate—2.1—match (输出延迟打拍电路) .

[0158] For the port identifier "B—gate-2", a corresponding port identifier can be determined for the preset comparator circuit design code. The determined port identifier can be "B—gate—2.2" or "B—gate—2.2—match". In this case, the ninth port identifier pair can be represented as: B—gate—2.2 (门控电路) &B—gate—2.2 (比较电路) Alternatively, the ninth port identifier pair can be represented as: B—gate—2.2 (门控电路) &B—gate—2.2—match (输出延迟比较电路) Similarly, the tenth port identifier can be represented as: B—gate—2.3 (门控电路) &B—gate—2.3 (结果寄存电路) Alternatively, the tenth port identifier pair can be represented as: B—gate—2.3 (门控电路) &B—gate—2.3—match (结果寄存电路) .

[0159] After obtaining the fifth to tenth port identifier pairs, port connection information including the first to tenth port identifier pairs can be generated.

[0160] In this way, port connection information can be clearly indicated. Figure 1 The wiring configuration of the protected circuit 10, reference circuit 11, comparator circuit 12, result register circuit 13, input delay beat circuit 14, output delay beat circuit 15, and gate circuit 16 is explained. For example, the fifth port identifier pair, the eighth port identifier pair, the ninth port identifier pair, and the tenth port identifier pair can indicate that one output port of the gate circuit 16 is connected to the clock port of the reference circuit 11, the output delay beat circuit 15, the comparator circuit 12, and the result register circuit 13, respectively. The sixth port identifier pair can indicate that the output port of the comparator circuit 12 is connected to the input port of the result register circuit 13, and the seventh port identifier pair can indicate that the other output port of the gate circuit 16 is connected to the clock port of the input delay beat circuit 14. This helps ensure that the circuit manufacturing plant correctly connects these circuits when building the physical hardware circuit, thereby ensuring the correctness and reliability of the final functional safety protection circuit.

[0161] In an optional example, when determining the second bit width definition information based on the first bit width definition information and port connection information in the protected circuit design file, the port bit width of each port of the reference circuit 11 can be made consistent with the port bit width of the corresponding port of the protected circuit 10. In addition, the corresponding port bit width of the input port of the comparator circuit 12 can be determined based on the port bit width of each port of the reference circuit 11, and the signal bit width between the reference circuit 11 and the comparator circuit 12 can also be determined.

[0162] In one example, the protected circuit 10 has two input ports and two output ports. The first bit width definition information indicates that the bit width of each of the two input ports of the protected circuit 10 is K1 bits, and the bit width of each of the two output ports of the protected circuit 10 is K2 bits. Assuming that the port connection information indicates that the two output ports of the reference circuit 11 need to be connected to the same input port of the comparator circuit 12, the second bit width definition information can indicate that the bit width of each of the two input ports of the reference circuit 11 is K1 bits, and the bit width of each of the two output ports of the reference circuit 11 is K2 bits; among the two input ports of the comparator circuit 12, the bit width of the input port used to connect to the output port of the reference circuit 11 is 2*K2 bits; the signal bit width between the reference circuit 11 and the comparator circuit 12 is 2*K2 bits.

[0163] It should be noted that the bit width definition information of the reference circuit 11 itself in the second port bit width definition information, as well as the bit width definition information at the location with a direct line connection relationship to the reference circuit 11, can all utilize the first bit width definition information and port connection information. For specific examples, refer to the example in the previous paragraph. However, at locations without a direct line connection relationship to the reference circuit 11 (such as the output port of the comparison circuit 12 and the result register circuit 13), the bit width definition information at these locations can be determined using preset bit width definition information and port connection information. For example, the preset bit width definition information indicates that the port bit width of the output port of the comparison circuit 12 is 1 bit, the port bit width of the input port of the result register circuit 13 is 1 bit, and the port connection information indicates that the output port of the comparison circuit 12 is connected to the input port of the result register circuit 13. Then, the second bit width definition information can indicate that the port bit width of the output port of the comparison circuit 12 is 1 bit, the port bit width of the input port of the result register circuit 13 is 1 bit, and the signal bit width between the output port of the comparison circuit 12 and the input port of the result register circuit 13 is 1 bit.

[0164] exist Figure 1 Based on the illustrated embodiments, as Figure 4-1 As shown, before step 210, the method further includes steps 202, 204 and 206.

[0165] Step 202: Based on the user's input operation, determine the target circuit design document indicated by the input operation.

[0166] Alternatively, the user in the embodiments of this disclosure may be a designer.

[0167] Optionally, multiple circuit design files can be pre-stored. Each circuit design file can correspond to a circuit in an integrated circuit (which can be located in a chip) used to implement a specific function. Designers can select one circuit design file from multiple circuit design files through input operations, and that circuit design file can be used as the target circuit design file.

[0168] Optionally, input operations include, but are not limited to, voice input operations, touch input operations, and keyboard input operations.

[0169] Step 204: By searching the target circuit design file, determine the first position where the preset protection keyword appears and the second position where the preset end keyword appears in the target circuit design file.

[0170] Optionally, the default protection keyword can be AUTOFUSA, and the default end keyword can be END.

[0171] The target circuit design file may include multiple lines of program code pre-written by the designer. In step 204, the code in the target circuit design file can be searched line by line to determine the position where the preset protection keyword appears in the target circuit design text. This position is the first position. The search can continue from the first position to determine the position where the preset end keyword first appears after the preset protection keyword. This position can be used as the second position.

[0172] Step 206: Based on the first position and the second position, determine the protected circuit design file from the target circuit design file.

[0173] In step 206, all the code between the first and second positions in the target circuit design file can be extracted, and this code can be used to form the protected circuit design file.

[0174] Of course, after extracting all the code between the first and second positions in the target circuit design file, the circuit design file composed of these codes can be checked first, redundant parts can be removed, and for parts with obvious errors, the designer can be prompted to make corrections. After all these processes are completed, the processed circuit design file can be used as the protected circuit design file.

[0175] In the embodiments of this disclosure, designers only need to input operation instructions for the target circuit design file to automatically, efficiently and reliably determine the protected circuit design file based on the search of the target circuit design file and by referring to the keywords in the target circuit design file.

[0176] Of course, in practice, designers can also directly specify the design file of the protected circuit through input operations.

[0177] It should be noted that the target circuit design file may contain multiple preset protection keywords, as well as multiple preset end keywords that correspond one-to-one with these preset protection keywords. Thus, by searching the target circuit design file, the number of protected circuit design files can be determined. For each protected circuit design file, a first functional safety protection circuit design file can be generated, resulting in multiple first functional safety protection circuit design files. These multiple protected circuit design files correspond to the multiple first functional safety protection circuit design files (specifically, a one-to-one correspondence). In this way, the subsequent circuit manufacturing plant can construct multiple protected circuits 10 that correspond one-to-one with the multiple protected circuit design files.

[0178] exist Figure 4-1 Based on the illustrated embodiments, as Figure 4-2 As shown, the method further includes steps 250 and 260.

[0179] Step 250: Based on the user's input operation, determine the output method of multiple comparison results corresponding to multiple first functional safety protection circuit design files. The comparison result corresponding to any first functional safety protection circuit design file is: the comparison result of the output data corresponding to the protected circuit design file and the reference circuit design code in the first functional safety protection circuit design file.

[0180] Optionally, designers can specify the output method of multiple comparison results corresponding to multiple first-function safety protection circuit design documents through input operations; wherein, the output method specified by the user includes, but is not limited to, aggregated output method, separate output method, etc.

[0181] Step 260: Set the output method parameter values ​​of the target circuit design file according to the output method of multiple comparison results.

[0182] Optionally, an output mode parameter value can be configured corresponding to the target circuit design file.

[0183] If the output method for multiple comparison results is to output them separately, the output method parameter value can be set to 1 to indicate that multiple comparison results need to be output separately. In this way, when the circuit manufacturing plant builds the physical hardware circuit according to the target circuit design file, the resulting target circuit can output the comparison results corresponding to different protected circuits 10 through different output ports among multiple output ports.

[0184] If the output of multiple comparison results is in aggregated output mode, the output mode parameter value can be set to 2 to indicate that aggregated output is required for multiple comparison results. In this way, when the circuit manufacturing plant builds the physical hardware circuit according to the target circuit design file, the resulting target circuit can output the comparison results corresponding to different protected circuits 10 through the same output port.

[0185] In the embodiments of this disclosure, designers only need to specify the output method through input operations, and the output method parameter values ​​of the target circuit design file will be automatically set according to the output method required by the user. This helps to ensure that the final constructed target circuit outputs the comparison results in the manner required by the designer.

[0186] exist Figure 1 Based on the illustrated embodiments, as Figure 5 As shown, before step 210, the method further includes step 208.

[0187] Step 208: In response to the detection that a corresponding second functional safety protection circuit design file exists in the protected circuit design file, the second functional safety protection circuit design file is cleared.

[0188] In the embodiments of this disclosure, before generating the first functional safety protection circuit for the protected circuit design file, it can be determined whether there is a corresponding functional safety protection circuit design file for the protected circuit design file (i.e., a functional safety protection circuit design file generated historically for the protected circuit design file).

[0189] If the judgment result is that it does not exist, the design file of the first functional safety protection circuit can be generated directly to protect the protected circuit 10.

[0190] If the determination result is that the existing functional safety protection circuit design file exists, the existing functional safety protection circuit design file can be used as the second functional safety protection circuit design file. The second functional safety protection circuit design file can be cleared. After the clearing is completed, the first functional safety protection circuit design file is generated. This can avoid redundancy in the functional safety protection circuit design file.

[0191] Of course, in practice, the second function safety protection circuit design file may not be cleared automatically. Instead, the designer can specify whether to clear it by inputting an operation. If the input operation specifies that clearing is required, then the clearing operation of the second function safety protection circuit design file will be executed.

[0192] exist Figure 1 Based on the illustrated embodiments, as Figure 6 As shown, the method further includes steps 270, 280 and 290.

[0193] Step 270: The first circuit identifier of the protected circuit design document is connected to the second preset string through the second preset connector to obtain the second connection result.

[0194] Optionally, the first circuit identifier may include: the circuit name of the protected circuit design file; if the protected circuit design file is instantiated in a certain file and has an instantiation name, the first circuit identifier may also include: the instantiation name.

[0195] Optionally, the second preset connector can be "-", "—", "&", etc., and the second preset string can be "fusadcls", "fusa", etc., which will not be listed here.

[0196] Assuming the circuit name in the protected circuit design file is B, the instantiation name is C, the second preset connector is "—", and the second preset string is "fusadcls", then the second connection result can be "B—fusadcls" or "C—fusadcls". In some cases, the second connection result can also be "B—C—fusadcls".

[0197] Step 280: Based on the second connection result, determine the second circuit identifier for the first functional safety protection circuit design document.

[0198] Optionally, the second connection result can be directly used as the second circuit identifier; or, a specified suffix can be added to the second connection result, and the second connection result with the specified suffix can be used as the second circuit identifier.

[0199] Step 290: Based on the second circuit identifier, instantiate the first functional safety protection circuit design file into the protected circuit design file.

[0200] In step 290, the first functional safety protection circuit design file can be instantiated into the protected circuit design file using the second circuit identifier in any feasible manner.

[0201] In the embodiments of this disclosure, through a simple connection process, a second circuit identifier can be obtained efficiently and reliably from the first circuit identifier of the protected circuit design file. Using the second circuit identifier, the first functional safety protection circuit design file can be instantiated into the protected circuit design file. In this way, the first functional safety protection circuit design file and the protected circuit design file can form an organic whole. By providing this whole to the circuit manufacturing plant, the circuit manufacturing plant can correctly construct the functional safety protection circuit to reliably protect the protected circuit 10.

[0202] In an optional example, such as Figure 7 As shown, designers can first perform command line input (equivalent to the input operation mentioned above) to specify the target circuit design file, whether to clear existing functional safety protection circuit design files, whether multiple comparison results need to be aggregated for output, and the location of the generated functional safety protection circuit design file, etc.

[0203] Next, the protected circuit design files can be automatically identified. If AUTOFUSA is present in the target circuit design file, it can be determined that a protected circuit design file requiring the generation of a functional safety protection circuit design file exists within the target circuit design file. Furthermore, the number of protected circuit design files can be counted by referring to the frequency of AUTOFUSA occurrences in the target circuit design file.

[0204] Afterwards, the target circuit design file can be analyzed, tested, and stored. Optionally, the code included in the target circuit design file can be read line by line to determine the protected circuit design file from the target circuit design file, the circuit name or instantiation name of the protected circuit design file can be stored, the port keywords (equivalent to the port type mentioned above) in the protected circuit design file can be analyzed, the port identifiers can be classified and marked according to the keywords to determine the port connection information, and all parameters of the protected circuit design file (equivalent to the first width definition information mentioned above) can be stored to determine the second width definition information.

[0205] Next, a functional safety protection circuit design file can be generated. Optionally, a reference circuit design code can be obtained by copying the protected circuit design file. Based on the keyword Dx in the protected circuit design file, the delay amount for the output of the protected circuit 10 and the input of the reference circuit 11 can be determined. Accordingly, the delay values ​​for the preset input delay timing circuit design code and the preset output delay timing circuit design code can be set. Combining the reference circuit design code, the set preset input delay timing circuit design code and the preset output delay timing circuit design code, the preset comparator circuit design code, the preset result register circuit design code, the preset gate circuit design code, as well as port connection information and the second bit width definition information, a first functional safety protection circuit design file can be obtained through encapsulation. Additionally, a protection circuit identifier (equivalent to the second circuit identifier mentioned above) can be generated based on the circuit name or instantiation name of the protected circuit design file, and the first functional safety protection circuit design file can be instantiated into the protected circuit design file accordingly.

[0206] In the embodiments of this disclosure, reference circuit design code can be automatically generated by copying the design file of the protected circuit; the output mode can be indicated by input operation, and the comparison results of multiple protected circuits 10 can be directly output as the top-level port (corresponding to separate output mode), or they can be packaged and then combined into a bus for output (corresponding to aggregated output mode); it can also support delay timing accurate to the input port level, support functional protection accurate to the output port level, and support selectable delay number; through the application of clock gating logic (which is carried by a preset gating circuit design file), low power consumption design can be achieved; all inputs and outputs can be registered to automatically optimize timing; all registers involved in the functional safety protection circuit can have a reset signal, and the reset value can be defaulted to 0 or a specified reset value to enhance circuit robustness; by encapsulating to obtain the first functional safety protection circuit design file, it is beneficial to enhance the hierarchy and readability of the first functional safety protection circuit design file.

[0207] The method for generating a functional safety protection circuit design file provided in this disclosure can be executed by any suitable device with data processing capabilities, including but not limited to terminal devices and servers. Alternatively, the method for generating a functional safety protection circuit design file provided in this disclosure can be executed by a processor, such as by a processor calling corresponding instructions stored in memory to execute the method for generating a functional safety protection circuit design file mentioned in this disclosure. Further details will not be elaborated below.

[0208] Exemplary device

[0209] Figure 8 This is a schematic diagram of the structure of a device for generating a functional safety protection circuit design document provided in an exemplary embodiment of this disclosure. Figure 8 The apparatus shown includes a copying module 810, a first determining module 820, a second determining module 830, and a generating module 840.

[0210] The copy module 810 is used to copy the protected circuit design file to obtain the reference circuit design code;

[0211] The first determining module 820 is used to determine the port connection information of the code set, including the reference circuit design code and the preset circuit design code obtained by the copying module 810, based on the port identifier and port type in the protected circuit design file.

[0212] The second determining module 830 is used to determine the second bit width definition information of the code set based on the first bit width definition information of the protected circuit design file and the port connection information determined by the first determining module 820.

[0213] The generation module 840 is used to generate a first functional safety protection circuit design file corresponding to the protected circuit design file based on the code set, the port connection information determined by the first determining module 820, and the second bit width definition information determined by the second determining module 830.

[0214] In one optional example, the preset circuit design code includes: preset delay pausing circuit design code;

[0215] like Figure 9 As shown, the device also includes:

[0216] The third determining module 812 is used to determine the delay stepping parameters in the protected circuit design file before the first determining module 820 determines the port connection information, including the reference circuit design code and the preset circuit design code, based on the port identifier and port type in the protected circuit design file.

[0217] The first setting module 814 is used to set the delay beat value of the preset delay beat circuit design code according to the delay beat parameters determined by the third determining module 812.

[0218] The fourth determining module 816 is used to determine the object to which the delay beat value indicated by the preset delay beat mode is applied;

[0219] The first determining module 820 is specifically used for:

[0220] Based on the port identifier and port type in the protected circuit design file, and the object to which the delay beat value is applied as determined by the fourth determination module 816, the port connection information is determined.

[0221] In an optional example, the preset circuit design code further includes: preset comparator circuit design code, and the preset delay pausing circuit design code includes: preset input delay pausing circuit design code and preset output delay pausing circuit design code;

[0222] like Figure 9 As shown, the first determining module 820 includes:

[0223] The first determining submodule 8201 is used to respond to the input application object of the delay beat value determined by the fourth determining module 816 being the reference circuit design code obtained by the copying module 810, and to determine the paired port identifiers for the preset input delay beat circuit design code and the reference circuit design code obtained by the copying module 810 based on the port identifiers and port types in the protected circuit design file, thereby obtaining a first port identifier pair; and to determine the paired port identifiers for the reference circuit design code obtained by the copying module 810 and the preset comparison circuit design code, thereby obtaining a second port identifier pair.

[0224] The second determining submodule 8203 is used in response to the fourth determining module 816 determining that the output application object of the delay beat value application object is the protected circuit design file. Based on the port identifier and port type in the protected circuit design file, it determines the paired port identifiers for the protected circuit design file and the preset output delay beat circuit design code to obtain a third port identifier pair; and determines the paired port identifiers for the preset output delay beat circuit design code and the preset comparison circuit design code to obtain a fourth port identifier pair.

[0225] The third determining submodule 8205 is used to determine port connection information based on the first port identifier pair and the second port identifier pair obtained by the first determining submodule 8201, and the third port identifier pair and the fourth port identifier pair obtained by the second determining submodule 8203.

[0226] In one optional example, the first determined submodule 8201 includes:

[0227] The first determining unit is used to determine a first type of port identifier from the port identifiers in the protected circuit design file, wherein the port type corresponding to each port identifier in the first type of port identifier is a first preset input type.

[0228] The second determining unit is used to determine that the first type of port identifier determined by the first determining unit meets the preset input delay pausing conditions, and based on the first type of port identifier and the port type corresponding to each port identifier in the first type of port identifier, to determine the paired port identifier for the preset input delay pausing circuit design code and the reference circuit design code, thereby obtaining the first port identifier pair.

[0229] In one optional example, the second determining submodule 8203 includes:

[0230] The third determining unit is used to determine the third type of port identifier from the port identifiers in the protected circuit design file. The port type corresponding to each port identifier in the third type of port identifier is the first preset output type.

[0231] The fourth determining unit is used to determine whether the third type of port identifier determined by the third determining unit meets the preset output result comparison conditions, and based on the third type of port identifier and the port type corresponding to each port identifier in the third type of port identifier, to determine the paired port identifier for the protected circuit design file and the preset output delay timing circuit design code, and obtain the second port identifier pair.

[0232] In one optional example, the first determined submodule 8201 includes:

[0233] The fifth determining unit is used to determine a second port identifier corresponding to the first port identifier for the reference circuit design code obtained by the copying module 810 based on the first port identifier and the first port type corresponding to the first port identifier in the protected circuit design file.

[0234] The sixth determining unit is used to determine a third port identifier that matches the second port identifier determined by the fifth determining unit for the preset input delay timing circuit design code;

[0235] The seventh determining unit is used to determine the first port identifier pair based on the second port identifier determined by the fifth determining unit and the third port identifier determined by the sixth determining unit.

[0236] In one optional example, the fifth determining unit includes:

[0237] The first determining subunit is used to determine the first preset string corresponding to the first port type;

[0238] A connection subunit is used to connect the first port identifier with a first preset string determined by the first determining subunit through a first preset connector to obtain a first connection result;

[0239] The second determining subunit is used to determine the second port identifier based on the first connection result obtained from the connecting subunit.

[0240] In one optional example, the preset circuit design code also includes: preset gating circuit design code and preset result register circuit design code;

[0241] The first determining module 820 also includes:

[0242] The fourth determining submodule is used to determine the paired port identifiers for the preset gated circuit design code and the reference circuit design code obtained by the copying module 810 based on the port identifiers and port types in the protected circuit design file, thus obtaining the fifth port identifier pair;

[0243] The fifth determination submodule is used to determine the paired port identifiers for the preset comparison circuit design code and the preset result register circuit design code, resulting in the sixth port identifier pair;

[0244] The sixth determining submodule is used to determine paired port identifiers for the preset gate circuit design code and the preset input delay timing circuit design code based on the first circuit identifier in the protected circuit design file, to obtain the seventh port identifier pair; to determine paired port identifiers for the preset gate circuit design code and the preset output delay timing circuit design code, to obtain the eighth port identifier pair; to determine paired port identifiers for the preset gate circuit design code and the preset comparison circuit design code, to obtain the ninth port identifier pair; and to determine paired port identifiers for the preset gate circuit design code and the preset result register circuit design code, to obtain the tenth port identifier pair.

[0245] The third determining submodule 8205 is specifically used for:

[0246] The first determining submodule 8201 obtains the first port identifier pair and the second port identifier pair, the second determining submodule 8203 obtains the third port identifier pair and the fourth port identifier pair, the fourth determining submodule obtains the fifth port identifier pair, the fifth determining submodule obtains the sixth port identifier pair, and the sixth determining submodule obtains the seventh port identifier pair, the eighth port identifier pair, the ninth port identifier pair and the tenth port identifier pair, and determines the port connection information.

[0247] In an optional example, such as Figure 10 As shown, the device also includes:

[0248] The fifth determining module 802 is used to determine the target circuit design file indicated by the input operation based on the user's input operation before the copying module 810 copies the protected circuit design file to obtain the reference circuit design code.

[0249] The sixth determining module 804 is used to search the target circuit design file determined by the fifth determining module 802 to determine the first position where the preset protection keyword appears and the second position where the preset end keyword appears in the target circuit design file.

[0250] The seventh determining module 806 is used to determine the protected circuit design file from the target circuit design file based on the first position and the second position determined by the sixth determining module 804.

[0251] In one optional example, the target circuit design file contains multiple protected circuits, and the multiple protected circuits correspond to multiple first functional safety protection circuit design files.

[0252] like Figure 11 As shown, the device also includes:

[0253] The eighth determining module 850 is used to determine the output mode of multiple comparison results corresponding to multiple first functional safety protection circuit design files based on the user's input operation. The comparison result corresponding to any first functional safety protection circuit design file is: the comparison result of the output data corresponding to the protected circuit design file and the reference circuit design code in the first functional safety protection circuit design file.

[0254] The second setting module 860 is used to set the output mode parameter values ​​of the target circuit design file according to the output mode of multiple comparison results.

[0255] In an optional example, such as Figure 12 As shown, the device also includes:

[0256] The clearing module 808 is used to clear the second functional safety protection circuit design file in response to the detection that the protected circuit design file has a corresponding second functional safety protection circuit design file before the copying module 810 copies the protected circuit design file to obtain the reference circuit design code.

[0257] In an optional example, such as Figure 13 As shown, the device also includes:

[0258] The connection module 870 is used to connect the first circuit identifier of the protected circuit design file to the second preset string through the second preset connector to obtain the second connection result;

[0259] The ninth determining module 880 is used to determine the second circuit identifier for the first functional safety protection circuit design document based on the second connection result obtained by the connection module 870.

[0260] Instantiation module 890 is used to instantiate the first functional safety protection circuit design file into the protected circuit design file based on the second circuit identifier determined by the ninth determination module 880.

[0261] Exemplary electronic devices

[0262] Below, for reference Figure 14 This describes an electronic device according to embodiments of the present disclosure. The electronic device may be either or both of a first device and a second device, or a standalone device independent of them, which may communicate with the first device and the second device to receive acquired input signals from them.

[0263] Figure 14 A block diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0264] like Figure 14 As shown, the electronic device 1400 includes one or more processors 1401 and memory 1402.

[0265] The processor 1401 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1400 to perform desired functions.

[0266] The memory 1402 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1401 may execute the program instructions to implement the method for generating functional safety protection circuit design documents of the various embodiments of this disclosure described above, and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0267] In one example, the electronic device 1400 may also include an input device 1403 and an output device 1404, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0268] For example, when the electronic device is a first device or a second device, the input device 1403 can be the microphone or microphone array described above, used to capture the input signal from the sound source. When the electronic device is a standalone device, the input device 1403 can be a communication network connector, used to receive the acquired input signal from the first device and the second device.

[0269] In addition, the input device 1403 may also include, for example, a keyboard, a mouse, etc.

[0270] The output device 1404 can output various information to the outside, including determined distance information, direction information, etc. The output device 1404 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0271] Of course, for the sake of simplicity, Figure 14 Only some of the components of the electronic device 1400 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 1400 may include any other suitable components depending on the specific application.

[0272] Exemplary computer program products and computer-readable storage media

[0273] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps in the methods for generating functional safety protection circuit design documents according to various embodiments of this disclosure as described in the "Exemplary Methods" section of this specification.

[0274] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0275] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps in the method for generating a functional safety protection circuit design document according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0276] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0277] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0278] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0279] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0280] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0281] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. A method for generating a functional safety protection circuit design document, comprising: Copy the design file of the protected circuit to obtain the reference circuit design code; Based on the port identifiers and port types in the protected circuit design file, the port connection information of the code set, including the reference circuit design code and the preset circuit design code, is determined; wherein, the protected circuit design file includes keywords that characterize the need for delayed pausing processing, and the port connection information of the code set is adapted to the preset delayed pausing method; Based on the first bit width definition information of the protected circuit design file and the port connection information of the code set, the second bit width definition information of the code set is determined; Based on the code set, the port connection information, and the second bit width definition information, a first functional safety protection circuit design file corresponding to the protected circuit design file is generated.

2. The method according to claim 1, wherein, The preset circuit design code includes: preset delay beat-up circuit design code; Before determining the port connection information of the code set including the reference circuit design code and the preset circuit design code based on the port identifier and port type in the protected circuit design file, the method further includes: Determine the delay timing parameters in the design file of the protected circuit; According to the aforementioned delay timing parameters, the delay timing value of the preset delay timing circuit design code is set; Determine the object to which the delay beat value indicated by the preset delay beat mode is applied; The process of determining port connection information for a code set including the reference circuit design code and a preset circuit design code, based on the port identifier and port type in the protected circuit design file, includes: Based on the port identifier and port type in the protected circuit design file, and the object to which the delay beat value is applied, the port connection information is determined.

3. The method according to claim 2, wherein, The preset circuit design code also includes: preset comparison circuit design code, and the preset delay beat circuit design code includes: preset input delay beat circuit design code and preset output delay beat circuit design code; The determination of the port connection information based on the port identifier and port type in the protected circuit design file, and the object to which the delay beat value is applied, includes: In response to the input application object being the reference circuit design code in the application object of the delay beat value, based on the port identifier and port type in the protected circuit design file, a pair of port identifiers is determined for the preset input delay beat circuit design code and the reference circuit design code to obtain a first port identifier pair; and a pair of port identifiers is determined for the reference circuit design code and the preset comparison circuit design code to obtain a second port identifier pair. In response to the fact that the output application object in the application object of the delay beat value is the protected circuit design file, based on the port identifier and port type in the protected circuit design file, a pair of port identifiers is determined for the protected circuit design file and the preset output delay beat circuit design code to obtain a third port identifier pair; and, a pair of port identifiers is determined for the preset output delay beat circuit design code and the preset comparison circuit design code to obtain a fourth port identifier pair; The port connection information is determined based on the first port identifier pair, the second port identifier pair, the third port identifier pair, and the fourth port identifier pair.

4. The method according to claim 3, wherein, The step of determining paired port identifiers for the preset input delay timing circuit design code and the reference circuit design code based on the port identifiers and port types in the protected circuit design file to obtain a first port identifier pair includes: From the port identifiers in the protected circuit design file, a first type of port identifier is determined, and the port type corresponding to each port identifier in the first type of port identifier is a first preset input type; The first type of port identifier is determined to meet the preset input delay timing condition. Based on the first type of port identifier and the port type corresponding to each port identifier in the first type of port identifier, a pair of port identifiers is determined for the preset input delay timing circuit design code and the reference circuit design code to obtain the first port identifier pair.

5. The method according to claim 3, wherein, The process of determining paired port identifiers for the protected circuit design file and the preset output delay timing circuit design code based on the port identifiers and port types in the protected circuit design file to obtain a third port identifier pair includes: A third type of port identifier is determined from the port identifiers in the protected circuit design file, and the port type corresponding to each port identifier in the third type of port identifier is a first preset output type; The third type of port identifier is determined to meet the preset output result comparison conditions. Based on the third type of port identifier and the port type corresponding to each port identifier in the third type of port identifier, a pair of port identifiers is determined for the protected circuit design file and the preset output delay pausing circuit design code, thus obtaining the third port identifier pair.

6. The method according to claim 3, wherein, The step of determining paired port identifiers for the preset input delay timing circuit design code and the reference circuit design code based on the port identifiers and port types in the protected circuit design file to obtain a first port identifier pair includes: Based on the first port identifier and the first port type corresponding to the first port identifier in the protected circuit design file, a second port identifier corresponding to the first port identifier is determined for the reference circuit design code; The design code for the preset input delay timing circuit determines a third port identifier that is paired with the second port identifier; The first port identifier pair is determined based on the second port identifier and the third port identifier.

7. The method according to claim 6, wherein, The step of determining a second port identifier corresponding to the first port identifier for the reference circuit design code based on the first port identifier and the first port type corresponding to the first port identifier in the protected circuit design file includes: Determine the first preset string corresponding to the first port type; The first port identifier is concatenated with the first preset string using a first preset connector to obtain the first connection result; Based on the first connection result, the second port identifier is determined.

8. The method according to any one of claims 3-7, wherein, The preset circuit design code also includes: preset gating circuit design code and preset result register circuit design code; The step of determining the port connection information based on the port identifier and port type in the protected circuit design file, and the object to which the delay beat value is applied, further includes: Based on the port identifiers and port types in the protected circuit design file, a pair of port identifiers is determined for the preset gated circuit design code and the reference circuit design code to obtain the fifth port identifier pair; A pair of port identifiers is determined for the preset comparison circuit design code and the preset result register circuit design code to obtain a sixth port identifier pair; Based on the first circuit identifier in the protected circuit design file, a pair of port identifiers is determined for the preset gate circuit design code and the preset input delay timing circuit design code to obtain a seventh port identifier pair; a pair of port identifiers is determined for the preset gate circuit design code and the preset output delay timing circuit design code to obtain an eighth port identifier pair; a pair of port identifiers is determined for the preset gate circuit design code and the preset comparison circuit design code to obtain a ninth port identifier pair; and a pair of port identifiers is determined for the preset gate circuit design code and the preset result register circuit design code to obtain a tenth port identifier pair. The step of determining the port connection information based on the first port identifier pair, the second port identifier pair, the third port identifier pair, and the fourth port identifier pair includes: The port connection information is determined based on the first port identifier pair, the second port identifier pair, the third port identifier pair, the fourth port identifier pair, the fifth port identifier pair, the sixth port identifier pair, the seventh port identifier pair, the eighth port identifier pair, the ninth port identifier pair, and the tenth port identifier pair.

9. The method according to claim 1, wherein, Before copying the protected circuit design file to obtain the reference circuit design code, the method further includes: Based on the user's input, determine the target circuit design document indicated by the input; By searching the target circuit design file, the first position where the preset protection keyword appears and the second position where the preset end keyword appears in the target circuit design file are determined; Based on the first location and the second location, the protected circuit design file is determined from the target circuit design file.

10. The method according to claim 9, wherein, The number of protected circuit design files in the target circuit design file is multiple, and the multiple protected circuit design files correspond to multiple first functional safety protection circuit design files. The method further includes: Based on the user's input operation, the output mode of multiple comparison results corresponding to multiple first functional safety protection circuit design files is determined. The comparison result corresponding to any first functional safety protection circuit design file is: the comparison result of the output data corresponding to the protected circuit design file and the reference circuit design code in the first functional safety protection circuit design file respectively. The output method parameter values ​​of the target circuit design file are set according to the output method of the multiple comparison results.

11. The method according to claim 1, wherein, Before copying the protected circuit design file to obtain the reference circuit design code, the method further includes: In response to the detection that the protected circuit design file contains a corresponding second functional safety protection circuit design file, the second functional safety protection circuit design file is cleared.

12. The method according to claim 1, further comprising: The first circuit identifier of the protected circuit design file is connected to the second preset string through the second preset connector to obtain the second connection result; Based on the second connection result, a second circuit identifier is determined for the first functional safety protection circuit design document; Based on the second circuit identifier, the first functional safety protection circuit design file is instantiated into the protected circuit design file.

13. An apparatus for generating functional safety protection circuit design documents, comprising: The copy module is used to copy the protected circuit design file to obtain the reference circuit design code; The first determining module is used to determine the port connection information of a code set including the reference circuit design code obtained by the copying module and the preset circuit design code, based on the port identifier and port type in the protected circuit design file; wherein, the protected circuit design file includes keywords that characterize the need for delayed padding processing, and the port connection information of the code set is adapted to the preset delayed padding method; The second determining module is used to determine the second bit width definition information of the code set based on the first bit width definition information of the protected circuit design file and the port connection information determined by the first determining module. The generation module is used to generate a first functional safety protection circuit design file corresponding to the protected circuit design file based on the code set, the port connection information determined by the first determining module, and the second bit width definition information determined by the second determining module.

14. A computer-readable storage medium storing a computer program for executing the method for generating a functional safety protection circuit design document according to any one of claims 1-12.

15. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the method for generating a functional safety protection circuit design document as described in any one of claims 1-12.

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