An accelerator design method of a dual 6T-SRAM memory cell and dual bit local computing cell based on split word lines

Abstract

This invention discloses an accelerator design method based on a dual 6T-SRAM memory cell with split word lines and a dual-bit local computation unit. Employing in-memory computing technology, it is used to accelerate artificial intelligence (AI) neural networks. Compared to traditional in-memory local computation units, this macrocell utilizes the characteristics of split-word-line 6T-SRAM. During operation, it simultaneously selects two word lines (WL) and read word lines (RWL) of a local cell, allowing data to be imported into the computation unit through the local bit lines and their inverse logic (LBL and LBLB) to complete the operation. This design can significantly improve the parallelism of operations while efficiently utilizing bit line pre-filling.

Description

Technical Field

[0001] This invention belongs to the field of application-specific integrated circuit (ASIC) design technology, and particularly relates to an accelerator design method based on a dual 6T-SRAM memory cell and a dual-bit local computing cell with separate word lines. Background Technology

[0002] In recent years, artificial intelligence (AI) applications have developed rapidly, and AI chips are the foundation of their computing power. Energy efficiency is a key indicator, referring to the reciprocal of the energy required for each computational operation, i.e., the number of operations that can be completed per unit of energy, measured in TOPS / W. However, in edge AI chip designs based on the traditional von Neumann architecture, the frequent and large-scale data transfers between the processor and memory via a limited-bandwidth bus lead to the "memory wall" or "power wall" problem, significantly limiting the energy efficiency of such chips. It is widely recognized in academia and industry that in-memory computing architecture can overcome this bottleneck of the traditional von Neumann architecture. This architecture not only retains the storage and read / write access functions inherent in memory itself but also supports different logical or matrix multiplication and addition operations, thereby greatly reducing the frequent interactions between the processor and memory, reducing the amount of intermediate data movement, and further improving system energy efficiency. Local Computation Cells (LCCs) are a popular in-memory computing implementation method proposed in recent years. Their key feature is that a group of memory cells share a single set of operational logic, reducing area and improving signal margin by decreasing the number of operational transistors. However, conventional LCCs can only utilize a single-sided memory node, leading to two problems: firstly, low computational parallelism due to underutilized data; and secondly, high pre-charge overhead and wasted power due to the large amount of local word line pre-charge on a single side. Summary of the Invention

[0003] The purpose of this invention is to provide an accelerator design method based on a dual 6T-SRAM memory cell and a dual-bit local computing unit with separate word lines, in order to solve the technical problems of low parallelism due to underutilization of data and high pre-charge overhead and power waste of a single local word line.

[0004] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:

[0005] An accelerator design method based on a dual 6T-SRAM memory cell and a dual-bit local computing unit with separate word lines includes the following:

[0006] The dual 6T-SRAM memory cell (DB6T) based on split word lines includes four NMOS transistors and four inverters; the four NMOS transistors are denoted as N1 to N4, and the four inverters are denoted as INV1 to INV4; wherein: the input node of INV1, the output node of INV2, and the drain of N1 are electrically connected, denoted as memory node Q[x+1], where x is an odd number; the output node of INV1, the input node of INV2, and the drain of N2 are electrically connected, denoted as memory node QB[x+1], where QB[x+1] and Q[x+1] are mutually coupled memory nodes and are logically opposite; the input node of INV3, the output node of INV4, and N3 are connected to the drain of N2. The drain of N4 is electrically connected, denoted as storage node QB[x]; the output node of INV3, the input node of INV4, and the drain of N4 are electrically connected, denoted as storage node Q[x], Q[x] and QB[x] are mutually coupled storage nodes, and their logic is opposite; the gate of transistor N1 is controlled by the word line, denoted as WL[x+1], and the source of transistor N1 is connected to the local bit line, denoted as LBL; the gate of transistor N2 is controlled by the read word line, denoted as RWL[x+1], and the source of transistor N2 is not connected to the local bit line, denoted as LBLB; the gate of transistor N3 is controlled by the word line, denoted as WL[x]; the gate of transistor N4 is controlled by the read word line, denoted as RWL[x];

[0007] The dual-bit local computation unit (DBLCC) has multiple interfaces, including LBL, LBLB, horizontal read / write control word line (HWL), global bit line GBL, global bit line inverse logic GBLB, and output port (SUM). In read / write mode, HWL is connected to a high level, GBL and LBL are electrically connected, and GBLB and LBLB are electrically connected, enabling global read / write. In operation mode, HWL is connected to a low level, GBL and LBL are electrically isolated, and GBLB and LBLB are electrically isolated. The weight input of the DBLCC is imported from dual 6T-SRAM storage cells through LBL and LBLB, and the feature input is imported through GBL and GBLB. It can process two-bit multiplication operations simultaneously or reduce the processing to fewer bits.

[0008] The accelerator design method based on dual 6T-SRAM memory cells and dual-bit local computing units using split word lines, as described in this invention, has the following advantages:

[0009] (1) The dual 6T-SRAM storage unit of the present invention can store two bits of data, which are transmitted to DBLCC for calculation through LBL and LBLB, thereby increasing the number of computable weights and improving the calculation throughput.

[0010] (2) In the present invention, the multiplication and addition operations of two-bit weights and multi-bit feature values ​​can be performed simultaneously in DBLCC. At the same time, the multi-bit feature values ​​reuse GBL and GBLB, which makes the overall routing overhead smaller and the layout planning simpler. Attached Figure Description

[0011] Figure 1 This is a structural diagram of the dual 6T-SRAM memory cell and dual-bit local computing unit based on the separated word line of the present invention;

[0012] Figure 2 This is a timing diagram of the operation of the dual 6T-SRAM memory cell and dual-bit local computing unit based on the split word line of the present invention. Detailed Implementation

[0013] To better understand the purpose, structure, and function of this invention, the following description, in conjunction with the accompanying drawings, provides a more detailed explanation of an accelerator design method based on a dual 6T-SRAM memory cell and a dual-bit local computing cell using a split word line.

[0014] Figure 1 Figure 2 The following assumptions were made to make the solution easier to understand:

[0015] 1. The storage uses 8 DB cells as one local storage module;

[0016] 2. During storage, data is stored in positive logic for odd-numbered rows (i.e., LBL end nodes store Q data, LBLB end nodes store QB data), and even-numbered rows are stored in reverse logic.

[0017] 3. Assume that GBL and GBLB input data with different feature values;

[0018] like Figure 1As shown in the figure, it is assumed that 8 DBcells are selected as a group of local storage blocks. Taking storage block DBcell#7 as an example, it includes four NMOS transistors and four inverters. The four NMOS transistors are denoted as N1 to N4, and the four inverters are denoted as INV1 to INV4. Among them, the input node of INV1, the output node of INV2 and the drain of N1 are electrically connected and are denoted as storage node Q[7]. The output node of INV1, the input node of INV2 and the drain of N2 are electrically connected and are denoted as storage node QB[7]. QB[7] and Q[7] are mutually coupled storage nodes and are logically opposite. The input node of INV3, the output node of INV4 and the drain of N3 are electrically connected and are denoted as storage node QB[6]. The output node of INV3, the input node of INV4, and the drain of N4 are electrically connected and are denoted as storage node Q[6]. Q[6] and QB[6] are mutually coupled storage nodes and are logically opposite. The gate of transistor N1 is controlled by word line and is denoted as WL[7]. The source of transistor N1 is connected to local bit line and is denoted as LBL. The gate of transistor N2 is controlled by read word line and is denoted as RWL[7]. The source of transistor N2 is not connected to local bit line and is denoted as LBLB. The gate of transistor N3 is controlled by word line and is denoted as WL[6]. The source of transistor N3 is connected to local bit line and is denoted as LBL. The gate of transistor N4 is controlled by read word line and is denoted as RWL[6]. The source of transistor N4 is not connected to local bit line and is denoted as LBLB.

[0019] The dual-bit local computation unit (DBLCC) has multiple interfaces for its arithmetic module, namely LBL, LBLB, the horizontal read / write control word line (HWL), the global bit line and its inverse logic (GBL, GBLB), and the output port (SUM). In read / write mode, HWL is connected to a high level, GBL and LBL are electrically connected, and GBLB and LBLB are electrically connected, allowing for global read / write. In arithmetic mode, HWL is connected to a low level, GBL and LBL are electrically isolated, and GBLB and LBLB are electrically isolated. The weight input of the DBLCC is imported by the DBcell through LBL and LBLB, and the feature input is imported through GBL and GBLB. It can simultaneously process multiplication and addition operations of two-bit weights and multi-bit features, or it can be reduced to processing with fewer bits.

[0020] Figure 2The timing diagram of the operation of the present invention based on the dual 6T-SRAM memory cell and local computing unit with "separated word line" is shown. During operation, HWL is connected to low level, GBL and LBL are electrically isolated, GBLB and LBLB are electrically isolated, WL[7] is connected to low level to turn off, and RWL[7] is connected to high level to turn on, so that the data in memory node QB[7] can be transmitted to DBLCC through LBLB; at the same time, WL[6] is connected to high level to turn on, and RWL[6] is connected to low level to turn off, so that the data in memory node QB[6] can be transmitted to DBLCC through LBL; the data on GBL represents the data of feature value 1, and the data on GBLB represents the data of feature value 2. Through the operation of DBLCC, the result of multiplying and adding 2 bits of weight and a pair of feature values ​​can be obtained. The result is output by SUM, where SUM1 represents the result of multiplying and adding with feature value 1, and SUM2 represents the result of multiplying and adding with feature value 2.

[0021] It is understood that the present invention has been described through some embodiments, and those skilled in the art will recognize that various changes or equivalent substitutions can be made to these features and embodiments without departing from the spirit and scope of the invention. Furthermore, under the teachings of the present invention, these features and embodiments can be modified to adapt to specific situations and materials without departing from the spirit and scope of the invention. Therefore, the present invention is not limited to the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the protection scope of the present invention.

Claims

1. An accelerator design method based on a dual 6T-SRAM memory cell and a dual-bit local computation unit with separate word lines, characterized in that, Including the following: The DB6T dual 6T-SRAM memory cell based on a split word line includes four NMOS transistors and four inverters. The four NMOS transistors are denoted as N1 to N4, and the four inverters are denoted as INV1 to INV4. Specifically: the input node of INV1, the output node of INV2, and the drain of N1 are electrically connected, denoted as memory node Q[x+1], where x is an odd number; the output node of INV1, the input node of INV2, and the drain of N2 are electrically connected, denoted as memory node QB[x+1]. QB[x+1] and Q[x+1] are mutually coupled memory nodes and are logically opposite; the input node of INV3, the output node of INV4, and the drain of N3 are electrically connected. The drains of N4 and N5 are electrically connected, denoted as storage node QB[x]. The output node of INV3, the input node of INV4, and the drain of N4 are electrically connected, denoted as storage node Q[x]. Q[x] and QB[x] are mutually coupled storage nodes, and their logic is opposite. The gate of transistor N1 is controlled by the word line, denoted as WL[x+1]. The source of transistor N1 is connected to the local bit line, denoted as LBL. The gate of transistor N2 is controlled by the read word line, denoted as RWL[x+1]. The source of transistor N2 is not connected to the local bit line, denoted as LBLB. The gate of transistor N3 is controlled by the word line, denoted as WL[x]. The gate of transistor N4 is controlled by the read word line, denoted as RWL[x]. The dual-bit local computation unit (DBLCC) has multiple interfaces, including LBL, LBLB, a horizontal read / write control word line HWL, a global bit line GBL, a global bit line inverse logic GBLB, and an output port SUM. In read / write mode, HWL is connected to a high level, GBL and LBL are electrically connected, and GBLB and LBLB are electrically connected for global read / write. In operation mode, HWL is connected to a low level, GBL and LBL are electrically isolated, and GBLB and LBLB are electrically isolated. The weight values ​​of the DBLCC are input from dual 6T-SRAM storage cells through LBL and LBLB, and the feature values ​​are input from GBL and GBLB.

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