A vector processor and processing method supporting multiple precision calculation and dynamic configuration

Abstract

The vector processor and the data processing method provided by the application add a systolic array acceleration unit in a processor channel to realize the calculation between vectors. The storage unit on the original architecture is fully utilized, the data throughput is increased, the calculation between more vector data is realized, the acceleration effect of the systolic array accelerator is fully utilized, and the utilization rate of the calculation is greatly improved. The systolic array accelerator can support multi-precision and ultra-low bit quantization calculation, improve the efficiency of vector calculation, and the parallelism and scalability of the vector processor can greatly improve the data calculation density, thereby effectively improving the computing power.

Description

Technical Field

[0001] This application relates to the fields of integrated circuits and communication technology, and in particular to a vector processor and processing method that supports multi-precision calculation and dynamic configuration. Background Technology

[0002] Neural network models typically consist of numerous network layers. Each layer involves a convolution operation between a weight matrix and an activation matrix. The weight matrix contains a large amount of weight data, and the activation matrix contains a large amount of activation data. When performing a convolution operation, it is generally converted into a matrix multiplication, which is then calculated using a matrix multiplication processor to obtain the result.

[0003] A matrix multiplication processor typically includes multiple basic arithmetic units arranged in a systolic array. Multiple weight data and activation data are broadcast to the systolic array under the control of a clock signal. The entire matrix multiplication operation process is implemented by controlling each basic arithmetic unit to continuously perform multiplication and accumulation operations on the received weight data and activation data through control signals.

[0004] With the development of deep neural networks, matrix multiplication and addition has gradually become a key computational focus for processors. Currently, most matrix multiplication and addition calculations are implemented using arithmetic logic units (ALUs). However, ALUs can only perform calculations on a single, fixed-width data set per cycle, failing to fully utilize the computational power of matrix multiplication and addition. This results in low computational efficiency and low data utilization for existing matrix multiplication and addition algorithms implemented using ALUs. From the perspective of current solutions, the bottleneck lies in the fact that the current hardware architecture can only perform serial vector-scalar calculations, which are essentially scalar-to-scalar calculations, thus preventing the computational architecture from achieving ideal utilization. Therefore, how to better design and implement hardware units for matrix multiplication and addition calculations using limited resources has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides a vector processor and processing method that supports multi-precision calculation and dynamic configuration, which can be used to solve the technical problem of low computational utilization.

[0006] In a first aspect, embodiments of this application provide a vector processor that supports multi-precision calculation and dynamic configuration, comprising:

[0007] The control module is a functional unit used to receive externally input operation instructions, parse the operation instructions to obtain vector calculation instructions and vector storage and loading instructions, and determine the function of sending the vector calculation instructions.

[0008] A loading storage module is used to load data to be processed from an external source according to the vector storage loading instruction;

[0009] An extended channel module is provided, comprising a channel storage unit and a pulsating array acceleration unit. The channel storage unit stores the data to be processed, and the pulsating array acceleration unit retrieves corresponding data from the channel storage unit according to the vector calculation instruction, performs vector calculations, and returns the calculation results to the channel storage unit for storage. The calculation results stored in the channel storage unit are transmitted to the outside through the loading storage module.

[0010] In conjunction with the first aspect, in one possible implementation of the first aspect, the control module includes an instruction distribution unit and a main sequencing unit. The instruction distribution unit receives externally input operation instructions, processes the operation instructions, identifies the type of operation instructions and the corresponding functional unit, and transmits the operation instructions to the main sequencing unit. The main sequencing unit broadcasts the instructions to all functional units and monitors the running status of the instructions.

[0011] In conjunction with the first aspect, in one possible implementation of the first aspect, the extended channel module includes a channel instruction sequencing unit, the channel storage unit, and several computing processing units, wherein the computing processing unit includes the pulsating array acceleration unit.

[0012] In conjunction with the first aspect, in one possible implementation of the first aspect, the channel storage unit includes a vector register file and an operand queue. The vector register file is used to provide operands for functional units and absorb their results. The operand queue connects the computation processing unit and the vector register file and is used to allocate operands for each of the computation processing units.

[0013] In conjunction with the first aspect, in one possible implementation of the first aspect, the vector register file includes several storage banks and an arbitration unit. The storage banks are single-port and have a bit width of 64 bits. Each vector register file has 8 storage banks for loading and transmitting data to be processed and calculation results. The arbitration unit is used to allocate the priority of each operation instruction.

[0014] In conjunction with the first aspect, in one possible implementation of the first aspect, the channel instruction sequencing unit is used to send operation instructions to each functional unit within the extended channel module and initiate a request to read operands from the vector register file.

[0015] In conjunction with the first aspect, in one possible implementation of the first aspect, after the pulsating array acceleration unit receives a request to read data from the vector register file, it automatically inputs the data to be processed into the buffer in sequence, and after loading is completed, it determines whether to start calculation based on the input mode. The calculation result is automatically stored in the output buffer, and it waits for the instruction to output the result back to the vector register file.

[0016] In conjunction with the first aspect, in one possible implementation of the first aspect, the operation instruction is a custom instruction, all of which are vector instructions, including the vector calculation instruction, vector loading instruction, and vector storage instruction. The custom instruction includes target address information and action information; the custom instruction is processed from an external input vector processor.

[0017] In conjunction with the first aspect, in one possible implementation of the first aspect, the loading storage module includes a data loading unit and a data storage unit, wherein the data loading unit loads data via an AXIAW bus, and the data storage unit uses an AXIAW bus for storing data.

[0018] Secondly, embodiments of this application provide a data processing method that supports multi-precision calculation and dynamic configuration, including,

[0019] The control module receives operation commands from external sources;

[0020] The control module parses the operation instructions to obtain vector calculation instructions and vector storage loading instructions, as well as a functional unit to determine the transmission of the vector calculation instructions;

[0021] The loading and storage module loads the data to be processed from the outside according to the vector storage loading instruction;

[0022] The pulse array acceleration unit in the extended channel module retrieves corresponding data from the channel storage unit according to the vector calculation instructions, performs vector calculations, and returns the calculation results to the channel storage unit for storage; the calculation results stored in the channel storage unit are transmitted to the outside through the loading storage module.

[0023] The vector processor and data processing method provided by this invention incorporate a systolic array acceleration unit within the processor channel to perform calculations between vectors. This fully utilizes the original architecture's storage units, increasing data throughput and enabling calculations between a large number of vector data sets. This allows for full utilization of the systolic array accelerator's acceleration effect, significantly improving computational efficiency. The systolic array accelerator supports multi-precision and ultra-low bit quantization calculations, improving vector computation efficiency. Simultaneously, the vector processor's parallelism and scalability greatly enhance data computation density, thereby effectively boosting computing power. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the vector processor framework structure in Example 1;

[0025] Figure 2 This is a schematic diagram of the vector processor framework structure in Example 2;

[0026] Figure 3 This is a framework diagram of the extended channel module in Example 2;

[0027] Figure 4 This is a schematic diagram of the working principle of the pulsating array acceleration unit.

[0028] Figure 5 This diagram illustrates the comparison of storage bandwidth utilization between traditional multiplication tree architecture and systolic array.

[0029] Figure 6 This is a schematic diagram of the components of a vector calculation instruction;

[0030] Figure 7 A schematic diagram illustrating the composition of vector storage and load instructions;

[0031] Figure 8 This is a flowchart of the data processing during the instruction execution process in Example 2;

[0032] Figure 9 This is a flowchart of the method in Example 3.

[0033] 100. Control module; 200. Expansion channel module; 300. Loading and storage module;

[0034] 101. Instruction dispatch unit; 102. Main sequencing unit;

[0035] 201. Channel storage unit; 202. Calculation and processing unit; 203. Channel instruction sequencing unit;

[0036] 201a, Vector Register File; 201b, Operand Queue;

[0037] 202a, Pulsating Array Acceleration Unit; 202b, Arithmetic Logic Unit; 202c, Multiplication Calculation Unit; 202d, Floating-Point Processing Unit;

[0038] 201a-1, Storage unit; 201a-2, Arbitration unit;

[0039] 301. Data loading unit; 302. Data storage unit. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0041] Example 1

[0042] The following is a combination of... Figure 1 The possible system architectures applicable to the embodiments of this application are described.

[0043] Please refer to Figure 1 The example illustrates a schematic diagram of a vector processor applicable to embodiments of this application, which includes an extended channel module 200, a control module 100, and a loading and storage module 300.

[0044] The control module 100 is a functional unit used to receive externally input operation instructions, parse the operation instructions to obtain vector calculation instructions and vector storage loading instructions, and determine the sending of the vector calculation instructions.

[0045] A loading storage module 300 is used to load data to be processed from an external source according to the vector storage loading instruction.

[0046] An extended channel module 200 includes a channel storage unit 201 and a pulsating array acceleration unit 202a. The channel storage unit 201 stores the data to be processed, and the pulsating array acceleration unit 202a retrieves corresponding data from the channel storage unit 201 according to the vector calculation instruction, performs vector calculations, and returns the calculation results to the channel storage unit 201 for storage. The calculation results stored in the channel storage unit 201 are transmitted to the outside through the loading storage module 300.

[0047] The vector processor provided in this embodiment incorporates a systolic array acceleration unit 202a within the processor channel and features a dedicated vector instruction call to the systolic array acceleration unit 202a for vector-to-vector computation. Compared to the original arithmetic logic unit 202b, which can only perform computation on a single fixed-width data point per cycle, the systolic array acceleration unit 202a fully utilizes the original architecture's storage units, increasing data throughput and enabling computation between a larger number of vector data points. This allows the acceleration effect of the systolic array accelerator to be fully utilized, significantly improving computational utilization. The systolic array accelerator supports multi-precision and ultra-low bit quantization computations, improving vector computation efficiency. Simultaneously, the parallelism and scalability of the vector processor can greatly increase data computation density, thereby effectively enhancing computing power.

[0048] Example 2

[0049] This embodiment provides a vector processor that supports multi-precision calculation and dynamic configuration, and its architecture is as follows: Figure 2 As shown.

[0050] The control module 100 includes an instruction distribution unit 101 and a main sequencing unit 102. The instruction distribution unit 101 receives externally transmitted operation instructions, processes the operation instructions, identifies the type of operation instructions and the corresponding functional unit, and transmits the operation instructions to the main sequencing unit 102. The main sequencing unit 102 broadcasts the instructions to all functional units and monitors the operation status of the instructions.

[0051] Specifically, the instruction dispatch unit 101 is the decoder of the vector processor, responsible for receiving operation instructions from external sources (i.e., the first-level instruction decoding unit), thereby identifying the vector functional unit corresponding to the vector instruction, the type of operation instruction, and other information. After instruction identification is completed, the instruction dispatch unit 101 transmits the operation instruction and the decoded information to the main sequencing unit 102 for subsequent processing. The instruction dispatch unit 101 can also filter the type of instruction and provide feedback to the first-level instruction decoder; for example, if a scalar instruction is received, an error message will be returned.

[0052] The main sequencer unit 102 is responsible for tracking the operation instructions running on the extended channel module 200, assigning them to different functional units, and confirming them through an external processing unit. The main sequencer unit 102 can monitor the execution progress of all instructions on the extended channel module 200. The main sequencer unit 102 also stores information about which vector instruction is accessing which vector register. This information is used to identify data hazards between instructions in order to determine the priority of each instruction.

[0053] like Figure 2 As shown, the extended channel module 200 includes a channel instruction sequencing unit 203, a channel storage unit 201, and several calculation processing units 202. The channel instruction sequencing unit 203 is used to send operation instructions to each functional unit within the extended channel module 200. The channel storage unit 201 is used to store the data to be processed and the calculation results. The calculation processing units 202 are used to receive vector calculation instructions, read the data to be processed in the channel storage unit 201, perform calculations, and then return the calculation results to the channel storage unit 201.

[0054] like Figure 2As shown, the vector processor also includes several other extended channel modules 200, namely channel 1…channel N, etc., while the extended channel module 200 containing the systolic array acceleration unit 202a in this example is channel 0. Each extended channel module 200 has the following channel structure: each channel has its own channel instruction sequencing unit 203, responsible for tracking up to 8 parallel vector instructions. Each channel also has a set of channel storage units 201 containing a register file to coordinate its access operation queue, and a computational processing unit 202 containing an integer arithmetic logic unit 202b, an integer multiplier, and a floating-point calculation unit. Each channel contains the entire register file and a portion of the computational processing unit 202. In this embodiment, a systolic array acceleration unit 202a is added to the channel structure for processing operations between vectors.

[0055] The following is combined with Figure 3 Analyze the specific structure within the extended channel module 200.

[0056] The channel instruction sequencing unit 203 is used to send operation instructions to each functional unit within the extended channel module 200, controlling their execution within the scope of a single channel. Unlike the main sequencing unit 102, the channel instruction sequencing unit 203 does not store the state of currently running instructions, avoiding data duplication between channels. It also initiates requests to read operands from the vector register file 201a in the channel storage unit 201.

[0057] The channel storage unit 201 in this embodiment includes a vector register file 201a and an operand queue 201b. The vector register file 201a is used to provide operands for the functional units and absorb their results. The operand queue 201b connects the computing processing unit 202 and the vector register file 201a and is used to allocate operands for each of the computing processing units 202.

[0058] The vector register file 201a includes several memory banks 201a-1 and arbitration units 201a-2. The memory banks 201a-1 are single-port and have a bit width of 64 bits. Each vector register file 201a contains 8 memory banks 201a-1 for loading and transmitting data to be processed and calculation results. The arbitration unit 201a-2 is used to allocate the priority of each operation instruction.

[0059] The Vector Register Files (VRFs) 201a are the core of every vector processor. Because several instructions can run in parallel, the VRFs must be able to support sufficient throughput to provide operands to functional units and absorb their results. The vector processor's VRF consists of a set of single-port memory banks 201a-1. The width of each memory bank 201a-1 is limited to the data path width of each channel, i.e., 64 bits, to avoid subword select logic errors. Therefore, in steady state, five memory banks 201a-1 can be accessed simultaneously to maintain the predetermined maximum throughput of multiply-accumulate instructions. Each channel of the vector processor's VRFs 201a is configured with eight banks to provide some margin for access.

[0060] When several functional units attempt to access operands in the same bank, bank conflicts occur. Each extended channel module 200 has a set of operand queues 201b between the VRF and the various functional units to absorb such bank conflicts. In this embodiment, there are 12 operand queues 201b: 4 dedicated to the FPU / MUL (Floating-Point Processing Unit 202d / Multiplication Unit 202c), 3 to the ALU (Arithmetic Logic Unit 202b), 3 to the VLSU (Vector Load / Store Unit), and 2 queues for the systolic array acceleration unit 202a. Each queue is 64 bits wide, and their depth is selected through simulation, depending on the latency and throughput of the functional units.

[0061] like Figure 3 As shown, the computational processing unit 202 includes an integer ALU (Arithmetic Logic Unit 202b), an integer MUL (Multiplication Unit 202c), and an FPU (Floating-Point Unit 202d), all operating on a 64-bit data path to perform basic scalar arithmetic functions. The MUL and FPU share the operand queue 201b, but they cannot use each other simultaneously. The vector processor provides full support for multi-precision arithmetic, allowing data conversion from 8 bits to 16 bits, from 16 bits to 32 bits, and from 32 bits to 64 bits. The FPU is configured to support FMAs (Floating-Point Multiply-Accumulate), addition, multiplication, division, square root, and comparison.

[0062] The pulsating array unit is specifically designed to handle operations between vectors, thereby significantly improving the vector processing capability of the vector processor. Figure 4The working principle of the systolic array acceleration unit 202a is demonstrated. The systolic array acceleration unit 202a consists of multiple identically constructed processing elements (PEs), operating in a pipeline-like manner. Each processing element calculates the incoming data and temporarily stores a partial sum. In the next clock cycle, it broadcasts the specified data to adjacent processing elements in a specified direction. In the systolic array adapted for matrix multiplication calculations, the processing elements selectively broadcast input data to adjacent processing elements.

[0063] In many cases, the overall system's processing power is limited by memory access bandwidth rather than computational power. Figure 5 As can be seen, this allows systolic arrays to better utilize limited memory access bandwidth without wasting computational power compared to traditional multiplication tree architectures. By using systolic transmission combined with data broadcasting, systolic arrays perform more efficient data reuse, enabling them to achieve high computational throughput without significantly increasing storage space.

[0064] In this embodiment, when the systolic array acceleration unit 202a receives a request from the VRF within the channel to input data into the systolic array, the control unit inside the systolic array acceleration unit 202a automatically inputs the data sequentially into buffer A and buffer B. After the data loading is complete, the unit determines whether to start calculation based on the input pattern. After the calculation is completed, the data is automatically stored in the output buffer, waiting for instructions to output the calculation result to the VRF.

[0065] like Figure 2 As shown, the load-store module 300 in this embodiment includes a data loading unit 301 and a data storage unit 302. These are used to load data to be processed from external sources and to store calculation results from the VRF into external memory, respectively. When the starting address in the operation instruction is passed to the data loading unit 301, this unit aggregates the unit's memory operations into a burst request, avoiding the need to request individual elements from memory. Then, the burst start address and burst length are sent to the load or storage unit, which is responsible for initiating data transmission through the Advanced Extensible Interface (AXI) of the Vector Processing Unit. The data loading unit 301 loads data via the AXI AR bus, and the data storage unit 302 uses the AXI AW bus to store data.

[0066] In this embodiment, the operation instructions are custom instructions, all of which are vector instructions, including vector calculation instructions, vector loading instructions, and vector storage instructions. The custom instructions include target address information and action information; the custom instructions are input from outside into the processing module for processing.

[0067] The vector computation instruction is a custom VMSAM instruction, while the vector loading instruction VL*E and the vector storage instruction VS*E are both RISC-V instructions, and both can be customized.

[0068] The RISC-V instruction set is an open instruction set architecture (ISA) built upon the principles of Reduced Instruction Set Computing (RISC). RISC-V is a completely new instruction set built upon the continuous development and maturation of instruction sets. The RISC-V instruction set is completely open source, simple in design, easy to port to Unix systems, modular in design, has a complete toolchain, and numerous open-source implementations and chip fabrication examples.

[0069] RISC-V is a modular reduced instruction set architecture, consisting of a basic integer instruction set represented by the letter I and extended instruction sets represented by the letters M, A, F, D, and C. The only instruction set that must be implemented is the basic integer instruction set (type I), which allows for the implementation of a complete software compilation toolchain. The extended instruction sets add features such as multiplication and division, atomic memory operations, and floating-point operations; all of these instruction sets can be selected and configured as needed.

[0070] While RISC-V was not the first open-source instruction set architecture (ISA), it was the first designed to be appropriately selected based on specific scenarios. Processors for various applications, such as server CPUs, home appliance CPUs, and sensor CPUs, can be designed based on the RISC-V instruction set architecture.

[0071] like Figure 6 As shown, the custom VMSAM instruction belongs to the vector processing instruction category; after entering the vector processing unit, the state input and calculation accuracy of the pulsating array accelerator are obtained by decoding the value of rs1 to drive the module to start running; the instruction will only end when the calculation is completed.

[0072] like Figure 7 As shown, the VL*E instruction belongs to the vector loading instruction class; after entering the vector processing unit, the target functional unit is the VRF in the extended channel module 200; the value of vs1 is decoded externally as the starting address of the AR line in the AXI bus; rs2 is the identifier of the method by which the data will be retrieved from memory, and rd is the starting address of the data stored in the VRF.

[0073] The VS*E instruction belongs to the vector storage instruction class; after entering the vector processing unit, the target functional unit is the VRF in the channel; the value of vs1 is decoded externally as the starting address of the AW line in the AXI bus; rs2 is the identifier of the method from which data will be retrieved from the VRF, and rd is the starting address of the data stored in memory.

[0074] like Figure 8 This demonstrates the process of executing instructions for data processing in a vector processor:

[0075] 1. After the vector processor receives the decoded VLE instruction, data is read from the AR line of the AXI bus according to the starting address order. When the data reading is complete, it is loaded into the VRF within the channel. When the data transmission is complete, the instruction execution ends.

[0076] 2. After the VMSAM instruction begins, the decoded rs1 specifies the starting address for reading data from the VRF, rs2 specifies the operating mode and quantization precision of the systolic array acceleration unit 202a, and rd specifies the starting address for storing the result in the VRF. When the systolic array acceleration unit 202a receives the start signal, data is fed into the systolic array. After the calculation is completed, the instruction execution ends.

[0077] 3. After the VSE command is initiated, data is loaded from the VRF within the channel onto the AW line of the AXI bus. The command ends when a transmission of a specific length is completed.

[0078] As an alternative implementation, since the design of custom instructions has a certain degree of flexibility, different from the three specific instructions proposed in this embodiment can be used to guide and control the various functional units in the processor.

[0079] Example 3

[0080] Reference Figure 9 The illustration shows a schematic flowchart of a data processing method applicable to an embodiment of this application, which mainly includes the following steps:

[0081] The control module 100 receives operation commands from external sources;

[0082] The control module 100 parses the operation instructions to obtain vector calculation instructions and vector storage loading instructions, as well as a functional unit to determine the transmission of the vector calculation instructions;

[0083] The loading storage module 300 loads the data to be processed from an external source according to the vector storage loading instruction;

[0084] The pulse array acceleration unit 202a in the extended channel module 200 retrieves corresponding data from the channel storage unit 201 according to the vector calculation instruction, performs vector calculations, and returns the calculation results to the channel storage unit 201 for storage; the calculation results stored in the channel storage unit 201 are transmitted to the outside through the loading storage module 300.

[0085] Specifically, this embodiment uses standard R-type instructions used to operate on the destination and source registers as examples to demonstrate the workflow of various instructions after entering the vector processor as follows:

[0086] The data flow diagram for the VL*E instruction is as follows:

[0087] 1. Input command to external decoder: 32'h 0000 1101 1010 0111 1111 1001 0101 0111

[0088] This is a vector instruction obtained from the first-level decoding and should be passed to the vector processor for processing. Meanwhile, the value of rs1 is 0F.

[0089] The value stored at this address is 32'h 8000 0004, and the rd value is 12. This information is also passed into the vector.

[0090] 2. When the vector receives the instruction and other information, it sends them to the instruction distribution unit 101 for secondary decoding. The instruction distribution unit 101 identifies this as a data load instruction (VLE) based on the instruction's opcode. Simultaneously, it loads the rs1 and rs2 values, as well as the decoded address value, and sends this data and the instruction to the main sequencing unit 102. Feedback to the external decoder confirms no errors.

[0091] 3. After checking that there are no hazards between the instruction and other instructions, the main sequencing unit 102 broadcasts the instruction and information to all functional units, but only the data loading unit 301 receives it. The data loading unit 301 sends a data loading request to the AR line of the AXI bus based on the starting address information and the transmission length information. After the data loading is completed, the loading unit transmits the data to the VRF in the Lane, with the storage address being the rd value. When the data is completely loaded into the VRF, the VLE instruction execution ends.

[0092] VMSAM instruction execution data flow diagram:

[0093] 4. Input command to external decoder: 32'h 1010 1010 1001 0001 1010 0000 0101 0111

[0094] This is a vector instruction obtained from the first-level decoding and should be passed to the vector processor for processing.

[0095] 5. When the vector processor receives the instruction and other information, it sends them to the instruction dispatch unit 101 for secondary decoding. The instruction dispatch unit 101 identifies this as the data processing instruction VMSAM based on the instruction's opcode. Simultaneously, it loads the rs1, rs2, and rd values ​​and sends these data along with the instruction to the main sequencing unit 102. Feedback to the external decoder indicates no errors.

[0096] 6. After checking that there are no hazards between the instruction and other instructions, the main sequencing unit 102 broadcasts the instruction and information to all functional units, but only each channel and the pulse array acceleration unit 202a in the channel receive it. Based on the starting address in rs1 and the mode state input contained in rs2, the rs2 value is decoded to obtain an input precision of 64 bits. The functional unit begins to retrieve data from the VRF and determines whether to start calculation based on the input state. After the calculation is completed, the result is stored in the output buffer. Using rd as the starting address, the value in the output buffer is stored in the VRF. When the data is completely loaded into the VRF, the VMSAM instruction execution ends.

[0097] VS*E instruction execution data flow diagram:

[0098] 7. Input command to external decoder: 32'h 0000 0010 0000 1101 1111 0000 0010 0111

[0099] This is a vector instruction obtained from the first-level decoding and should be passed into the vector for processing. Simultaneously, the rs1 value is 1B, which, when decoded in the external decoder, reveals that the value stored at this address is 32'h 80042380, and the rd value is 00. This information should also be passed into the vector.

[0100] 8. When the vector processor receives the instruction and other information, it sends them to the instruction dispatch unit 101 for secondary decoding. The instruction dispatch unit 101 identifies this as a data storage instruction (VSE) based on the instruction's opcode. Simultaneously, it loads the rs1 and rd values, as well as the decoded address value, and sends this data and the instruction to the main sequencing unit 102. Feedback to the external decoder indicates no errors.

[0101] 9. After checking that there are no hazards between the instruction and other instructions, the main sequencer 102 broadcasts the instruction and information to all functional units, but only the data storage unit 302 receives it. The data storage unit 302 sends a data storage request to the AW line of the AXI bus based on the decoded starting address information and transmission length information. After data storage is completed, the AW line returns a termination signal to the instruction sequencer. When the data is completely loaded into the AXI AW line, the VSE instruction execution ends.

[0102] Those skilled in the art will clearly understand that the techniques in the embodiments of this application can be implemented using software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solutions in the embodiments of this application, or the parts that contribute to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application or some parts of the embodiments.

[0103] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the service building apparatus and service loading apparatus embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

[0104] The embodiments described above do not constitute a limitation on the scope of protection of this application.

Claims

1. A vector processor supporting multi-precision calculation and dynamic configuration, characterized in that, include: The control module (100) is used to receive externally input operation instructions, parse the operation instructions to obtain vector calculation instructions and vector storage loading instructions, and determine the function unit to send the vector calculation instructions. A loading storage module (300) is used to load data to be processed from an external source according to the vector storage loading instruction; An extended channel module (200) includes a channel storage unit (201) and a pulsating array acceleration unit (202a). The channel storage unit (201) stores the data to be processed. The pulsating array acceleration unit (202a) retrieves corresponding data from the channel storage unit (201) according to the vector calculation instructions, performs vector calculations, and returns the calculation results to the channel storage unit (201) for storage. The calculation results stored in the channel storage unit (201) are transmitted to the outside through the loading storage module (300). The extended channel module (200) includes a channel instruction sequencing unit (203), a channel storage unit (201), and several computing processing units (202), wherein the computing processing unit (202) includes the pulsating array acceleration unit (202a); The channel storage unit (201) includes a vector register file (201a) and an operand queue (201b). The vector register file (201a) is used to provide operands for the functional units and absorb their results. The operand queue (201b) connects the computing processing unit (202) and the vector register file (201a) and is used to allocate operands for each of the computing processing units (202).

2. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1, characterized in that: The control module (100) includes an instruction distribution unit (101) and a main sequencing unit (102). The instruction distribution unit (101) receives externally transmitted operation instructions, processes the operation instructions, identifies the type of operation instructions and the corresponding functional unit, and transmits the operation instructions to the main sequencing unit (102). The main sequencing unit (102) broadcasts the instructions to all functional units and monitors the running status of the instructions.

3. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1, characterized in that: The vector register file (201a) includes several memory banks and an arbitration unit (201a-2). The memory banks are single-port and have a bit width of 64 bits. Each vector register file (201a) has 8 memory banks (201a-1) for loading and transmitting data to be processed and calculation results. The arbitration unit (201a-2) is used to allocate the priority of each operation instruction.

4. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1, characterized in that: The channel instruction sequencing unit (203) is used to send operation instructions to each functional unit in the extended channel module (200) and initiate a request to read operands from the vector register file (201a).

5. The vector processor supporting multi-precision calculation and dynamic configuration according to claim 1 or 3, characterized in that: After receiving a data reading request from the vector register file (201a), the pulse array acceleration unit (202a) automatically inputs the data to be processed into the buffer in sequence, and determines whether to start calculation based on the input mode after loading is completed. The calculation result is automatically stored in the output buffer and waits for the instruction to output the result back to the vector register file (201a).

6. The vector processor supporting multi-precision calculation and dynamic configuration according to any one of claims 1-4, characterized in that: The operation instructions are custom instructions, all of which are vector instructions, including vector calculation instructions, vector loading instructions, and vector storage instructions. The custom instructions include target address information and action information; the custom instructions are processed from an external input vector processor.

7. The vector processor supporting multi-precision calculation and dynamic configuration according to any one of claims 1-4, characterized in that: The loading and storage module (300) includes a data loading unit (301) and a data storage unit (302). The data loading unit (301) loads data via an AXI AW bus, and the data storage unit (302) uses an AXI AW bus to store data.

8. A processing method supporting multi-precision calculation and dynamic configuration, applied to the vector processor described in any one of claims 1 to 7, characterized in that: include, The control module (100) receives operation commands from external sources; The control module (100) parses the operation instructions to obtain vector calculation instructions and vector storage loading instructions, as well as a functional unit that determines the transmission of the vector calculation instructions; The loading storage module (300) loads the data to be processed from the outside according to the vector storage loading instruction; The pulse array acceleration unit (202a) in the extended channel module (200) retrieves corresponding data from the channel storage unit (201) according to the vector calculation instruction, performs vector calculations, and returns the calculation results to the channel storage unit (201) for storage; the calculation results stored in the channel storage unit (201) are transmitted to the outside through the loading storage module (300).

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