Multi-target blur detection system based on focal plane array decoded data
By introducing fuzzy detection and membership concepts into the focal plane array testing system, the efficiency and accuracy issues of multi-target detection in focal plane arrays are solved, enabling efficient target detection and flexible application in non-ideal environments.
Patent Information
- Application Number
- CN202211656853.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-12-22
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2042-12-22
AI Technical Summary
Existing focal plane array testing systems struggle to efficiently detect multiple targets when decoding data, and noise interference and single threshold detection in non-ideal environments lead to inaccurate detection rates.
Design a multi-target fuzzy detection system. Utilize an FPGA for timing control, decode and preprocess the focal plane array data through an ARM processor in a fully programmable SoC, use fuzzy sets and membership concepts to determine targets, and output the membership degree of suspected targets.
It improves system maintainability and frame rate, reduces the impact of noise interference, provides more target information feedback, and is suitable for complex application scenarios.
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Figure CN115937337B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of electronic product testing technology and relates to a multi-target fuzzy detection system based on focal plane array decoding data. Background Technology
[0002] Focal plane arrays can be used in fields such as 3D imaging and target detection. During the testing phase of a focal plane array, the testing system emits laser pulses to the target, uses photoelectric detection technology to receive the echoes, and uses readout circuit technology to encode the time-of-flight data of photons received by each pixel of the focal plane array. The encoded results are then processed by the data acquisition system.
[0003] The data acquisition system decodes data according to the time-of-flight encoding rules. Traditional decoding methods use FPGAs, where developers write glue logic into the FPGA during the data acquisition system design phase. During testing, after a single frame of data is acquired, the FPGA decodes the data and uses the glue logic to piece the data together according to certain rules to reconstruct the time of flight. However, this method has two drawbacks: First, designing the glue logic using an FPGA is challenging and requires repeated downloads of the FPGA program, resulting in poor maintainability; second, the FPGA also handles the timing control tasks for the focal plane array counting stage, meaning it cannot count the time of flight for the next frame while using the glue logic to piece together the data, thus limiting the frame rate of data acquisition in the application scenario.
[0004] Depending on the specific optical system, time-of-flight can be converted into target distance information. When the focal plane array acquires enough data, the time-of-flight data will form a certain statistical distribution. Theoretically, target detection can be achieved by detecting the peak value of the time-of-flight. However, in practical applications, the following problems arise: First, noise interference caused by the non-ideal nature of the testing system and application environment makes the single peak detection algorithm less accurate due to noise effects; second, traditional target detection algorithms set a single threshold, using a one-size-fits-all approach to determine whether a peak value corresponds to a detected target, which affects the detection rate in complex application scenarios. Summary of the Invention
[0005] (a) Technical problems to be solved
[0006] The technical problem to be solved by this invention is: how to design a focal plane array multi-target detection system that can efficiently decode the acquired data and continue to detect targets while decoding; how to find the time-of-flight count peaks corresponding to multiple detected targets based on the statistical distribution of the decoded data; and how to use the concept of fuzzy sets to determine whether the time-of-flight count peaks correspond to the detected targets for user applications of focal plane arrays, quantitatively assess the possibility that a suspected target is a real target, and provide more references for user applications.
[0007] (II) Technical Solution
[0008] To address the aforementioned technical problems, this invention provides a design method for a multi-target fuzzy detection system based on focal plane array decoded data. The multi-target fuzzy detection system is designed to include an FPGA and a computer. The FPGA is designed to apply timing control to the focal plane array. The acquired output signal of the focal plane array readout circuit is packaged into raw data and sent to the computer via the ARM in the fully programmable SoC. This raw data is the focal plane array data. The computer is designed to include four modules: a data decoding module, a post-decoding data preprocessing module, a target detection module, and a target membership output module. These modules are used sequentially to perform data decoding, post-decoding data preprocessing, target detection, and target membership output on the acquired focal plane array data. The system presents information about multiple detected targets to the user and outputs membership values for suspected targets.
[0009] The method as described in claim 1 is characterized in that the FPGA is designed to receive the output signal of the focal plane array readout circuit in parallel under the control of the readout clock using its multiple I / O pins. After the single frame data is transmitted to the ARM via the AXI bus, it is directly packaged into an array and sent to the computer.
[0010] Preferably, the computer's data decoding module is designed to: extract specific binary bits from the array according to the encoding rules of the focal plane array readout circuit, concatenate them into a two-dimensional array corresponding to the image data in the focal plane array, and decode according to the encoding table of LFSR and clock phase shift.
[0011] Preferably, the computer's post-decoding data preprocessing module is designed as follows: under continuous detection, the received data is statistically distributed and preprocessed, a multinomial fitting algorithm is used to fit the data, the baseline of the statistical distribution is calculated, and then the quotient of each count value and the standard deviation of all data is calculated to obtain new data that is convenient for target detection.
[0012] Preferably, the computer's target detection module is designed to set a fuzzy set for the detected target, perform peak detection on the statistical distribution of the new data, and the computer's target membership output module is designed to: calculate the membership degree using a membership function based on the peak detection result and according to the lower and upper limits set by the user, give the determined target and the suspected target, and output the membership degree of the suspected target to the user.
[0013] The present invention also provides a multi-target fuzzy detection system designed using the method described above.
[0014] The present invention also provides a method for multi-target fuzzy detection using the aforementioned system.
[0015] (III) Beneficial Effects
[0016] This invention proposes a multi-target fuzzy detection system based on focal plane array decoded data. It aims to optimize the testing and application process of focal plane arrays, improve the maintainability of the testing system, facilitate target detection for users while ensuring a certain frame rate, and provide users with more target information in more complex and non-ideal application environments by using fuzzy detection, thus providing greater flexibility for subsequent information processing.
[0017] Compared to traditional methods of implementing glue logic using only FPGAs, the system proposed in this invention has a clearer division of hardware functions. The FPGA is used only for timing control, while the functions of traditional glue logic are allocated to the computer. This design approach is clearer and improves system maintainability while ensuring a certain data acquisition frame rate.
[0018] For continuously collected large amounts of data, a statistical distribution can be calculated. Traditional target detection typically employs a single peak detection algorithm, determining whether a peak corresponds to a target by setting a threshold, suitable for ideal application scenarios. However, in non-ideal environments, influenced by factors such as optical system performance and application environment, the multi-target fuzzy detection algorithm proposed in this invention reduces the impact of noise by detecting the baseline of the statistical distribution and introduces the concepts of fuzzy sets and membership degrees to provide users with more information about the detected target. Compared to traditional target detection algorithms, the system proposed in this invention allows users to perform in-depth and flexible processing in complex application scenarios, improving the system's detection rate. Attached Figure Description
[0019] Figure 1 This is a general block diagram of the multi-target fuzzy detection system used in this invention;
[0020] Figure 2 This is a flowchart of the data preprocessing algorithm after decoding;
[0021] Figure 3This is a schematic diagram of the multi-target detection results;
[0022] Figure 4 This refers to the S-function used as the membership function in the membership output module. Detailed Implementation
[0023] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0024] To address the complex scenarios and non-ideal conditions encountered during the testing and application of focal plane arrays (FLAS), this invention proposes a data decoding method for FLAS that is easy to develop and maintain. During data decoding, the FLAS can continue to detect targets, ensuring the system's frame rate. The method calculates the statistical distribution of the decoded time-of-flight data and preprocesses it, using a multinomial fitting algorithm to eliminate the influence of background noise and other factors. Peak detection is then used to locate the detected targets. This invention treats potential targets as fuzzy sets, and by calculating and outputting the membership degree of the statistical distribution peaks to the target fuzzy set, it improves the flexibility of users in applying FLAS and ensures a certain detection rate.
[0025] System overall architecture:
[0026] For the testing and application of focal plane arrays, the overall system structure proposed in this invention is as follows: Figure 1 As shown, the FPGA is used to apply timing control to the focal plane array. The acquired readout circuit output signals are packaged by the ARM processor in the fully programmable SoC and sent directly to the computer as raw data. The computer's internal data processing is divided into four modules: a data decoding module, a post-decoding data preprocessing module, a target detection module, and a target membership output module. By performing the above processing on the acquired focal plane array data, information on multiple detected targets is presented to the user, and membership values are output for suspected targets, allowing for more flexible subsequent processing by the user.
[0027] 1. Focal Plane Array Data Decoding Method
[0028] When the focal plane array is operating, the FPGA receives signals from the focal plane array readout circuit in parallel through multiple I / O pins (configured in input mode). Under the action of the readout clock, the FPGA continuously receives signals until a single frame of signal has been received.
[0029] The single-frame signal received by the FPGA can be represented as the following matrix:
[0030]
[0031] In the matrix, element b (byte number, bit number) represents the signal received by the FPGA's I / O pin, with a value of 0 or 1. During each readout clock cycle, the FPGA reads one column of signals in the matrix in parallel. Since the maximum bit width of the AXI bus in a fully programmable SoC is 32 bits, this matrix contains 32 rows, allowing the FPGA to read signals from 32 I / O pins simultaneously.
[0032] In a computer system, one byte contains eight binary bits. Therefore, after the FPGA transmits the output signal of the focal plane array readout circuit to the ARM via the AXI bus, the ARM packages the signal into a one-dimensional array with byte-type data elements as follows: Eight binary bits with the same byte number and bit numbers 0-7 are grouped into one byte and stored at the corresponding address in the one-dimensional array. That is, b(0,0), b(0,1), ..., b(0,7) form one byte and are stored at the address with index 0 in the one-dimensional array; b(1,0), b(1,1), ..., b(1,7) form one byte and are stored at the address with index 1 in the one-dimensional array, and so on. The ARM transmits the packaged one-dimensional array to the computer via the Ethernet interface for data decoding.
[0033] The data decoding method involves extracting consecutive binary bits with the same bit number (located in the same row of the matrix) and reconstructing the time-of-flight measured by the focal plane array using a lookup table. The number of consecutive binary bits extracted corresponds to the number of D flip-flops used for counting the time of flight of a single pixel in the readout circuit, which is specified by the focal plane array readout circuit designer. Typically, 14 consecutive bits in the same row of the matrix represent the output signal of a single pixel, i.e., b(0,0), b(4,0), ..., b(52,0) represent the pixel in the first row and first column, b(0,1), b(4,1), ..., b(52,1) represent the pixel in the second row and first column, b(56,0), b(60,0), ..., b(108,0) represent the pixel in the first row and second column, and so on. For a typical two-stage encoding rule, the 14 binary bits are represented by an 11-bit linear feedback shift register (LFSR) for coarse counting and by a 3-bit clock phase shift for fine counting. The encoding tables for coarse and fine counts are stored in the computer. After the computer obtains the output signal representing each pixel, it directly looks up the encoding table for each pixel to obtain the coarse and fine counts. By merging the coarse and fine counts, the flight time can be restored.
[0034] 2. The data preprocessing module performs the following preprocessing steps after decoding:
[0035] The preprocessing procedure for the decoded data is as follows: Figure 2As shown. In the case of continuous detection, the computer calculates the statistical distribution of the large amount of received time-of-flight data, uses a multinomial fitting algorithm to find the baseline of the statistical distribution, subtracts the baseline, and calculates the quotient of each count value with the standard deviation of all count values to obtain the statistical distribution of new data that can be used for target detection.
[0036] The statistical distribution of the frequency of all flight time data within the distance gate is denoted as {c}. t}, where element c t Let $t$ represent the frequency of the flight time count value $t$. $t$ iterates through all flight time count values within the distance gate. Let $n$ be the number of elements in the sequence ${t}$. t Theoretically, the t-value corresponding to the target should exhibit a peak in the statistical distribution, with most other count values being 0. However, in actual testing and applications, due to factors such as environmental noise and backscattering caused by non-ideal optical systems, the focal plane array exhibits dark counts, causing fluctuations in the baseline of the statistical distribution. Therefore, after finding the baseline of the statistical distribution using a polynomial fitting algorithm, the measured value is subtracted from the baseline to eliminate the influence of dark counts.
[0037] Since t is an integer, its order of magnitude can reach up to 10 in typical application scenarios. 4 To obtain polynomial fitting coefficients that are easy to calculate numerically, the data is processed as follows:
[0038]
[0039] Where t and σ t These represent the mean and standard deviation of all flight time data, respectively. Used for polynomial fitting, to obtain polynomial coefficients p1, p2, ..., p9 (preferably, an 8th-order polynomial is used, so there are 9 coefficients).
[0040] The sequence obtained by subtracting the baseline from the count values corresponding to all t is {d} t}, use the following formula to complete the baseline subtraction calculation:
[0041]
[0042] Substituting d into the above formula t The expression is used to calculate the quotient of each count value after baseline subtraction and the standard deviation of all count values to obtain new data:
[0043]
[0044] In the above formula, σ is {d t Standard deviation of}
[0045]
[0046] In the formula,
[0047]
[0048] The sequence {x} of new data obtained according to formulas (4) to (6) t} represents the statistical distribution of the new data. In this way, regardless of the order of magnitude of the measured flight time, a consistent standard can be used to determine the target in subsequent target detection.
[0049] 3. Peak detection is performed using a target detection module, and membership is calculated using a target membership output module, as detailed below:
[0050] For the sequence {x} obtained by the decoded data preprocessing module t Perform peak detection and find {x} t The maximum value in a statistical distribution. Based on the user-defined lower limit (λ). 下限 ) and upper limit (λ) 上限 ), determine whether these maxima are detected targets. If x t If the value is below the lower limit, then the corresponding peak value is not the detected target; if x t If it exceeds the upper limit, the corresponding peak value is determined as the target; if x t If the value falls between the lower and upper limits, the corresponding peak value is considered a suspected target.
[0051] Figure 3 This is a typical statistical distribution chart of time-of-flight data. Targets and suspected targets identified according to the above target detection criteria are marked on the chart. This invention treats potential targets as fuzzy sets, introduces the concept of membership degree, and develops a membership degree output module to provide users with more information about the detected targets. The membership function used is the S-function:
[0052]
[0053] In the formula, λ 下限 Set to 2.5~3.0, λ 上限 Set it to 5.5-6.0. For example... Figure 4 As shown, x below the lower limit t A membership degree of 0 indicates that the peak value is not the target; x values above the upper limit... t A membership degree of 1 indicates that the peak value is considered a target; x, which lies between the lower and upper bounds... t The membership degree is between 0 and 1, quantitatively representing such x t The possibility of becoming a true target. Users can refer to the target membership degree output by this invention to conduct subsequent testing and data processing in a more flexible manner according to the actual application scenario.
[0054] Based on the above principles, such as Figure 1 , Figure 2 , Figure 3 , Figure 4 As shown, this embodiment of the invention provides the design and operation process of a multi-target blur detection system based on focal plane array decoding data, including the following steps:
[0055] S1. Determine the overall system architecture. In this invention, the FPGA is only responsible for applying timing control to the focal plane array. The output signal of the acquired focal plane array readout circuit is packaged by the ARM in the fully programmable SoC and sent directly to the computer as raw data. The internal data processing of the computer is divided into four modules: data decoding module, post-decoding data preprocessing module, target detection module, and target membership output module. Subsequently, the computer performs data decoding, post-decoding data preprocessing, target detection, and target membership output on the acquired focal plane array data. The information of multiple detected targets is presented to the user, and the membership degree of suspected targets is output for the user to perform more flexible subsequent processing.
[0056] S2. Multiple I / O pins of the FPGA (configured in input mode) receive the output signals of the focal plane array readout circuit in parallel under the control of the readout clock. After a single frame of data is transmitted to the ARM via the AXI bus, it is directly packaged into an array and sent to the computer. The computer extracts specific binary bits from the array according to the encoding rules of the focal plane array readout circuit, splices them into a two-dimensional array corresponding to the image data in the focal plane array, and decodes it according to the encoding table of LFSR and clock phase shift.
[0057] S3. In the case of continuous detection, the computer calculates the statistical distribution of the large amount of data received and performs data preprocessing. It uses a multinomial fitting algorithm to fit the data, calculates the baseline of the statistical distribution, and then calculates the quotient of each count value and the standard deviation of all data to obtain new data that is convenient for target detection.
[0058] S4. Set a fuzzy set for the target to be detected. Perform peak detection on the statistical distribution of the new data calculated above. According to the user-defined lower limit (2.5~3.0) and upper limit (5.5~6.0), use the S-function as the membership function to calculate the membership degree, give the confirmed target and the suspected target, and output the membership degree of the suspected target to the user.
[0059] As can be seen, this invention, based on the background technology of focal plane array testing and application, proposes a multi-target fuzzy detection system based on focal plane array decoded data. This system uses a computer to share the tasks of the FPGA glue logic, employing computer programming technology to decode the data acquired by the focal plane array, enabling the FPGA to simultaneously perform target detection in the next frame. After calculating the statistical distribution of the decoded data and performing data preprocessing, new data suitable for peak detection is obtained. The concept of fuzzy sets is introduced for potential targets, outputting the membership degree of the suspected target to the fuzzy set, allowing users to flexibly determine whether the detected signal is a target based on the actual application scenario.
[0060] Compared with traditional focal plane array testing techniques, the multi-target blur detection system based on focal plane array decoding data proposed in this invention adopts a clearer design concept and ensures a certain imaging frame rate and detection rate for complex and ever-changing application scenarios.
[0061] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A multi-target blur detection system based on focal plane array decoded data, characterized in that, The multi-target fuzzy detection system includes an FPGA and a computer. The FPGA is responsible for applying timing control to the focal plane array. The acquired output signal of the focal plane array readout circuit is packaged by the ARM in the fully programmable SoC and sent to the computer as raw data. This raw data is the focal plane array data. The computer includes four modules: a data decoding module, a data preprocessing module, a target detection module, and a target membership output module. These modules are used to perform data decoding, data preprocessing, target detection, and target membership output on the acquired focal plane array data, respectively. The system presents the information of multiple detected targets to the user and outputs the membership degree of suspected targets. The computer's data decoding module extracts specific binary bits from the array according to the encoding rules of the focal plane array readout circuit, splices them into a two-dimensional array corresponding to the image data in the focal plane array, and decodes and restores the time of flight measured by the focal plane array according to the encoding table of LFSR and clock phase shift. After decoding, the computer's data preprocessing module calculates the statistical distribution of the large amount of received time-of-flight data under continuous detection. It uses a multinomial fitting algorithm to find the baseline of the statistical distribution. After subtracting the baseline, it calculates the quotient of each count value and the standard deviation of all count values to obtain the statistical distribution of new data that can be used for target detection. The computer's target detection module sets a fuzzy set for the detected target and performs peak detection on the statistical distribution of the new data. The computer's target membership output module is designed to: calculate the membership degree using a membership function based on the peak detection result and according to the user-defined lower and upper limits, provide the definite target and the suspected target, and output the membership degree of the suspected target to the user. The data preprocessing module performs the following preprocessing steps after decoding: The frequency distribution of all flight time data within the distance gate is denoted as { c t }, where elements c t Represents flight time count value t Frequency of occurrence t Iterate through all flight time counts within the distance gate, in sequence { t The number of elements in} is denoted as n t After finding the baseline of the statistical distribution using a multinomial fitting algorithm, the measured value is subtracted from the baseline. t Since the coefficients are integers, the data is processed as follows to obtain polynomial fitting coefficients that are easy to calculate numerically: (1) in, and σ t The mean and standard deviation of all flight time data are respectively; all Used for polynomial fitting to obtain polynomial coefficients. p 1, p 2, …, p 9; all t The sequence obtained by subtracting the baseline from the corresponding count value is { d t }, use the following formula to complete the baseline subtraction calculation: (2) Substituting into the above formula d t The expression is used to calculate the quotient of each count value after baseline subtraction and the standard deviation of all count values to obtain new data: (3) In the above formula σ for{ d t Standard deviation of} (4) In the formula, (5) The sequence of new data obtained according to formulas (3) to (5) { x t } represents the statistical distribution of the new data.
2. The system as described in claim 1, characterized in that, The FPGA uses its multiple I / O pins to receive the output signals of the focal plane array readout circuit in parallel under the control of the readout clock. After a single frame of data is transmitted to the ARM via the AXI bus, it is directly packaged into an array and sent to the computer.
3. A method for multi-target fuzzy detection using the system described in claim 1 or 2, characterized in that, Includes the following steps: S1. Multiple I / O pins of the FPGA receive the output signals of the focal plane array readout circuit in parallel under the control of the readout clock. After a single frame of data is transmitted to the ARM via the AXI bus, it is directly packaged into an array and sent to the computer. The data decoding module extracts specific binary bits from the array according to the encoding rules of the focal plane array readout circuit, splices them into a two-dimensional array corresponding to the image data in the focal plane array, and decodes it according to the encoding table of LFSR and clock phase shift. S2. In the case of continuous detection, the data preprocessing module after decoding calculates the statistical distribution of the large amount of received data and performs data preprocessing. It uses a multinomial fitting algorithm to fit the data, calculates the baseline of the statistical distribution, and then calculates the quotient of each count value and the standard deviation of all data to obtain new data that is convenient for target detection. S3. The target detection module sets a fuzzy set for the detected target and performs peak detection on the statistical distribution of the new data. The target membership output module calculates the membership degree based on the peak detection result and the user-defined lower and upper limits using a membership function, providing the confirmed target and suspected target, and outputting the membership degree of the suspected target to the user.
4. The method as described in claim 3, characterized in that, When the focal plane array is working, the FPGA receives the signals output by the focal plane array readout circuit in parallel through multiple I / O pins. Under the action of the readout clock, the FPGA continuously receives signals until a single frame of signal is received. The single-frame signal received by the FPGA is represented by the following matrix: (6) Elements in the matrix b (Byte number, bit number) represents the signal received by the FPGA's I / O pin, with a value of 0 or 1; in each cycle of the readout clock, the FPGA reads one column of signals in the matrix in parallel. The maximum bit width of the AXI bus in the fully programmable SoC is 32 bits, so the matrix contains 32 rows, and the FPGA can read the signals of 32 I / O pins at the same time. After the FPGA transmits the output signal of the focal plane array readout circuit to the ARM via the AXI bus, the ARM packages the signal into a one-dimensional array with byte-type data elements as follows: Eight binary bits with the same byte number and bit numbers 0-7 are grouped into one byte and stored at the corresponding address in the one-dimensional array. b (0,0), b (0,1), …, b (0,7) form a byte, which is stored at the address of index 0 in a one-dimensional array; b (1,0), b (1,1), …, b (1,7) form a byte, which is stored at the address of index 1 in the one-dimensional array, and so on; the ARM transmits the packaged one-dimensional array to the computer through the Ethernet interface for data decoding; The data decoding method in step 1 involves extracting multiple consecutive binary bits with the same bit number and reconstructing the flight time measured by the focal plane array using a lookup table. The number of extracted consecutive binary bits corresponds to the number of D flip-flops used for counting the flight time of a single pixel in the readout circuit. The 14 consecutive bits in the same row of the matrix represent the output signal of a single pixel. b (0,0), b (4,0), …, b (52,0) represents the cell in the first row and first column. b (0,1), b (4,1), …, b (52,1) represents the cell in the 2nd row and 1st column. b (56,0), b (60,0), …, b (108,0) represents the cell in the 1st row and 2nd column, and so on. For the two-segment encoding rule, the 14 binary bits are represented by an 11-bit linear feedback shift register (LFSR) for coarse counting and by a 3-bit clock phase shift for fine counting. The encoding tables for coarse and fine counting are stored in the computer. After the computer obtains the output signal representing each cell, it directly looks up the encoding table for each cell to obtain the coarse and fine counts. By merging the coarse and fine counts, the time of flight can be restored.
5. The method as described in claim 4, characterized in that, In step S3, the target detection module is used to detect peak values, and the target membership output module is used to calculate membership degrees, as follows: The target detection module processes the sequence obtained by the decoded data preprocessing module. x t Peak detection is performed, and the target membership output module searches for { x t The maximum value in the statistical distribution is determined by the lower limit set by the user. λ 下限 ) and upper limit ( λ 上限 ), determine whether these maxima are detected targets, if x t If the value is below the lower limit, then the corresponding peak value is not the target being detected; if x t If it exceeds the upper limit, the corresponding peak value is determined as the target; if x t If the value falls between the lower and upper limits, the corresponding peak value is identified as a suspected target, and the membership degree of the suspected target is output to the user; the membership function used by the target membership degree output module is the S-function.
Citation Information
Patent Citations
Method and device of processing traffic road information
CN106530684A
Design method of miniaturized focal plane array test data acquisition and display system
CN112926277A