Memory device, method of operating the same, and memory system

Abstract

A memory device includes a cell group and a control circuit. The cell group includes a plurality of non-volatile memory cells, each non-volatile memory cell capable of storing multi-bit data corresponding to an erased state and a plurality of program states. The control circuit performs at least two partial program operations for programming the multi-bit data into at least two non-volatile memory cells. The at least two partial program operations include an ISPP operation and a single pulse program operation, the ISPP operation increasing a threshold voltage of the at least two non-volatile memory cells from the erased state to a first program state among the plurality of program states, and the single pulse program operation increasing a threshold voltage of at least one non-volatile memory cell among the at least two non-volatile memory cells from the first program state to another program state among the plurality of program states that is higher than the first program state.

Description

Technical Field

[0001] One or more embodiments of this disclosure described herein relate to memory devices, and more specifically, to apparatus and methods for programming data in a non-volatile memory device. Background Technology

[0002] A data processing system includes a memory system or data storage device. A data processing system can be developed to store larger volumes of data in the data storage device, to store data faster in the data storage device, and to retrieve data stored in the data storage device faster. The memory system or data storage device may include non-volatile memory cells and / or volatile memory cells for storing data. Summary of the Invention

[0003] Embodiments of this disclosure may provide apparatus and methods capable of improving the data input / output speed of a memory device.

[0004] Furthermore, embodiments of this disclosure can apply a single programming pulse to program data into the memory device to increase the threshold voltage from one programming state to another, and use a current sensing circuit (CSC) to examine the threshold voltage distribution of the non-volatile memory cells included in the memory device. Therefore, the number of verification operations to verify the programming state and the time required can be reduced.

[0005] Specifically, in a memory device according to an embodiment of the present disclosure, a programming operation may include multiple unit operations. First, the memory device may perform an incremental step-pulse programming (ISPP) operation to increase the threshold voltage of a non-volatile memory cell capable of storing multiple bits of data from an erase state to a first programming state having the lowest threshold voltage among multiple programming states. Herein, the incremental step-pulse programming (ISPP) operation may include repeatedly applying programming pulses to induce a gradual increase in the threshold voltage. The memory device may determine a programming pulse corresponding to the difference in threshold voltages corresponding to multiple programming states, and then apply a single programming pulse to the non-volatile memory cell. By applying a single programming pulse, the non-volatile memory cell may have a threshold voltage that suddenly reaches another programming state, which has a higher threshold voltage level than the first programming state. Through this process, the memory device can reduce the number of verification operations during the programming operation, thereby reducing the internal current consumption (ICC) that occurs during the verification operation.

[0006] In one embodiment, a memory device may include: a cell array comprising non-volatile memory cells, each non-volatile memory cell capable of storing multi-bit data corresponding to an erase state and a plurality of programming states; and control circuitry configured to perform at least two partial programming operations for programming the multi-bit data into at least two of the at least two non-volatile memory cells, the at least two partial programming operations including an incremental step pulse programming (ISPP) operation and a single pulse programming operation, the ISPP operation increasing the threshold voltage of the at least two non-volatile memory cells from an erase state to a first programming state among the plurality of programming states, and the single pulse programming operation increasing the threshold voltage of at least one of the at least two non-volatile memory cells from the first programming state to another programming state among the plurality of programming states that is higher than the first programming state.

[0007] The control circuit can be configured to: apply a programming pulse to at least two non-volatile memory cells for an ISPP operation to gradually increase the threshold voltage of the at least two non-volatile memory cells from an erase state to a first programming state having the lowest threshold voltage level among a plurality of programming states corresponding to multiple bits of data; perform a first verification operation to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state; based on the result of the first verification operation, apply a single first programming pulse to the first non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state, the first programming pulse corresponding to the difference between the first programming state and the second programming state; and based on the result of the first verification operation, apply a single second programming pulse to the second non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

[0008] At least two non-volatile memory cells may include non-volatile memory cells to be programmed to have threshold voltages corresponding to a first programming state, a second programming state, and a third programming state. The result of the first verification operation may be determined based on whether the ratio of the non-volatile memory cells having the threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference.

[0009] The control circuit can also be configured to perform a second verification operation after the application of the first programming pulse and the second programming pulse to determine whether at least two non-volatile memory cells have threshold voltages corresponding to the second programming state and the third programming state.

[0010] The control circuit can also be configured to apply a programming pulse to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell when it is determined, based on the result of the second verification operation, that the threshold voltage of the first non-volatile memory cell fails to have a threshold voltage corresponding to the second programming state.

[0011] The control circuit can also be configured to apply a programming pulse to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell when it is determined, based on the result of the second verification operation, that the threshold voltage of the second non-volatile memory cell fails to have a threshold voltage corresponding to the third programming state.

[0012] The second verification operation may include a verification operation to determine whether at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state. The control circuit may also be configured to, as a result of the verification operation, apply programming pulses to some of the at least two non-volatile memory cells to gradually increase the threshold voltage of some of the at least two non-volatile memory cells to the first programming state.

[0013] The memory device may further include a page buffer configured to temporarily store multi-bit data from one of a plurality of non-volatile memory cells. The page buffer may include a plurality of latches. The number of latches may be equal to or greater than the number of bits of the multi-bit data. The memory device may further include verification circuitry coupled to the page buffer and configured to verify whether the multi-bit data is stored in each of the plurality of non-volatile memory cells.

[0014] The verification circuit may include: a plurality of current sensing circuits configured to perform verification operations for a first programming state, a second programming state, and a third programming state to output a pass signal or a failure signal for each of the first programming state, the second programming state, and the third programming state; and a first component configured to output programming success when the plurality of current sensing circuits output a pass signal.

[0015] In another embodiment, a method for operating a memory device may include: receiving multiple bits of data to be programmed into a plurality of non-volatile memory cells; applying programming pulses to at least two non-volatile memory cells in an erase state to gradually increase a threshold voltage of the at least two non-volatile memory cells from the erase state to a first programming state, the first programming state being the lowest programming state among a plurality of programming states corresponding to the multiple bits of data; performing a first verification operation to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state; and based on the result of the first verification operation... A single first programming pulse is applied to a first non-volatile memory cell among at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state, the first programming pulse corresponding to the difference between the first programming state and the second programming state; and based on the result of the first verification operation, a single second programming pulse is applied to a second non-volatile memory cell among at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

[0016] At least two non-volatile memory cells may include non-volatile memory cells to be programmed to have threshold voltages corresponding to a first programming state, a second programming state, and a third programming state. The result of the first verification operation may be determined based on whether the ratio of the non-volatile memory cells having the threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference value.

[0017] The method may also include performing a second verification operation for the second programming state and the third programming state after applying the first programming pulse and the second programming pulse.

[0018] The method may further include applying a programming pulse to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell when it is determined, based on the result of the second verification operation, that the first non-volatile memory cell fails to have a threshold voltage corresponding to the second programming state.

[0019] The method may further include applying a programming pulse to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell when it is determined, based on the result of the second verification operation, that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third programming state.

[0020] The method may further include: performing a verification operation for a first programming state during a second verification operation; and when it is determined, as a result of the verification operation during the second verification operation, that some of the non-volatile memory cells among the at least two non-volatile memory cells fail to have a threshold voltage corresponding to the first programming state, applying a programming pulse to some of the non-volatile memory cells among the at least two non-volatile memory cells to gradually increase the threshold voltage of some of the non-volatile memory cells among the at least two non-volatile memory cells to the first programming state.

[0021] In another embodiment, a memory system may include: a controller configured to receive data from an external device, determine the location for storing the data, and generate multi-bit data to be stored at the location; and a memory device configured to: receive the multi-bit data based on the location from the controller, apply programming pulses to at least two non-volatile memory cells in an erase state among a plurality of non-volatile memory cells to gradually increase the threshold voltage of the at least two non-volatile memory cells from the erase state to a first programming state, the first programming state being the lowest programming state among a plurality of programming states corresponding to the multi-bit data, and perform actions to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state. A first verification operation of the threshold voltage of the state, based on the result of the first verification operation, applies a single first programming pulse to a first non-volatile memory cell among at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state, the first programming pulse corresponding to the difference between the first programming state and the second programming state, and based on the result of the first verification operation, applies a single second programming pulse to a second non-volatile memory cell among at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

[0022] The memory device can also be configured to send a completion signal to the controller when a programming operation on multi-bit data is completed.

[0023] At least two non-volatile memory cells may include non-volatile memory cells to be programmed to have threshold voltages corresponding to a first programming state, a second programming state, and a third programming state. The result of the first verification operation may be determined based on whether the ratio of the non-volatile memory cells having the threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference value.

[0024] The memory device can also be configured to perform a second verification operation for the second programming state and the third programming state after the application of the first programming pulse and the second programming pulse.

[0025] The storage device may also be configured to: when it is determined, as a result of a second verification operation, that a first non-volatile memory cell fails to have a threshold voltage corresponding to a second programming state, apply a programming pulse to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell; and when it is determined, based on the result of the second verification operation, that a second non-volatile memory cell fails to have a threshold voltage corresponding to a third programming state, apply a programming pulse to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell.

[0026] In another embodiment, a method of operating a memory device may include: performing a first programming cycle on memory cells connected to word lines; and, as a result of the first programming cycle, sequentially performing a second programming cycle and a third programming cycle on the memory cells when the number of conducting cells in the memory cells according to a reference verification voltage is greater than a reference number. Each first programming cycle may include: applying a first programming pulse to the word line and verifying whether the number of conducting cells is greater than the reference number, wherein the first programming pulse increases by a default amount as the first programming cycle is performed according to an Incremental Step Pulse Programming (ISPP) scheme. The second programming cycle may include: sequentially applying a predetermined number of second programming pulses to the word line, and after sequentially applying the second programming pulses, sequentially verifying whether the memory cells have a corresponding target programming state, wherein the level of the second programming pulse differs by a predetermined amount relative to the first programming pulse of the last first programming cycle in the first programming cycle. The third programming cycle may include: sequentially applying a predetermined number of third programming pulses to the word line, and after sequentially applying the third programming pulses, sequentially verifying whether the memory cells have a corresponding target programming state, wherein the level of the third programming pulse differs by a default amount relative to the first programming pulse of the last first programming cycle in the first programming cycle. Attached Figure Description

[0027] The description herein refers to the accompanying drawings, wherein similar reference numerals refer to similar parts throughout the drawings.

[0028] Figure 1 A memory device according to an embodiment of the present disclosure is illustrated.

[0029] Figure 2 A data processing system according to an embodiment of the present disclosure is illustrated.

[0030] Figure 3A and Figure 3BAn incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0031] Figure 4 A method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0032] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated.

[0033] Figure 6 The programming and verification operations of an incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure are illustrated.

[0034] Figure 7 Programming operations according to embodiments of the present disclosure are illustrated.

[0035] Figure 8 An embodiment according to the present disclosure is illustrated in reference. Figure 7 The programming pulse used in the described programming operation.

[0036] Figure 9 An embodiment of the present disclosure is illustrated for use in reference to Figure 7 An example of a current sensing circuit (CSC) that verifies multiple programmed values ​​during the programming operation is described. Detailed Implementation

[0037] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0038] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not necessarily be combined in the same embodiment.

[0039] In this disclosure, the terms “comprising,” “including,” “containing,” and “included in” are open-ended. As used in the appended claims, these terms specify the presence of the mentioned element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0040] In this disclosure, various units, circuits, or other components may be described or claimed as being "configured to" perform one or more tasks. In this context, "configured to" is used to imply a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, a block / unit / circuit / component may be referred to as being configured to perform a task even when the specified block / unit / circuit / component is not currently in operation (e.g., not opened or not activated). Blocks / units / circuit / components used with the language "configured to" include hardware, such as circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor executing software) to operate in a manner capable of performing the task in question. "Configured to" may also include adapting a manufacturing process (e.g., a semiconductor manufacturing facility) to manufacture means (e.g., integrated circuits) suitable for implementing or performing one or more tasks.

[0041] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (such as an implementation in analog and / or digital circuits only), and (b) a combination of circuits and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) portions of processors / software (including digital signal processors), software, and memory that work together to enable a device (such as a mobile phone or server) to perform various functions; and (iii) circuits such as a microprocessor or a portion of a microprocessor that require software or firmware (even if the software or firmware is not physically present) to function. This definition of “circuit” or “logic” applies to all uses of the term in this application (including in any claim). As another example, as used in this application, the terms “circuit” or “logic” also cover implementations of processors (or processors) only, or portions of processors and their accompanying software and / or firmware. The terms “circuit” or “logic” also cover, for example, and if applicable to a particular claim element, integrated circuits for storage devices.

[0042] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for the nouns that follow them and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily imply that the first value must precede the second value. Furthermore, while these terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another element that would otherwise have the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0043] Furthermore, the term "based on" is used to describe factors influencing a determination. This term does not exclude additional factors that may influence the determination. That is, a determination may be based solely on those factors, or at least partially on those factors. Consider the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, such a phrase does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely on B.

[0044] In this document, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in object-oriented programming, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to one embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0045] The embodiments described herein provide a data processing system and a method for operating the data processing system. The data processing system includes components and resources such as a memory system and a host, and is capable of dynamically allocating multiple data paths for data communication between components based on the usage of the components and resources.

[0046] The embodiments will now be described with reference to the accompanying drawings, wherein similar reference numerals denote similar elements.

[0047] Figure 1 An example of a memory device 150 comprising a memory cell array circuit formed in a memory die, according to an embodiment of the present disclosure, is illustrated.

[0048] Reference Figure 1 The memory device 150 may include at least one memory bank 330 having a plurality of cell strings 340. Each cell string 340 may include a plurality of non-volatile memory cells MC0 to MCn-1 connected to corresponding bit lines of a plurality of bit lines BL0 to BLm-1. The cell strings 340 are disposed in respective columns of the memory bank 330, and each cell string 340 may include at least one drain select transistor (DST) and at least one source select transistor (or string select transistor) SST. The non-volatile memory cells MC0 to MCn-1 of each cell string 340 may be connected in series between the drain select transistor DST and the source select transistor SST. Each of the non-volatile memory cells MC0 to MCn-1 may be configured to store a multi-level cell (MLC) with a data item having a plurality of bits per cell. The cell string 340 may be electrically connected to the corresponding bit lines of the bit lines BL0 to BLm-1.

[0049] In one embodiment, memory group 330 may include NAND flash memory cells MC0 to MCn-1. In another embodiment, memory group 330 may be implemented as NOR flash memory, hybrid flash memory containing at least two different types of memory cells, or single-chip NAND flash memory in which the controller is embedded in a single memory chip. In another embodiment, memory group 330 may include flash memory cells including a charge trapping flash (CTF) layer comprising a conductive floating gate or an insulating layer.

[0050] Figure 2 A memory system 110, which may include a memory device 150, is illustrated according to an embodiment of the present disclosure. In this embodiment, the memory group 330 in the memory device 150 may include one or more memory blocks 152, 154, 156. According to the embodiment, the memory device 150 may have a two-dimensional (2D) or three-dimensional (3D) structure. For example, each of the memory blocks 152, 154, 156 in the memory device 150 may be implemented as a 3D structure, such as a vertical structure. Each of the memory blocks 152, 154, 156 may have a three-dimensional structure extending along a first direction to a third direction (e.g., the x-axis direction, the y-axis direction, and the z-axis direction).

[0051] Memory bank 330, comprising multiple memory blocks 152, 154, and 156, can be connected to multiple bit lines BL, multiple string select lines (or source select lines) SSL, multiple drain select lines DSL, multiple word lines WL, multiple dummy word lines DWL (not shown), and multiple common source lines CSL. In one embodiment, memory bank 330 may include multiple NAND strings NS, for example, multiple NAND strings NS may each correspond to a cell string 340. Each NAND string NS may include multiple memory cells MC and can be connected to corresponding bit lines in the bit lines BL. Additionally, the string select transistor SST of each NAND string NS can be connected to the common source line CSL, and the drain select transistor DST of each NAND string NS can be connected to the corresponding bit line BL. In each NAND string NS, the memory cells MC can be arranged between the string select transistor SST and the drain select transistor DST.

[0052] Reference Figure 1 and Figure 2The memory device 150 may include a voltage supply circuit 170, which can provide word line voltages (e.g., one or more predetermined voltages such as programming voltage, read voltage, and pass voltage) to corresponding word lines in the word lines according to an operating mode, or provide voltage to the body portion (e.g., a well region) in which each memory block comprising memory cells MC is formed. In this case, the voltage generation operation of the voltage supply circuit 170 can be performed under the control of the control circuit 180. Additionally, the voltage supply circuit 170 can generate multiple variable read voltages to distinguish multiple data items from each other.

[0053] In response to control by the control circuitry, one of the memory blocks (or sectors) of the memory cell array can be selected, and one of the word lines of the selected memory block can be selected. Word line voltages can be supplied separately to the selected word line and the unselected word line. The voltage supply circuitry 170 may include a voltage generation circuitry for generating target voltages with various levels (e.g., see reference 170). Figures 4 to 8 ).

[0054] In one embodiment, the voltage supply circuit 170 may be coupled to a first pin or pad that receives a first power supply voltage VCC applied from an external source (e.g., an external device) and a second pin or pad that receives a second power supply voltage VPP applied from an external device. The second power supply voltage VPP may have a voltage level higher than the first power supply voltage VCC (e.g., twice or more). For example, the first power supply voltage VCC may have a voltage level of 2.0V to 5.5V, while the second power supply voltage may have a voltage level of 9V to 13V.

[0055] According to one embodiment, the voltage supply circuit 170 may include a voltage generation circuit for more quickly generating target voltages of various levels used in the memory bank 330. The voltage generation circuit may use a second power supply voltage VPP to generate the target voltage, which may have a voltage level higher than that of the second power supply voltage VPP.

[0056] The memory device 150 may further include a read / write circuit 320 controlled by the control circuit 180. The read / write circuit 320 may operate as a read amplifier or a write driver depending on the operating mode. For example, in verification and read operations, the read / write circuit 320 may operate as a read amplifier for reading data items from the memory cell array. In programming operations, the read / write circuit 320 may operate as a write driver for controlling the potential of bit lines based on the data items to be stored in the memory cell array. The read / write circuit 320 may receive data items to be programmed into the cell array from a page buffer during programming operations. The read / write circuit 320 may drive bit lines based on the input data items. For this purpose, the read / write circuit 320 may include a plurality of page buffers (PB) 322, 324, 326, each page buffer corresponding to each column or each bit line, or each column pair or each bit line pair. According to an embodiment, each of the page buffers 322, 324, 326 may include a plurality of latches.

[0057] Page buffers 322, 324, and 326 can be connected to data input / output devices, such as serialization circuits or serializers, via multiple buses. When each of page buffers 322, 324, and 326 is connected to a data input / output device via a different bus, potential delays in data transmission from page buffers 322, 324, and 326 can be reduced. For example, each page buffer 322, 324, and 326 can perform data transmission without waiting time.

[0058] According to an embodiment, the memory device 150 can receive a write command, write data, and information about the location where the write data is to be stored, such as a physical address. The control circuit 180 causes the voltage supply circuit 170 to generate programming pulses, pass voltages, etc., used for programming operations performed in response to the write command, and to generate one or more voltages used for verification operations performed after the programming operation.

[0059] When programming multiple data items into the non-volatile memory cells included in memory bank 330, the error rate may be higher than when storing a single data item in a non-volatile memory cell. For example, errors in non-volatile memory cells may be caused by inter-cell interference (CCI). To reduce errors in non-volatile memory cells, the width (deviation) of the threshold voltage distribution corresponding to the data items stored between non-volatile memory cells should be reduced.

[0060] To this end, the memory device 150 can perform incremental step pulse programming (ISPP) operations to effectively narrow the threshold voltage distribution of the non-volatile memory cells. In an embodiment, the memory device 150 can use the ISPP operation for multi-step programming operations. For example, the memory device 150 can divide the programming operation into least significant bit (LSB) programming operations and most significant bit (MSB) programming operations according to a predetermined order between non-volatile memory cells or pages.

[0061] According to embodiments, an apparatus and method can be provided that reduces the time used to discharge bit lines or channels between programming pulse applications during data programming operations performed by applying multiple programming pulses to memory cells in a memory device. When the discharge time can be reduced, the speed of programming operations on the memory device can be increased. For example, to discharge bit lines or channels in the memory device, the memory device can control or adjust the voltage level of the bit line select line or drain select line (DSL) to prevent transistors from being in a floating state when controlled by the bit line select line or drain select line (DSL). Because the transistors may be in a floating state, the bit lines or channels cannot be properly discharged.

[0062] In an embodiment, the memory device can adjust and change the setup time for adjusting the bit line potential after the programming pulse is applied during a single programming operation of applying a programming pulse to a non-volatile memory cell in the memory device. As a result, apparatus and methods capable of improving the speed and / or efficiency of programming operations can be provided.

[0063] For example, during the operation of applying multiple programming pulses to a non-volatile memory cell in a memory device to program the non-volatile memory cell with multiple bits of data, the memory device can perform a unit programming operation in one of a variety of modes in which a second programming pulse is applied after a first programming pulse has been applied.

[0064] The programming operation modes can include a first programming mode, a second programming mode, and a third programming mode. In the first programming mode, the degree to which data is programmed in response to a second programming pulse (e.g., a change or shift in the threshold voltage of the non-volatile memory cell when the second programming pulse is applied) can be similar to or greater than the degree to which data is programmed in response to a first programming pulse. In the second programming mode, the degree to which data is programmed in response to a second programming pulse is less than the degree to which data is programmed in response to a first programming pulse. In the third programming mode, the degree to which data is programmed in response to a second programming pulse is nonexistent; for example, even when the second programming pulse is applied, the threshold voltage of the non-volatile memory cell does not change or shift. This mode can be implemented based on the potential of the bit line connected to the target memory cell when the programming pulse is applied. If the discharge time can be reduced, the memory device can improve the efficiency or speed of data programming operations by adjusting and changing the setup time used to change the bit line potential or to discharge the bit line potential.

[0065] According to an implementation, the memory device can change or adjust the control voltage applied via the bit line select line or drain select line (DSL) in response to the programming operating environment (e.g., temperature) and regarding the number, level, or magnitude of programming pulses applied to the non-volatile memory cells during data programming operations. Therefore, the memory device can reduce the operating margin corresponding to each programming pulse during data programming operations by applying multiple programming pulses to the non-volatile memory cells. This can reduce the time spent performing data programming operations.

[0066] Refer again Figure 2 The memory device 150 is shown as being included in the data processing system 100. According to an embodiment, the data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as memory system 110. For example, the host 102 and the memory system 110 may be connected to each other via a data bus, host cable, etc., to perform data communication.

[0067] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 may be considered as physically separate components or elements. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a path.

[0068] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Furthermore, according to embodiments, the memory device 150 and the controller 130 may be implemented on a single chip or on multiple chips. The controller 130 may perform data input / output operations in response to a request from an external device. For example, when the controller 130 performs a read operation in response to a read request from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0069] exist Figure 2 In this configuration, memory device 150 may include one or more memory blocks 152, 154, and 156. Memory blocks 152, 154, and 156 can be understood as a group of non-volatile memory cells whose data is removed together in a single erase operation. Memory blocks 152, 154, and 156 may include at least one page, for example, a group of non-volatile memory cells that store data together during a single programming operation and / or output data together during a single read operation. For example, a memory block may include multiple pages.

[0070] In an embodiment, the memory device 150 may include a plurality of memory planes or one or more memory chips. According to an embodiment, a memory plane may be considered as a logical or physical partition including at least one memory block, a drive circuit capable of controlling an array of a plurality of non-volatile memory cells, and a buffer capable of temporarily storing data input to or output from the non-volatile memory cells.

[0071] According to an implementation, each memory chip may include at least one memory plane and can be understood as a collection of components implemented on a physically separable substrate. Each memory chip may be connected to the controller 130 via a data path and may include an interface for exchanging data items and signals with the controller 130.

[0072] According to an embodiment, the memory device 150 may include at least one memory block 152, 154, 156, at least one memory plane, or at least one memory chip. The internal structure of the memory device 150 (e.g., Figure 1 (As shown) may vary depending on the performance of the memory system 110. Embodiments of this disclosure are not limited to... Figure 1 The internal structure is shown.

[0073] exist Figure 2In the memory device 150, a voltage supply circuit 170 is included, capable of providing one or more voltages to memory blocks 152, 154, and 156. The voltage supply circuit 170 may include a voltage generation circuit for generating target voltages for memory blocks 152, 154, and 156, for example, as shown in reference... Figures 4 to 8 As described.

[0074] In this implementation, the voltage supply circuit 170 can provide a read voltage Vrd, a programming voltage Vprog, a pass voltage Vpass, or an erase voltage Vers to the non-volatile memory cells included in the memory blocks. For example, during a read operation for reading data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can provide the read voltage Vrd to the selected non-volatile memory cell. During a programming operation for storing data in the non-volatile memory cells of memory blocks 152, 154, and 156, the voltage supply circuit 170 can provide the programming voltage Vprog to the selected non-volatile memory cell. During a read or programming operation performed on a selected non-volatile memory cell, the voltage supply circuit 170 can provide the pass voltage Vpass to the unselected non-volatile memory cell. During the erase operation used to erase data stored in the non-volatile memory cells of memory blocks 152, 154, and 156, voltage supply circuit 170 can provide an erase voltage Vers to the memory blocks.

[0075] Memory device 150 may store information about various voltages supplied to memory blocks 152, 154, and 156 based on which operation is performed. For example, when the non-volatile memory cells in memory blocks 152, 154, and 156 can store multiple bits of data, multiple levels of read voltage Vrd can be used to identify or read multiple data items. Memory device 150 may include a table having information indicating multiple levels of read voltage Vrd corresponding to multiple data items. For example, the table may include bias values ​​stored in a register, each bias value corresponding to a specific level of read voltage Vrd. The number of bias values ​​for read voltage Vrd used for read operations may be limited to a predetermined range. Furthermore, in embodiments, the bias values ​​may be quantized.

[0076] The host 102 may include a portable electronic device (e.g., a mobile phone, MP3 player, laptop computer, etc.) or a non-portable electronic device (e.g., a desktop computer, game player, television, projector, etc.). According to an embodiment, the host 102 may include the central processing unit (CPU) included in both portable and non-portable electronic devices.

[0077] Host 102 may include at least one operating system (OS) capable of controlling the functions and operations performed within host 102. The OS can provide interoperability between host 102, which is operationally coupled to memory system 110, and users who wish to store data in memory system 110. The OS can support functions and operations corresponding to user requests. By way of example and not limitation, OS can be classified as general-purpose operating systems and mobile operating systems based on the mobility of host 102. General-purpose operating systems can be further classified as personal operating systems and enterprise operating systems based on system requirements or user environment. Compared to personal operating systems, enterprise operating systems can be specifically designed to ensure and support high-performance computing.

[0078] The mobile operating system may include services or features supporting mobility, such as power-saving functions. Host 102 may include multiple operating systems. In response to a user request, host 102 may execute multiple operating systems interlocked with memory system 110. Host 102 may send multiple commands corresponding to the user request to memory system 110, thereby executing operations corresponding to the multiple commands within memory system 110.

[0079] The controller 130 can control the memory device 150 in response to requests or commands from the host 102. For example, the controller 130 can perform a read operation to provide data read from the memory device 150 to the host 102 and can perform a write operation (e.g., a programming operation) to store data input from the host 102 into the memory device 150. In order to perform data input / output (I / O) operations, the controller 130 can control and manage internal operations such as reading data, programming data, erasing data, etc.

[0080] According to an implementation, the controller 130 may include a host interface (I / F) 132, a processor 134, an error correction circuit (ECC) 138, a power management unit (PMU) 140, a memory interface (I / F) 142, and a memory 144. For example... Figure 2 The components in the controller 130 shown can vary depending on the structure, function, and operational performance of the memory system 110.

[0081] For example, memory system 110 can be implemented using any of a variety of storage devices electrically connected to host 102, depending on the host interface protocol. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini-SDs, micro-SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc. Depending on the implementation of memory system 110, components can be added to or omitted from controller 130.

[0082] Each of the host 102 and the memory system 110 may include a controller or interface for sending and receiving signals, data, etc., according to one or more predetermined protocols. For example, the host interface 132 in the memory system 110 may include devices capable of sending signals, data, etc. to or receiving signals, data, etc. from the host 102.

[0083] Host interface 132 can receive signals, commands (or requests), and / or data input from host 102. For example, host 102 and memory system 110 can send and receive data between them using predetermined protocols. Examples of communication standards or interfaces supported by host 102 and memory system 110 for sending and receiving data include Universal Serial Bus (USB), Multimedia Card (MMC), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), High-Speed ​​Peripheral Component Interconnect (PCIe or PCI-e), Serial Attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Mobile Industry Processor Interface (MIPI), etc. According to embodiments, host interface 132 is a layer for exchanging data with host 102 and is implemented or driven by firmware called the Host Interface Layer (HIL).

[0084] Integrated Drive Electronics (IDE) or Advanced Technology Accessory (ATA) can be used as one of the interfaces for sending and receiving data, and, for example, a cable including 40 wires connected in parallel can be used to support data transmission and reception between host 102 and memory system 110. When multiple memory systems 110 are connected to a single host 102, the multiple memory systems 110 can be classified as master and slave using the positions or DIP switches to which they are connected. The memory system 110 set as master can be used as the primary memory device. IDE (ATA) can include, for example, Fast-ATA, ATAPI, or Enhanced IDE (EIDE).

[0085] The Serial Advanced Technology Attachment (SATA) interface is a serial data communication interface compatible with various ATA standards for parallel data communication interfaces used by Integrated Drive Electronic Devices (IDE) devices. The 40 wires in an IDE interface can be reduced to 6 wires in a SATA interface. For example, the 40 parallel signals of IDE can be converted to the 6 serial signals of a SATA interface. The SATA interface has been widely used because it offers faster data transmission and reception rates and consumes fewer resources in the host 102 used for data transmission and reception. The SATA interface can connect up to 30 external devices to a single transceiver included in the host 102. Furthermore, the SATA interface supports hot-plugging, which allows external devices to be attached to or detached from the host 102 even while data communication between the host 102 and another device is in progress. Therefore, the memory system 110 can be connected or disconnected as an attachment device (such as a device supported by Universal Serial Bus (USB)) even when the host 102 is powered on. For example, in a host 102 with an eSATA port, the storage system 110 can be freely attached to or detached from the host 102 like an external hard drive.

[0086] The Small Computer System Interface (SCSI) is a serial data communication interface used to connect a computer or server to other peripheral devices. Compared to other interfaces such as IDE and SATA, SCSI offers high transfer speeds. In SCSI, the host 102 and at least one peripheral device (e.g., memory system 110) are connected in series, but data transmission and reception between the host 102 and each peripheral device can be performed through parallel data communication. In SCSI, devices such as memory system 110 can be easily connected to or disconnected from the host 102. SCSI can support connections of up to 15 other devices to a single transceiver included in the host 102.

[0087] Serial Attached SCSI (SAS) can be understood as a serial data communication version of SCSI. In SAS, the host 102 and multiple peripheral devices are connected in series, and data transmission and reception between the host 102 and each peripheral device can be performed according to a serial data communication scheme. Furthermore, SAS can support the connection between the host 102 and peripheral devices using serial cables instead of parallel cables, making it easier to manage equipment using SAS and enhancing operational reliability and communication performance. Additionally, SAS can support connections from up to eight external devices to a single transceiver included in the host 102.

[0088] High-speed non-volatile memory (NVMe) is an interface based at least on the High-Speed ​​Peripheral Component Interconnect (PCIe), which is designed to increase the performance and design flexibility of hosts 102, servers, computing devices, etc., equipped with a non-volatile memory system 110. PCIe can use slots or specific cables to connect computing devices (e.g., host 102) and peripheral devices (e.g., memory system 110). For example, PCIe can use multiple pins (e.g., 18 pins, 32 pins, 49 pins, or 82 pins) and at least one line (e.g., x1, x4, x8, or x16) to achieve high-speed data communication of hundreds of MB / s (e.g., 250 MB / s, 500 MB / s, 984.6250 MB / s, or 1969 MB / s). Depending on the implementation, PCIe schemes can achieve bandwidths of tens to hundreds of gigabits per second. NVMe can support faster operating speeds than hard drives for non-volatile memory systems 110 (such as SSDs).

[0089] According to one implementation, host 102 and memory system 110 can be connected via Universal Serial Bus (USB). Universal Serial Bus (USB) is a scalable, hot-pluggable, plug-and-play serial interface that provides a cost-effective standard connection between host 102 and peripheral devices such as keyboards, mice, joysticks, printers, scanners, storage devices, modems, cameras, etc. Multiple peripheral devices, such as memory system 110, can be connected to a single transceiver included in host 102.

[0090] Error correction circuit 138 can correct erroneous bits in data read from memory device 150 and may include an error correction code (ECC) encoder and an ECC decoder. The ECC encoder performs error correction encoding on data to be programmed into memory device 150 to generate encoded data with parity bits added. The encoded data can be stored in memory device 150. When controller 130 reads data stored in memory device 150, ECC decoder can detect and correct erroneous bits contained in the data read from memory device 150. For example, after performing error correction decoding on data read from memory device 150, error correction circuit 138 determines whether error correction decoding was successful and outputs an indication signal, such as a correction success signal or a correction failure signal, based on the result of error correction decoding. Error correction circuit 138 can use parity bits generated during the ECC encoding process for data stored in memory device 150 to correct erroneous bits in the read data. When the number of erroneous bits is greater than or equal to the number of correctable erroneous bits, error correction circuit 138 may not correct the erroneous bits but instead may output a correction failure signal indicating that the error bit correction failed.

[0091] According to an implementation, the error correction circuit 138 can perform error correction operations based on coded modulation. Examples include low-density parity-check (LDPC) codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, turbo codes, Reed-Solomon (RS) codes, convolutional codes, recursive systematic codes (RSC), trellis-coded modulation (TCM), block-coded modulation (BCM), etc. The error correction circuit 138 may include all circuits, modules, systems, and / or devices for performing error correction operations based on at least one of the above codes. In an implementation, the error correction circuit 138 may include... Figure 2 At least some of the components in the controller 130 shown.

[0092] The ECC decoder can perform either hard-decision decoding or soft-decision decoding on data sent from memory device 150. Hard-decision decoding can be understood as one of two methods broadly classified for error correction. Hard-decision decoding may include, for example, correcting erroneous bits by reading digital data "0" or "1" from non-volatile memory cells in memory device 150. Because hard-decision decoding deals with binary logic signals, the circuit / algorithm design or configuration can be simpler and the processing speed can be faster compared to soft-decision decoding.

[0093] Soft-decision decoding can quantize the threshold voltage of a non-volatile memory cell in memory device 150 using two or more quantized values ​​(e.g., multi-bit data, approximations, analog values, etc.) to correct erroneous bits based on the two or more quantized values. Controller 130 can receive two or more letters or quantized values ​​from multiple non-volatile memory cells in memory device 150 and then perform decoding based on information generated by characterizing the quantized values ​​as a combination of information such as conditional probability or likelihood.

[0094] According to the implementation, the ECC decoder can use Low-Density Parity-Generator Matrix (LDPC-GM) codes, which are part of a method designed for soft-decision decoding. Low-Density Parity-Generator (LDPC) codes use an algorithm that reads data values ​​from memory device 150 bit by bit based on reliability, rather than simply reading 1 or 0 data as in hard-decision decoding, and iteratively repeats this algorithm through message exchange to improve the reliability of the values. These values ​​are then ultimately determined to be 1 or 0 data. For example, the decoding algorithm using LDPC codes can be understood as probabilistic decoding. In hard-decision decoding, the value output from a non-volatile memory cell is decoded as 0 or 1.

[0095] Compared to hard-decision decoding, soft-decision decoding can determine the value stored in a non-volatile memory cell based on random information. Regarding bit flips that can be considered errors that may occur in memory device 150, soft-decision decoding can provide an improved probability of correcting errors and recovering data, and provides the reliability and stability of the corrected data. LDPC-GM codes can have schemes in which the internal low-density generator matrix (LDGM) code can be cascaded with high-speed LDPC codes.

[0096] According to the implementation, the ECC decoder can use, for example, low-density parity-check convolutional codes (LDPC-CC) for soft-decision decoding. LDPC-CC can correspond to schemes using linear-time coding and pipelined decoding based on variable block length and shift registers.

[0097] According to the implementation, the ECC decoder can use, for example, a log-likelihood ratio Turbo code (LLR-TC) for soft-decision decoding. The log-likelihood ratio (LLR) can be calculated as a nonlinear function of the distance between the sampled value and the ideal value. Alternatively, the Turbo code (TC) can include simple two-dimensional or three-dimensional codes (e.g., Hamming codes), and the decoding is repeated in both the row and column directions to improve the reliability of the values.

[0098] The power management unit (PMU) 140 can control the power supplied to the controller 130. The PMU 140 can monitor the power supplied to the memory system 110, such as the voltage supplied to the controller 130, and supply power to the components included in the controller 130. The PMU 140 can not only detect power on or off, but also generate a trigger signal to enable the memory system 110 to perform an emergency backup of its current state when the power supplied to the memory system 110 is unstable. According to embodiments, the PMU 140 may include means or components capable of accumulating power that can be used in emergency situations.

[0099] The memory interface 142 can be used as an interface for processing commands and data transferred between the controller 130 and the memory device 150, so as to allow the controller 130 to control the memory device 150 in response to commands or requests input from the host 102. When the memory device 150 is flash memory, the memory interface 142 can generate control signals for the memory device 150 and can process data input to or output from the memory device 150 under the control of the processor 134.

[0100] For example, when the memory device 150 includes NAND flash memory, the memory interface 142 includes a NAND flash memory controller (NFC). The memory interface 142 can provide an interface for handling commands and data between the controller 130 and the memory device 150. According to an embodiment, the memory interface 142 can be implemented or driven by firmware called a flash interface layer (FIL) for exchanging data with the memory device 150.

[0101] According to the implementation, the memory interface 142 may support an Open NAND Flash Interface (ONFi), a toggle mode, etc., for data input / output with the memory device 150. For example, ONFi may use a data path, such as a channel, path, etc., that includes at least one signal line capable of bidirectional transmission and reception in units of 8 bits or 16 bits of data. Data communication between the controller 130 and the memory device 150 may be implemented through at least one interface relating to Asynchronous Single Data Rate (SDR), Synchronous Double Data Rate (DDR), Switched Double Data Rate (DDR), etc.

[0102] The memory 144 can serve as working memory for either the memory system 110 or the controller 130, while simultaneously temporarily storing transaction data for operations performed in the memory system 110 and the controller 130. For example, the memory 144 can temporarily store read data that has been output from the memory device 150 in response to a read request from the host 102 before it is output to the host 102.

[0103] Additionally, the controller 130 can temporarily store write data in the memory 144 before programming write data input from the host 102 into the memory device 150. When the controller 130 controls operations such as data read operations, data write or programming operations, and data erase operations of the memory device 150, data transferred between the controller 130 and the memory device 150 of the memory system 110 can be temporarily stored in the memory 144.

[0104] In addition to reading or writing data, memory 144 may also store information for inputting or outputting data between host 102 and memory device 150, such as mapped data, read requests, programming requests, etc. According to embodiments, memory 144 may include one or more of a command queue, programming memory, data memory, write buffer / cache, read buffer / cache, data buffer / cache, mapping buffer / cache, etc. Controller 130 may allocate some storage space in memory 144 for components established to perform data input / output operations. For example, a write buffer established in memory 144 may be used to temporarily store target data undergoing programming operations.

[0105] In implementations, memory 144 can be implemented using volatile memory. For example, memory 144 can be implemented using static random access memory (SRAM), dynamic random access memory (DRAM), or both. Although Figure 2 The example illustrates that memory 144 is located within controller 130, but the implementation is not limited thereto. Memory 144 may be located inside or outside controller 130. For example, memory 144 may be implemented by an external volatile memory having a memory interface for transferring data and / or signals between memory 144 and controller 130.

[0106] Processor 134 can control the overall operation of memory system 110. For example, processor 134 can control programming or reading operations of memory device 150 in response to write or read requests from host 102. According to embodiments, processor 134 can execute firmware to control programming or reading operations in memory system 110. The firmware may be, for example, a flash translation layer (FTL). According to embodiments, processor 134 can be implemented using a microprocessor, a central processing unit (CPU), or another processing device.

[0107] According to one embodiment, the memory system 110 can be implemented using at least one multi-core processor. A multi-core processor is a circuit or chip in which two or more cores, considered distinct processing regions, are integrated. For example, when multiple cores in a multi-core processor independently drive or execute multiple flash translation layers (FTLs), the data input / output speed or performance of the memory system 110 can be improved. According to one embodiment, data input / output (I / O) operations in the memory system 110 can be performed independently by different cores in the multi-core processor.

[0108] The processor 134 in the controller 130 can perform operations corresponding to requests or commands input from the host 102. Furthermore, the memory system 110 can perform operations independently of commands or requests input from the host 102. In one case, operations performed by the controller 130 in response to requests or commands input from the host 102 can be considered foreground operations, while operations performed by the controller 130 independently of requests or commands input from the host 102 can be considered background operations. The controller 130 can perform foreground or background operations for reading, writing, or erasing data in the memory device 150. Additionally, parameter setting operations corresponding to setting parameter commands or setting feature commands sent as setting commands from the host 102 can be considered foreground operations. Examples of background operations that can be performed without commands sent from the host 102 include the controller 130 performing garbage collection (GC), wear leveling (WL), bad block management for identifying and handling bad blocks, etc.

[0109] According to the implementation, both foreground and background operations can be performed with substantially similar operations. For example, garbage collection can be considered a foreground operation when the memory system 110 performs garbage collection (e.g., manual GC) in response to a request or command input from the host 102. Garbage collection can be considered a background operation when the memory system 110 performs garbage collection (e.g., automatic GC) independently of the host 102.

[0110] When the memory device 150 includes multiple wafers or chips, each containing multiple non-volatile memory cells, the controller 130 can perform parallel processing of multiple requests or commands input from the host 102 to improve the performance of the memory system 110. For example, the sent requests or commands can be divided into multiple groups including at least some of the multiple planes, wafers, or chips included in the memory device 150, and the requests or commands of the multiple groups can be processed individually or in parallel in each plane, wafer, or chip.

[0111] The memory interface 142 in controller 130 can be connected to multiple wafers or chips in memory device 150 via at least one channel and at least one path. When controller 130 distributes and stores data across multiple wafers via each channel or path in response to a request or command associated with multiple pages including non-volatile memory cells, multiple operations corresponding to the request or command can be performed simultaneously or in parallel across multiple wafers or planes. This processing method or scheme can be considered an interleaving method. Because the data input / output speed of memory system 110 is increased by operating in an interleaving method, the data I / O performance of memory system 110 can be improved.

[0112] By way of example, and not limitation, controller 130 can identify the states of multiple channels or pathways associated with multiple wafers included in memory device 150. Controller 130 can determine the state of each channel or pathway as one of a busy state, a ready state, an active state, an idle state, a normal state, and an abnormal state. The determination by controller 130 regarding which channel or pathway is used to deliver instructions and / or data can be associated with a physical block address. Controller 130 can reference descriptors delivered from memory device 150. A descriptor may include a block or page containing parameters describing certain things about memory device 150. A descriptor may have a predetermined format or structure. For example, a descriptor may include a device descriptor, a configuration descriptor, a cell descriptor, etc. Controller 130 can refer to or use the descriptors to determine which channel or pathway is used to exchange instructions or data.

[0113] As described above, the memory device 150 in the memory system 110 may include one or more memory blocks 152, 154, and 156. Each of the memory blocks 152, 154, and 156 includes a plurality of non-volatile memory cells. According to an embodiment, the memory blocks 152, 154, and 156 may be a group of non-volatile memory cells that are erased together. The memory blocks 152, 154, and 156 may include a plurality of pages, which are a group of non-volatile memory cells that are read or programmed together.

[0114] In this embodiment, each of the memory blocks 152, 154, and 156 may have a highly integrated three-dimensional stacked structure. Furthermore, the memory device 150 may include multiple wafers, each wafer including multiple planes, and each plane including memory blocks 152, 154, and 156. The configuration of the memory device 150 may be varied depending on the performance of the memory system 110.

[0115] exist Figure 2 In this embodiment, memory device 150 includes memory blocks 152, 154, and 156. Based on the number of bits that can be stored in a single memory cell, memory blocks 152, 154, and 156 can be any type of memory block, such as a single-level cell (SLC) memory block or a multi-level cell (MLC) memory block. An SLC memory block comprises multiple pages implemented with memory cells that store one bit of data per memory cell. SLC memory blocks can have higher data I / O performance and greater endurance than MLC memory blocks. An MLC memory block comprises multiple pages implemented with memory cells that store multiple bits of data (e.g., two or more bits of data) per memory cell. Compared to SLC memory blocks, MLC memory blocks can have a larger storage capacity for the same space. From a storage capacity perspective, MLC memory blocks can be highly integrated.

[0116] In one embodiment, the memory device 150 may be implemented using MLC memory blocks such as two-level cell (DLC) memory blocks, three-level cell (TLC) memory blocks, four-level cell (QLC) memory blocks, and combinations thereof. A DLC memory block may include multiple pages implemented by memory cells capable of storing 2 bits of data per memory cell. A TLC memory block may include multiple pages implemented by memory cells capable of storing 3 bits of data per memory cell. A QLC memory block may include multiple pages implemented by memory cells capable of storing 4 bits of data per memory cell. In another embodiment, the memory device 150 may be implemented using blocks comprising multiple pages implemented by memory cells capable of storing five or more bits of data per memory cell.

[0117] According to one implementation, the controller 130 can use an MLC memory block included in the memory device 150 as an SLC memory block that stores one bit of data in a memory cell. The data input / output speed of a Multilevel Cell (MLC) memory block can be slower than that of an SLC memory block. For example, when an MLC memory block is used as an SLC memory block, the margin for read or programmable operations can be reduced. For example, when an MLC memory block is used as an SLC memory block, the controller 130 can perform data input / output operations at a higher speed. Therefore, the controller 130 can use an MLC memory block as an SLC buffer to temporarily store data, because a buffer may require a high data input / output speed to improve the performance of the memory system 110.

[0118] According to one embodiment, the controller 130 can program data multiple times in the MLC without performing an erase operation on a specific MLC memory block included in the memory device 150. Typically, non-volatile memory cells do not support data overwriting. However, the controller 130 can utilize the characteristic of the MLC to store multiple bits of data to program one bit of data multiple times in the MLC. For an MLC overwrite operation, when programming one bit of data in the MLC, the controller 130 can store the number of programming times as separate operation information. According to one embodiment, an operation to evenly level the threshold voltage of the MLC can be performed before programming another one bit of data in the same MLC where one bit of data has already been stored.

[0119] In one embodiment, the memory device 150 is implemented as a non-volatile memory such as flash memory (e.g., NAND flash memory, NOR flash memory, etc.). In another embodiment, the memory device 150 may be implemented by at least one of phase-change random access memory (PCRAM), ferroelectric random access memory (FRAM), spin-torque random access memory (STT-RAM), and spin-torque magnetic random access memory (STT-MRAM).

[0120] Figure 3A and Figure 3B An incremental step pulse programming (ISPP) operation according to an embodiment of the present disclosure is illustrated.

[0121] Reference Figure 3A Data can be programmed into non-volatile memory cells in an erased state. When a programming pulse is provided to a word line connected to a non-volatile memory cell, the threshold voltage distribution of the non-volatile memory cell can shift to the right (e.g., in the direction of increasing threshold voltage) from the erased state. If programming pulses are continuously provided to the non-volatile memory cells, the threshold voltage distribution of the non-volatile memory cells can be continuously shifted to the right. Programming pulses can be provided until most of the multiple non-volatile memory cells in the threshold voltage distribution have a value higher than the target voltage V. TARG Threshold voltage.

[0122] exist Figure 3B In the process of programming, when the programming operation begins (operation 212), the memory device 150 may apply programming pulses to a plurality of non-volatile memory cells to be programmed (operation 214). After applying the programming pulses, the memory device 150 may verify whether most of the plurality of non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH (Operation 216). When the verification result FAIL (failure) determines that most of the multiple non-volatile memory cells do not have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, memory device 150 applies another programming pulse to the corresponding non-volatile memory cell (operation 214). When it is determined, based on another verification result PASS, that most of the multiple non-volatile memory cells have a voltage higher than the target voltage V. TARG Threshold voltage V TH At this time, the memory device 150 can end the programming operation (operation 218).

[0123] To narrow the threshold voltage distribution of multiple non-volatile memory cells, it is advantageous to slightly shift the threshold voltage distribution of the multiple non-volatile memory cells to the right by, for example, a first amount, when a single programming pulse is applied, rather than shifting them significantly to the right by, for example, a second amount larger than the first amount. On the other hand, when the threshold voltage distribution of the multiple non-volatile memory cells is slightly shifted to the right, the number of programming pulses applied can be increased.

[0124] According to the implementation, the number of programming pulses applied can be three times or more the number of data bits that can be stored in the non-volatile memory cell. For example, when 2 bits of data can be stored in the non-volatile memory cell, the non-volatile memory cell can have four programming states corresponding to the 2 bits of data, such as "00", "01", "10", and "11". To form a denser threshold voltage distribution, such as a narrower distribution, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts to the right in response to a single programming pulse can be less than the difference between two adjacent programming states. For example, when two or more programming pulses are applied, it can be designed to shift according to the difference between two adjacent programming states. In this case, the number of programming pulses applied can be eight or more, which is more than four times the number of data bits.

[0125] According to the implementation method, the degree to which the threshold voltage distribution of multiple non-volatile memory cells shifts when a single programming pulse is applied can be understood as the target level. For Figure 6 An example of the implementation method is described in more detail below for the target level.

[0126] Figure 4 A method for storing multiple bits of data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 4 The method may include programming operations performed in a memory device 150 comprising non-volatile memory cells each capable of storing 3 bits of data.

[0127] Data stored in non-volatile memory cells can be based on the threshold voltage V of the corresponding memory cell. TH The threshold voltage V of the memory cell is used to differentiate them. TH The threshold voltage V can vary depending on the number of electrons or charges injected into the floating gate of the corresponding memory cell. A single-level cell (SLC) can be divided into two ranges. TH It stores 1-bit data, either "0" or "1". On the other hand, the three-level cell (TLC) in the memory device 150 can have eight threshold voltage ranges.

[0128] Reference Figure 4To reduce the number of programming pulses applied during Incremental Step Pulse Programming (ISPP) operations, the application of programming pulses to the Level 3 Cell (TLC) in response to the data bits stored in the TLC can be controlled differently. The data stored in the TLC can be divided into LSB data, CSB data, and MSB data. When programming LSB data, the number of programming pulses applied can be minimized, while the number of programming pulses applied when programming CSB data can be greater than that applied when programming LSB data. When programming MSB data, the number of programming pulses applied can be maximized.

[0129] In a three-level cell (TLC) memory device, each physical page can be divided into three logical pages: an LSB page, a CSB page, and an MSB page. The programming pulse applied to each page can be different. For example, different positive threshold voltages (V) can be triggered during the programming of LSB data, CSB data, and MSB data. TH The distribution shifts. In the implementation, the threshold voltage V of multiple non-volatile memory cells. TH The maximum number of cells can be moved during LSB page programming, and the threshold voltage V of multiple non-volatile memory cells is [not specified]. TH Minimal movement is achieved during MSB page programming. According to the implementation, the shortest latency and lowest power consumption are achieved when the number of programming pulses applied during LSB page programming is minimized. Conversely, increasing the number of programming pulses applied during MSB page programming increases latency and power consumption.

[0130] Figure 5 Another method for storing multi-bit data in a non-volatile memory cell according to an embodiment of the present disclosure is illustrated. Figure 5 As an example, the programming operation performed by a memory device 150, which includes a non-volatile memory cell capable of storing 3 bits of data, will be described.

[0131] Reference Figure 5 The memory device 150 may not sequentially divide the operation of storing 3 bits of data in the non-volatile memory cell into LSB programming operation, CSB programming operation, and MSB programming operation. In order to store 3 bits of data in the non-volatile memory cell without separation, the code values ​​of LSB, CSB, and MSB corresponding to the eight programming states can be... Figure 4The differences are shown below. The 3-bit data corresponding to the 8 programming states can be identified as Gray code, and the LSB, CSB, and MSB code values ​​can be set differently. Here, Gray code is a code created to change the value of only one bit between adjacent data when the data changes. For example, the data in the erase state can be understood as "111", while the data in the lowest programming state is "011". The data in the second lowest programming state adjacent to the lowest programming state data "011" can be "001".

[0132] Reference Figure 4 and Figure 5 The code values ​​of LSB, CSB, and MSB can vary depending on how multiple bits of data are stored in a non-volatile memory cell. For example, corresponding to... Figure 4 The MSB code value for the eight programming states shown can be "10101010", while Figure 5 The MSB code value for the eight programming states shown can be "11100001". According to the implementation method, Figure 4 and Figure 5 The code values ​​of the LSB and MSB described herein may vary depending on the implementation method.

[0133] Figure 6 The programming voltage application operation and verification operation of the ISPP operation according to an embodiment of the present disclosure are illustrated.

[0134] Reference Figure 6 After performing the programming voltage application operation Pgm during ISPP operation, the memory device 150 performs a verification operation Ver corresponding to the programming voltage application operation Pgm. Each programming voltage application operation Pgm can adjust the threshold voltage V of the non-volatile memory cell. TH Increase. For example, each programming voltage applied to operation Pgm will increase the threshold voltage V of the non-volatile memory cell. TH Increase the first potential difference ΔV.

[0135] After performing the programming voltage application operation Pgm, the threshold voltage V of the non-volatile memory cell can be applied during the verification operation. TH Compare with the verification voltage. When the threshold voltage V of the non-volatile memory cell... TH If the voltage drops below the verification voltage, another programming voltage application operation Pgm can be performed to add more electrons to the floating gate of the non-volatile memory cell. Thereafter, a verification operation Ver is performed in response to the corresponding programming voltage application operation Pgm. Repeated programming voltage application operations Pgm can be performed until the threshold voltage V of the non-volatile memory cell is reached. TH Change to the verification voltage or higher.

[0136] According to the implementation method, the number of repetitions of the programming voltage application operation Pgm and the verification operation Ver can vary depending on standby time or delay time, power consumption, accuracy, etc. When the threshold voltage V of the non-volatile memory cell is finely increased through the programming voltage application operation Pgm... TH At this rate, the accuracy of the programming voltage application operation can be increased. However, with more programming voltage applications that can be performed, the latency can be longer and the power consumption can be greater. On the other hand, when the threshold voltage V of the non-volatile memory cell... TH While significantly increasing the power consumption of the programming voltage application operation Pgm may increase, the operating time of Pgm can be shortened. The operating time Δt of both the programming voltage application operation Pgm and the verification operation Ver can be determined based on the target power of each programming voltage application operation Pgm (e.g., threshold voltage V). TH Changes (due to changes in the environment).

[0137] Reference Figure 4 and Figure 5 In a memory device comprising a three-level non-volatile memory cell (TLC), the programming voltage application operation Pgm and the verification operation Ver can be performed differently depending on the purpose and process of programming data in the least significant bit (LSB), center significant bit (CSB), and most significant bit (MSB) of the memory cell. Figure 4 As an example, a memory device including a three-level non-volatile memory cell (TLC) has been described, but the above programming operations can also be applied to memory devices including a four-level non-volatile memory cell (QLC) for storing 4 bits of data, or a non-volatile memory cell capable of storing 5 or more bits of data.

[0138] According to the implementation, for each programming cycle during ISPP operation, the voltage level of the programming pulse applied to the non-volatile memory cell in the programming voltage application operation Pgm can be gradually increased according to a preset voltage ΔV. However, the voltage level of the verification pulse applied to the non-volatile memory cell in the verification operation Ver corresponding to the programming voltage application operation Pgm can be substantially the same, for example, unchanged. In the verification operation Ver for each programming cycle, substantially the same verification pulse is applied to the non-volatile memory cell, but the time Δt for applying the verification pulse can be changed. When the verification operation is performed by reflecting noise generated according to the operating characteristics of the memory device 150, the memory device 150 can change or adjust the voltage level of the verification pulse.

[0139] Figure 7 Programming operations according to embodiments of this disclosure are illustrated. Figure 7The example described herein illustrates an implementation of storing 2 bits of data in a non-volatile memory cell. The threshold voltage level of the non-volatile memory cell capable of storing 2 bits of data can belong to a distribution corresponding to the erase state (P0) and the first programming states P1 to the third programming states P3.

[0140] Reference Figure 7 Programming operations for storing multiple bits of data in a non-volatile memory cell can generally consist of two parts. First, the memory device 150 can perform an ISPP operation to move the threshold voltage of the non-volatile memory cell from an erase state P0 to a first programming state P1 (operation 530). Then, when the ISPP operation determines that the non-volatile memory cell has a threshold voltage corresponding to the first programming state P1, the memory device 150 can perform a single programming pulse operation to shift or increase the threshold voltage of the non-volatile memory cell from the first programming state P1 to a second programming state P2 or a third programming state P3 (operations 540, 550). In the single programming pulse operation, the single programming pulse applied to the non-volatile memory cell can be determined based on the difference between the first programming state P1 and the second programming state P2 or the third programming state P3 (see [link to relevant documentation]). Figure 8 ).

[0141] The two-bit data programmed in the non-volatile memory cell can be divided into four data types: "11", "10", "00", and "01". According to an embodiment, the two-bit data "11" can correspond to an erase state P0. The two-bit data "10" can correspond to a first programming state P1, the two-bit data "00" can correspond to a second programming state P2, and the two-bit data "01" can correspond to a third programming state P3. Among the plurality of non-volatile memory cells, the non-volatile memory cell storing the two-bit data "11" can be maintained in the erase state P0. Even if at least one programming pulse is applied to the non-volatile memory cell, the memory device 150 can adjust the potential of the bit line connected to the non-volatile memory cell to suppress an increase in the threshold voltage of the non-volatile memory cell (i.e., not program the non-volatile memory cell). Furthermore, among the multiple non-volatile memory cells, the memory device 150 can apply a programming pulse to the non-volatile memory cell that is to store 2 bits of data "10", "00" or "01" to change them from the erase state P0 to one of the first programming states P1 to the third programming state P3.

[0142] The memory device 150 can perform an ISPP operation (operation 530) on a non-volatile memory cell programmed to have a threshold voltage corresponding to one of the first programming states P1 to the third programming states P3. (See also...) Figure 6In ISPP operation 530, a programming pulse with a gradually increasing level can be applied to a non-volatile memory cell. The threshold voltage of the non-volatile memory cell can gradually shift from the erase state P0 to the first programming state P1 in response to the applied programming pulse.

[0143] In operations 540 and 550, a programming pulse can be applied to at least some of the non-volatile memory cells in the first programming state P1, such that at least some of the non-volatile memory cells have a threshold voltage level corresponding to the second programming state P2 or the third programming state P3. In these operations, the memory device 150 can apply a single programming pulse to the non-volatile memory cell to increase the threshold voltage of the non-volatile memory cell without performing an ISPP operation that applies multiple programming pulses to gradually increase the threshold voltage. The first single programming pulse applied to the non-volatile memory cell to be programmed to the second programming state P2 can be determined based on the difference between the first programming state P1 and the second programming state P2 (operation 540). Furthermore, a second single programming pulse corresponding to the difference between the first programming state P1 and the third programming state P3 can be applied to the non-volatile memory cell to be programmed to the third programming state P3 (operation 550).

[0144] In the operations 540 and 550 described above, because the memory device 150 applies a single programming pulse to the non-volatile memory cell, the memory device 150 may not perform a verification operation to check the threshold voltage during the process of changing from the first programming state P1 to the second programming state P2 or the third programming state P3.

[0145] As the threshold voltage is gradually increased through the ISPP operation, the memory device 150 can perform verification operations between operations that apply programming pulses to the non-volatile memory cell. However, during the ISPP operation, the threshold voltage gradually increases, such that most verification operations for the non-volatile memory cell may output failure signals before the non-volatile memory cell has a threshold voltage corresponding to the second programming state P2 or the third programming state P3. That is, comparing the threshold voltage of the non-volatile memory cell with the third verification target level PV3 corresponding to the third programming state P3 results in failure until the non-volatile memory cell is programmed to the third programming state P3. During this process, there is no difference between the verification results output from the current sensing circuit (CSC) when the threshold voltage of the non-volatile memory cell is in the erase state P0 and when the threshold voltage of the non-volatile memory cell is in the second programming state P2. Furthermore, there is no significant difference in the current consumption in the current sensing circuit CSC. When the current sensing circuit CSC outputs failure signals several times in multiple programming cycles, the internal current consumption increases. If the internal current consumption (ICC) increases sharply, it may have an adverse effect on the peak current consumption in the memory device 150.

[0146] According to the implementation method, the first verification target level PV1 corresponding to the first programming state P1, the second verification target level PV2 corresponding to the second programming state P2, and the third verification target level PV3 corresponding to the third programming state P3 can be slightly lower than the average value of the distribution corresponding to the first programming state P1 to the third programming state P3. (Refer to...) Figure 6 The first verification target level PV1 to the third verification target level PV3 can be determined based on the level or application time of the verification voltage. The verification voltages can have essentially the same level, but different application times (i.e., different times when the verification voltage is applied to the non-volatile memory cell).

[0147] According to the implementation, when the threshold voltage of a non-volatile memory cell changes from a first programming state P1 to a second programming state P2 or a third programming state P3, the deviation of the threshold voltage distribution of the non-volatile memory cell can increase (e.g., the width of the threshold voltage distribution becomes wider). Therefore, when the non-volatile memory cell undergoes a verification operation targeting a first verification target level PV1 to a third verification target level PV3, the memory device 150 can additionally perform ISPP operations (operations 532, 542, 552) on the non-volatile memory cell. Through the additional ISPP operations 532, 542, 552, the threshold voltage distribution of the plurality of non-volatile memory cells can be slightly shifted to the first programming state P1 to the third programming state P3, and the deviation of the threshold voltage distribution can be reduced, that is, the width of the distribution becomes narrower.

[0148] Figure 8 An embodiment according to the present disclosure is illustrated in reference. Figure 7 The programming pulse used in the described programming operation.

[0149] Reference Figure 8 The process of programming multiple bits of data in multiple non-volatile memory cells may include a first ISPP operation segment 530, an operation segment 560 for applying a single programming pulse, and a second ISPP operation segment 570.

[0150] Reference Figure 7 and Figure 8 During the first ISPP operation segment 530, the threshold voltage of a non-volatile memory cell can shift from the erase state P0 to the first programming state P1. A verification operation targeting a first verification target level PV1 can be performed on the non-volatile memory cells scheduled to be programmed with first programming states P1 to third programming states P3. Based on the verification result, the memory device 150 can determine whether the right side of the threshold voltage distribution for the non-volatile memory cell reaches the first verification target level PV1. When the threshold voltage distribution reaches the first verification target level PV1 (PV1 PASS), the memory device 150 can terminate the first ISPP operation segment 530. The right side of the threshold voltage distribution may include the upper tail (right tail) of a normal distribution or probability distribution of the threshold voltages for the non-volatile memory cells. The upper tail represents the appendages on the right side of the distribution (e.g., 3%, 5%, or 10% of the right side).

[0151] In operation segment 560, following the first ISPP operation segment 530, the memory device 150 may not perform multiple cycles of programming pulse application and corresponding verification. The memory device 150 may apply a single programming pulse to each non-volatile memory cell to shift a threshold voltage from a first programming state P1 or to a second programming state P2 or a third programming state P3. A first programming pulse corresponding to the difference between the first programming state P1 and the second programming state P2 may be applied to the first non-volatile memory cell to be programmed with the second programming state P2 (operation 540). For example, the difference between the first programming state P1 and the second programming state P2 may indicate the difference between the average level of the threshold voltage distribution corresponding to the first programming state P1 and the average level of the threshold voltage distribution corresponding to the second programming state P2. In this case, the first programming pulse may be higher than a preset level (A) than the last programming pulse applied in the first ISPP operation segment 530. The preset level (A) may be determined based on the difference between the first programming state P1 and the second programming state P2. Furthermore, the memory device 150 can apply a second programming pulse to a second non-volatile memory cell to be programmed with a third programming state P3. The second programming pulse can be higher than the last programming pulse applied in the first ISPP operation segment 530 by another preset level (A+B) (operation 550). The second programming pulse can be determined based on the difference between the first programming state P1 and the second programming state P2, and the difference between the second programming state P2 and the third programming state P3 (A+B). After applying the first and second programming pulses to increase the threshold voltage to the second programming state P2 and the third programming state P3 (operations 540, 550), the memory device 150 can continuously perform verification operations for the first verification target level PV1 to the third verification target level PV3 corresponding to the first programming state P1 to the third programming state P3.

[0152] When the memory device 150 determines through a verification operation that the right side of the threshold voltage distribution of the non-volatile memory cells has reached the first verification target level PV1 to the third verification target level PV3 (PASS), the memory device 150 may perform a second ISPP operation (segment 570). During the second ISPP operation segment 570, the programming pulse applied to the non-volatile memory cells has a higher level than the programming pulse applied to the non-volatile memory cells during the first ISPP operation segment 530 or the programming pulse applied to the non-volatile memory cells during operation segment 560. In the first ISPP operation segment 530, before each verification operation (see “PV1” in ISPP segment 530), programming pulses with the same level may be applied to multiple non-volatile memory cells.

[0153] However, in the second ISPP operation segment 570, prior to the verification operations (see PV1, PV2, PV3 in ISPP segment 570), programming pulses with different levels can be applied to the multiple non-volatile memory cells based on a first verification target level PV1 to a third verification target level PV3. For example, in the first ISPP operation segment 530, prior to each verification operation targeting the first verification target level PV1, a single programming pulse can be applied to the word lines connected to the multiple non-volatile memory cells. On the other hand, in the second ISPP operation segment 570, prior to a series of verification operations targeting the first verification target level PV1 to the third verification target level PV3, multiple programming pulses 532, 542, 552 with different levels can be sequentially applied to the word lines connected to the multiple non-volatile memory cells. The memory device 150 can adjust or change the potential of the bit lines connected to the non-volatile memory cells in response to the multiple programming pulses 532, 542, 552 to selectively program the multiple non-volatile memory cells connected to the word lines. After applying multiple programming pulses 532, 542, and 552 with different levels sequentially to word lines connected to multiple non-volatile memory cells, the memory device 150 can perform a verification operation to determine whether the multiple non-volatile memory cells have the first programming state P1 to the third programming state P3 based on the first verification target level PV1 to the third verification target level PV3 corresponding to the first programming state P1 to the third programming state P3.

[0154] Figure 9 An embodiment of the present disclosure is illustrated for use in reference to Figure 7 An example of a current sensing circuit (CSC) that verifies multiple programmed values ​​during a programming operation is described herein. In this document, the programmed values ​​can indicate the target threshold voltage level after a programming operation in which at least one programming pulse has been applied.

[0155] Reference Figure 9 The page buffer 322 in memory device 150 can be connected to the verification circuit 420. The page buffer 322 can be connected to a non-volatile memory cell via bit line BL. The page buffer 322 may include multiple latches 502 and 504. When multiple bits of data are stored in the non-volatile memory cell, the page buffer 322 may include multiple latches 502 and 504, each latch capable of storing each bit of the multiple bits of data transmitted via bit line BL. For example, the page buffer 322 may include an LSB (least significant bit) latch 502 for storing LSB data and an MSB (most significant bit) latch 504 for storing MSB data.

[0156] The verification circuit 420 connected to the page buffer 322 may include multiple current sensing circuits 422, 424, and 426, each current sensing circuit being configured to perform a verification operation based on each of a first verification target level PV1 to a third verification target level PV3. (See reference...) Figure 8 The memory device 150 can continuously perform verification operations with respect to the first verification target level PV1 to the third verification target level PV3. When the verification circuit 420 includes first current sensing circuits to third current sensing circuits 422, 424, and 426 corresponding to the first verification target level PV1 to the third verification target level PV3 to perform verification operations, the verification circuit 420 may include an AND gate 428 configured to sum the results output from the first current sensing circuits to the third current sensing circuits 422, 424, and 426 to output a verification result. When all three current sensing circuits (422, 424, and 426) output pass signals, the AND gate 428 can output the verification result CSC P / F as a pass signal. On the other hand, if any one of the first current sensing circuits to the third current sensing circuits 422, 424, and 426 outputs a failure signal, the AND gate 428 can output the verification result CSC P / F as a failure signal.

[0157] According to an implementation, the verification circuit 420 may include a single current sensing circuit, and performs multiple verification operations sequentially based on multiple verification target levels PV1 to PV3 through the single current sensing circuit. After the results of the verification operations sequentially performed in the single current sensing circuit are temporarily stored in a latch or register, the results of the multiple verification operations can be output. Based on the results of the multiple verification operations, programming operations can be additionally performed only if the result of the multiple verification operations regarding the verification target level is a failure signal.

[0158] As described above, the memory system or memory device according to the embodiments of the present disclosure can reduce the amount of current consumed during programming operations and stabilize or mitigate peak current consumption.

[0159] The methods, processes, and / or operations described herein can be performed by code or instructions to be executed by a computer, processor, controller, or other signal processing device. The computer, processor, controller, or other signal processing device can be those described herein or those other than those described herein. Because the algorithms that form the basis of the methods (or the operation of the computer, processor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the methods can convert a computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods herein.

[0160] In addition, another embodiment may include a computer-readable medium for storing the aforementioned code or instructions, such as a non-transitory computer-readable medium. The computer-readable medium may be volatile or non-volatile memory or other storage device, which may be removably or permanently coupled to a computer, processor, controller, or other signal processing device that will execute the code or instructions for performing the operations of the method or apparatus embodiments described herein.

[0161] The controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features disclosed herein can, for example, be implemented in non-transitory logic that may include hardware, software, or both. When implemented at least partially in hardware, the controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features can be, for example, any of the following integrated circuits, including but not limited to: application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), combinations of logic gates, systems-on-a-chip (SoCs), microprocessors, or other types of processing or control circuitry.

[0162] When implemented at least partially in software, controllers, processors, control circuits, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, generators, and other signal generation and signal processing features may include, for example, memory or other storage devices for storing code or instructions, for example, to be executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device may be those described herein or those other than those described herein. Because the algorithms underlying the formation of the method (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method implementation can transform the computer, processor, controller, or other signal processing device into a dedicated processor for executing the methods described herein.

[0163] While the teachings have been illustrated and described with reference to specific embodiments, it will be apparent to those skilled in the art, based on this disclosure, that various changes and modifications can be made without departing from the spirit and scope of the disclosure as defined in the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0164] Cross-references to related applications

[0165] This patent application claims the benefit of Korean Patent Application No. 10-2021-0131551, filed on October 5, 2021, the entire disclosure of which is incorporated herein by reference.

Claims

1. A memory device, the memory device comprising: The cell array includes non-volatile memory cells, each of which can store multi-bit data corresponding to an erase state and multiple programming states; as well as A control circuit that performs programming operations to program the multi-bit data into at least two portions of at least two non-volatile memory cells. The at least two programming operations include: Incremental Step Pulse Programming (ISPP) operation, wherein the ISPP operation increases the threshold voltage of the at least two non-volatile memory cells from the erase state to a first programming state among the plurality of programming states, and A single-pulse programming operation increases the threshold voltage of at least one of the at least two non-volatile memory cells from the first programming state to another programming state among the plurality of programming states that is higher than the first programming state.

2. The memory device according to claim 1, wherein, The control circuit also includes: For the ISPP operation, a programming pulse is applied to the at least two non-volatile memory cells to gradually increase the threshold voltage of the at least two non-volatile memory cells from the erase state to the first programming state, which has the lowest threshold voltage level among the plurality of programming states corresponding to the multi-bit data. Perform a first verification operation to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state. Based on the result of the first verification operation, a single first programming pulse is applied to the first non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state. The first programming pulse corresponds to the difference between the first programming state and the second programming state. Based on the result of the first verification operation, a single second programming pulse is applied to the second non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

3. The memory device according to claim 2, in, The at least two non-volatile memory cells include non-volatile memory cells to be programmed to have threshold voltages corresponding to the first programming state, the second programming state, and the third programming state, and The result of the first verification operation is determined based on whether the ratio of the non-volatile memory cells having a threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference value.

4. The memory device according to claim 2, wherein, The control circuit also performs a second verification operation after applying the first programming pulse and the second programming pulse to determine whether the at least two non-volatile memory cells have threshold voltages corresponding to the second programming state and the third programming state.

5. The memory device according to claim 4, wherein, When the control circuit determines, as a result of the second verification operation, that the first non-volatile memory cell fails to have a threshold voltage corresponding to the second programming state, it applies a programming pulse to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell.

6. The memory device according to claim 4, wherein, When the control circuit determines, as a result of the second verification operation, that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third programming state, it applies a programming pulse to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell.

7. The memory device according to claim 4, in, The second verification operation includes a verification operation for determining whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state, and The control circuit further applies programming pulses to some of the non-volatile memory cells when it determines, as a result of the verification operation, that some of the non-volatile memory cells fail to have a threshold voltage corresponding to the first programming state, thereby gradually increasing the threshold voltage of the non-volatile memory cells to the first programming state.

8. The memory device according to claim 1, further comprising: A page buffer temporarily stores the multi-bit data from one of the non-volatile memory cells, and includes a plurality of latches, the number of which is equal to or greater than the number of bits of the multi-bit data. as well as A verification circuit is connected to the page buffer and verifies whether the multi-bit data is stored in each of the plurality of non-volatile memory cells.

9. The memory device according to claim 8, wherein, The verification circuit includes: Multiple current sensing circuits, each performing a verification operation for a first programming state, a second programming state, and a third programming state, to output a pass signal or a failure signal for each of the first programming state, the second programming state, and the third programming state; and The first component outputs a programming success signal when the plurality of current sensing circuits output the pass signal.

10. A method for operating a memory device, the method comprising the steps of: Receives multi-bit data to be programmed into multiple non-volatile memory cells; A programming pulse is applied to at least two non-volatile memory cells in the erase state among the plurality of non-volatile memory cells to gradually increase the threshold voltage of the at least two non-volatile memory cells from the erase state to a first programming state, the first programming state being the lowest programming state among the plurality of programming states corresponding to the multi-bit data. Perform a first verification operation to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state; Based on the result of the first verification operation, a single first programming pulse is applied to the first non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state, the first programming pulse corresponding to the difference between the first programming state and the second programming state; as well as Based on the result of the first verification operation, a single second programming pulse is applied to the second non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

11. The method according to claim 10, in, The at least two non-volatile memory cells include non-volatile memory cells to be programmed to have threshold voltages corresponding to the first programming state, the second programming state, and the third programming state, and The result of the first verification operation is determined based on whether the ratio of the non-volatile memory cells having a threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference value.

12. The method of claim 10, further comprising performing a second verification operation for the second programming state and the third programming state after applying the first programming pulse and the second programming pulse.

13. The method of claim 12, further comprising, when it is determined, based on the result of the second verification operation, that the first non-volatile memory cell fails to have a threshold voltage corresponding to the second programming state, applying a programming pulse to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell.

14. The method of claim 12, further comprising, when it is determined, based on the result of the second verification operation, that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third programming state, applying a programming pulse to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell.

15. The method according to claim 12, further comprising the following steps: A verification operation for the first programming state is performed during the second verification operation; as well as When it is determined, as a result of the verification operation during the second verification operation, that some of the at least two non-volatile memory cells fail to have a threshold voltage corresponding to the first programming state, a programming pulse is applied to some of the at least two non-volatile memory cells to gradually increase the threshold voltage of some of the at least two non-volatile memory cells to the first programming state.

16. A memory system, the memory system comprising: A controller that receives data from an external device, determines the location where the data will be stored, and generates multiple bits of data to be stored in the location. as well as The memory device: Receive the multi-bit data based on the location from the controller. A programming pulse is applied to at least two non-volatile memory cells in an erase state among a plurality of non-volatile memory cells to gradually increase the threshold voltage of the at least two non-volatile memory cells from the erase state to a first programming state, the first programming state being the lowest programming state among a plurality of programming states corresponding to the multi-bit data. Perform a first verification operation to determine whether the at least two non-volatile memory cells have a threshold voltage corresponding to the first programming state. Based on the result of the first verification operation, a single first programming pulse is applied to the first non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the first non-volatile memory cell to a second programming state higher than the first programming state. The first programming pulse corresponds to the difference between the first programming state and the second programming state. Based on the result of the first verification operation, a single second programming pulse is applied to the second non-volatile memory cell among the at least two non-volatile memory cells to increase the threshold voltage of the second non-volatile memory cell to a third programming state higher than the second programming state, the second programming pulse corresponding to the difference between the first programming state and the third programming state.

17. The memory system according to claim 16, wherein, The memory device also sends a completion signal to the controller when the programming operation on the multi-bit data is completed.

18. The memory system according to claim 16, in, The at least two non-volatile memory cells include non-volatile memory cells to be programmed to have threshold voltages corresponding to the first programming state, the second programming state, and the third programming state, and The result of the first verification operation is determined based on whether the ratio of the non-volatile memory cells having a threshold voltage corresponding to the first programming state among the at least two non-volatile memory cells is equal to or greater than a reference value.

19. The memory system according to claim 16, wherein, The memory device also performs a second verification operation for the second programming state and the third programming state after the first programming pulse and the second programming pulse are applied.

20. The memory system of claim 19, wherein, The memory device also includes: When it is determined, as a result of the second verification operation, that the first non-volatile memory cell fails to have the threshold voltage corresponding to the second programming state, a programming pulse is applied to the first non-volatile memory cell to gradually increase the threshold voltage of the first non-volatile memory cell; and When it is determined, as a result of the second verification operation, that the second non-volatile memory cell fails to have a threshold voltage corresponding to the third programming state, a programming pulse is applied to the second non-volatile memory cell to gradually increase the threshold voltage of the second non-volatile memory cell.

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