Multilayer Ceramic Capacitors

Abstract

Provided is a stacked ceramic capacitor, which is an LW inversion type stacked ceramic capacitor capable of suppressing the deterioration of the self-alignment effect and performing stable mounting. In the stacked ceramic capacitor (1), when the length in the length direction connecting the first end face (LS1) and the second end face (LS2) of the stacked body (10) is set to 1, the length in the width direction connecting the first side face (WS1) and the second side face (WS2) is set to w, and the length in the height direction connecting the first main face (TS1) and the second main face (TS2) is set to t, in a dimensional relationship of w>1>t, there is an opening (H) that exposes the surface of the stacked body (10) on the fourth face (40A4) and the fifth face (40A5) of the first external electrode (40A) and the ninth face (40B4) and the tenth face (40B5) of the second external electrode (40B).

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, there are known laminated ceramic capacitors. A typical laminated ceramic capacitor has a substantially rectangular parallelepiped laminate in which the dimension in the length direction L is longer than the dimension in the width direction W, and external electrodes are provided at both ends of the laminate in the length direction L. On the other hand, in order to reduce ESL, there are also known so-called LW reverse type laminated ceramic capacitors in which the size relationship between the dimension in the length direction L and the dimension in the width direction W of the laminate is reversed (see Patent Documents 1 and 2).

[0003] In addition, in recent years, as the mounting density of substrates has increased, the mounting area of ​​multilayer ceramic capacitors has decreased. As a result, the demand for multilayer ceramic capacitors that are mounted at the lower end of the substrate using the PoP (Package on Package) mounting method and the LSC (Land side Capacitor) type has increased. As such multilayer ceramic capacitors mounted in the LSC (Land side Capacitor) type, a thin multilayer ceramic capacitor with a thinner height direction is sought.

[0004] Prior Art Literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2020-57753

[0007] Patent Document 2: Japanese Patent Application Publication No. 2020-61524 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] Patent document 2 discloses an LW inversion type laminated ceramic electronic component, in which a recessed portion extending from the end edge toward the first face portion is provided at the end edge of at least one of the fourth face portion and the fifth face portion of the external electrode, and the two side portions in the third direction of the recess serve as covering portions of the ridges of the two faces in the second direction of the component body.

[0010] However, in the laminated ceramic electronic component disclosed in Patent Document 2, it is believed that the area and shape of the covering portion of the ridge portion of the two surfaces of the second direction of the covering component body are deviated due to the formation position and thickness deviation of the base conductor layer and the covering conductor layer arranged on the base conductor layer. Here, when the LW inversion type laminated ceramic electronic component is mounted on the mounting substrate using solder, due to the left and right differences in the area and shape of the covering portion, the wetting mode of the solder relative to the covering portion changes on each surface, and the tensile stress of the solder may be applied differently. As a result, it is believed that the self-alignment effect is deteriorated. As a result, the laminated ceramic electronic component is easy to rotate or tilt, and the mounting performance may be reduced. It should be noted that since the distance between the pads of the substrate on which the LW inversion type laminated ceramic electronic component is mounted is short, when the self-alignment effect is deteriorated and the laminated ceramic electronic component is rotated significantly, it will be installed as an external electrode spanning pads with different polarities, which may cause a short circuit failure.

[0011] An object of the present invention is to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting.

[0012] Means used to solve problems

[0013] The multilayer ceramic capacitor of the present invention comprises: a multilayer body having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the height direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and a second external electrode having At least any one of the sixth face portion located on the second end face, the seventh face portion located on a portion of the first main face, and the eighth face portion located on a portion of the second main face, the ninth face portion located on a portion of the first side face, and the tenth face portion located on a portion of the second side face, wherein, when the length in the longitudinal direction connecting the first end face and the second end face of the stack is set to l, the length in the width direction connecting the first side face and the second side face is set to w, and the length in the height direction connecting the first main face and the second main face is set to t, the size relationship of w>l>t is established, and there is an opening portion that exposes the surface of the stack on the fourth face portion and the fifth face portion and the ninth face portion and the tenth face portion.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide an LW inversion type multilayer ceramic capacitor capable of suppressing deterioration of the self-alignment effect and performing stable mounting. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a perspective view of the appearance of a multilayer ceramic capacitor according to an embodiment.

[0017] Figure 2 It is viewed from the first side along the direction of arrow II Figure 1 The following is an axial view of a stacked ceramic capacitor.

[0018] Figure 3 It is viewed from the second side along the direction of arrow III Figure 1 The following is an axial view of a stacked ceramic capacitor.

[0019] Figure 4 The first main surface is viewed from the direction of arrow IV. Figure 2 The following is an axial view of a stacked ceramic capacitor.

[0020] Figure 5 The second main surface is viewed from the direction of arrow V. Figure 2 The following is an axial view of a stacked ceramic capacitor.

[0021] Figure 6 yes Figure 4 A cross-sectional view of the multilayer ceramic capacitor taken along line VI-VI is shown.

[0022] Figure 7 yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor taken along line VII-VII shown.

[0023] Fig. 8A yes Figure 6 The cross-sectional view taken along line VIIIA-VIIIA of the multilayer ceramic capacitor shown is a diagram showing the first internal electrode layer.

[0024] Figure 8B yes Figure 6 The cross-sectional view taken along line VIIIB-VIIIB of the multilayer ceramic capacitor shown is a diagram showing the second internal electrode layer.

[0025] Fig. 9 yes Figure 4 The cross-sectional view taken along line IX-IX of the multilayer ceramic capacitor shown is a view showing a first side surface of the multilayer body.

[0026] Fig. 10A yes Figure 6The enlarged view of the XA portion in FIG. 1 is a view showing a cross section of the first external electrode.

[0027] Fig. 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a view showing a cross section of the second external electrode.

[0028] Fig.11A is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10A The corresponding figure.

[0029] Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode of the multilayer ceramic capacitor of the above-mentioned embodiment, Fig. 10B The corresponding figure.

[0030] Fig.12 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0031] Fig.13 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0032] Fig.14 It is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the above-mentioned embodiment.

[0033] Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrodes of the multilayer ceramic capacitor according to the above embodiment, Figure 1 The corresponding figure.

[0034] Fig.16A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 1, which is similar to Figure 1 The corresponding figure.

[0035] Fig. 16B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0036] Fig. 16C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0037] Fig.17A is a perspective view of the appearance of the multilayer ceramic capacitor of Comparative Example 2. Figure 1 The corresponding figure.

[0038] Fig. 17B is a diagram showing the first internal electrode layer of the multilayer ceramic capacitor of the comparative example, Fig. 8A The corresponding figure.

[0039] Fig. 17C is a diagram showing the second internal electrode layer of the multilayer ceramic capacitor of the comparative example, Figure 8B The corresponding figure.

[0040] Fig.18A It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0041] Fig.18B It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0042] Fig. 18C It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0043] Fig.18D It is a figure for demonstrating the evaluation method of the mountability in the experimental example.

[0044] Description of Reference Numerals

[0045] 1. Multilayer ceramic capacitor;

[0046] 10 laminate;

[0047] 11 inner part;

[0048] 12 first main surface side outer layer portion;

[0049] 13 second main surface side outer layer portion;

[0050] LS1 first end face;

[0051] LS2 second end face;

[0052] WS1 first side;

[0053] WS2 second side;

[0054] TS1 first main surface;

[0055] TS2 second main surface;

[0056] l Length in the longitudinal direction;

[0057] w is the length in width direction;

[0058] t is the length in height direction;

[0059] 20 dielectric layer;

[0060] 30 internal electrode layer;

[0061] 31 first internal electrode layer;

[0062] 31A: a first opposing electrode portion;

[0063] 31B first lead-out portion;

[0064] 31C second lead-out section;

[0065] 31D third lead-out section;

[0066] 32 second internal electrode layer;

[0067] 32A: a second opposing electrode portion;

[0068] 32B fourth lead-out portion;

[0069] 32C Fifth lead-out section;

[0070] 32D sixth lead-out section;

[0071] 40 external electrodes;

[0072] 40A first external electrode;

[0073] 40A1 first face;

[0074] 40A2 Second facial area;

[0075] 40A3 third face;

[0076] 40A4 fourth face;

[0077] 40A5 fifth face;

[0078] 40B second external electrode;

[0079] 40B1 sixth facial part;

[0080] 40B2 seventh face;

[0081] 40B3 eighth face;

[0082] 40B4 9th face;

[0083] 40B5 tenth face;

[0084] H opening;

[0085] 50A first base electrode layer;

[0086] 51A first film layer;

[0087] 50B second base electrode layer;

[0088] 51B second film layer;

[0089] 60A first plating layer;

[0090] 60B second plating layer;

[0091] L length direction;

[0092] W width direction;

[0093] T Stacking direction. DETAILED DESCRIPTION

[0094] Hereinafter, a multilayer ceramic capacitor 1 according to an embodiment of the present disclosure will be described. Figure 1 It is a perspective view of the appearance of the multilayer ceramic capacitor 1 according to the present embodiment. Figure 2 It is viewed from the first side WS1 side along the direction of arrow II Figure 1 An arrow view of the multilayer ceramic capacitor 1 shown. Figure 3 It is observed from the second side WS2 side along the direction of arrow III Figure 1 An arrow view of the multilayer ceramic capacitor 1 shown. Figure 4 The first main surface TS1 is viewed from the direction of arrow IV. Figure 2 An arrow view of the multilayer ceramic capacitor 1 shown. Figure 5 The second main surface TS2 is viewed along the direction of arrow V. Figure 2 An arrow view of the multilayer ceramic capacitor 1 shown. Figure 6 yes Figure 4 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VI-VI. Figure 7 yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VII-VII. Fig. 8A yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIA-VIIIA. Figure 8B yes Figure 6 FIG. 1 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line VIIIB-VIIIB. Fig. 9 yes Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 taken along the line IX-IX is a view showing the first side surface WS1 of the multilayer body 10 . Fig. 10A yes Figure 6 The enlarged view of the XA portion in FIG. 1 is a view showing a cross section of the first external electrode 40A. Fig. 10B yes Figure 6 The enlarged view of the XB portion in FIG. 1 is a view showing a cross section of the second external electrode 40B.

[0095] The multilayer ceramic capacitor 1 includes a multilayer body 10 and external electrodes 40 .

[0096] exist Figures 1 to 9The XYZ orthogonal coordinate system is shown in FIG. The length direction L of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Y direction. The width direction W of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the X direction. The height direction T of the multilayer ceramic capacitor 1 and the multilayer body 10 corresponds to the Z direction. Here, Figure 6 The section shown is also referred to as the LT section. Figure 7 The section shown is also referred to as the WT section. Fig. 8A and Figure 8B The section shown is also referred to as the LW section.

[0097] like Figures 1 to 5 As shown, the stack 10 includes a first main surface TS1 and a second main surface TS2 opposite to each other in the height direction T, a first end surface LS1 and a second end surface LS2 opposite to each other in the length direction L orthogonal to the height direction T, and a first side surface WS1 and a second side surface WS2 opposite to each other in the width direction W orthogonal to the height direction T and the length direction L.

[0098] The laminate 10 has a substantially rectangular parallelepiped shape. Preferably, roundness is applied to the corners and ridges of the laminate 10. The corner is the portion where three faces of the laminate intersect, and the ridge is the portion where two faces of the laminate intersect. It should be noted that concavities and convexities may also be formed on a portion or all of the surface constituting the laminate 10.

[0099] like Figure 6 and Figure 7 As shown, the laminate 10 includes an inner layer portion 11 , and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged in the height direction T so as to sandwich the inner layer portion 11 .

[0100] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first main surface TS1 side to the internal electrode layer 30 located closest to the second main surface TS2 side in the height direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite to each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and substantially functions as a capacitor. It should be noted that the inner layer portion 11 is also referred to as an effective layer portion.

[0101] The plurality of dielectric layers 20 are composed of a dielectric material. The dielectric material is, for example, a ceramic material. The dielectric material may also be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. When these components are the main components, it is also possible to add, according to the desired characteristics of the laminate, a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, a Ni compound, etc., whose content is less than that of the main component.

[0102] The thickness of the dielectric layer 20 is preferably not less than 0.5 μm and not more than 10 μm. The number of laminated dielectric layers 20 is preferably not less than 15 and not more than 700. It should be noted that the number of dielectric layers 20 is the sum of the number of dielectric layers of the inner layer portion 11 and the number of dielectric layers of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0103] The plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 and a plurality of second internal electrode layers 32. The first internal electrode layers 31 are arranged on the plurality of dielectric layers 20 and are led out to the first end surface LS1. The second internal electrode layers 32 are arranged on the plurality of dielectric layers 20 and are led out to the second end surface. The plurality of first internal electrode layers 31 and the plurality of second internal electrode layers 32 are alternately arranged in the height direction T of the stack 10 with the dielectric layers 20 interposed therebetween. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layer 20.

[0104] like Fig. 8A As shown, the first internal electrode layer 31 has a first opposing electrode portion 31A opposite to the second internal electrode layer 32, a first lead portion 31B led out from the first opposing electrode portion 31A to the first end surface LS1, a portion of the first side surface WS1 and a portion of the second side surface WS2, a second lead portion 31C led out from the first opposing electrode portion 31A to a portion of the first side surface WS1, and a third lead portion 31D led out from the first opposing electrode portion 31A to a portion of the second side surface WS2.

[0105] The first opposing electrode portion 31A is located inside the stacked body 10. The first lead portion 31B is connected to the first opposing electrode portion 31A and is exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2. The second lead portion 31C is connected to the first opposing electrode portion 31A and is exposed at a portion of the first side surface WS1. The third lead portion 31D is connected to the first opposing electrode portion 31A and is exposed at a portion of the second side surface WS2.

[0106] The second lead portion 31C is disposed at a distance from the portion of the first lead portion 31B led to the first side surface WS1 in the longitudinal direction L. The third lead portion 31D is disposed at a distance from the portion of the first lead portion 31B led to the second side surface WS2 in the longitudinal direction L.

[0107] like Figure 8BAs shown, the second internal electrode layer 32 has a second opposing electrode portion 32A opposite to the first internal electrode layer 31, a fourth lead portion 32B led from the second opposing electrode portion 32A to the second end surface LS2, a portion of the first side surface WS1 and a portion of the second side surface WS2, a fifth lead portion 32C led from the second opposing electrode portion 32A to a portion of the first side surface WS1, and a sixth lead portion 32D led from the second opposing electrode portion 32A to a portion of the second side surface WS2.

[0108] The second opposing electrode portion 32A is located inside the stacked body 10. The fourth lead portion 32B is connected to the second opposing electrode portion 32A and is exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2. The fifth lead portion 32C is connected to the second opposing electrode portion 32A and is exposed at a portion of the first side surface WS1. The sixth lead portion 32D is connected to the second opposing electrode portion 32A and is exposed at a portion of the second side surface WS2.

[0109] The fifth lead portion 32C is disposed at a distance from the portion of the fourth lead portion 32B extending toward the first side surface WS1 in the longitudinal direction L. The sixth lead portion 32D is disposed at a distance from the portion of the fourth lead portion 32B extending toward the second side surface WS2 in the longitudinal direction L.

[0110] Fig. 9 yes Figure 4 The cross-sectional view of the multilayer ceramic capacitor 1 along the line IX-IX shown in FIG. 1 is a view showing the first side surface WS1 of the multilayer body 10. Fig. 8A and Figure 8B It is also shown in Fig. 9 The IX-IX line of the cross-sectional view is located. Fig. 9 As shown, the first lead portion 31B and the second lead portion 31C of the first internal electrode layer 31 and the fourth lead portion 32B and the fifth lead portion 32C of the second internal electrode layer 32 are exposed on the first side surface WS1 of the laminate 10. The first lead portion 31B and the second lead portion 31C are exposed on the surface of the laminate 10 in a separated state. The fourth lead portion 32B and the fifth lead portion 32C are exposed on the surface of the laminate 10 in a separated state.

[0111] Although not shown in the figure, the first lead portion 31B and the third lead portion 31D of the first internal electrode layer 31 and the fourth lead portion 32B and the sixth lead portion 32D of the second internal electrode layer 32 are exposed on the second side surface WS2 side, similarly to the first side surface WS1 side. The first lead portion 31B and the third lead portion 31D are exposed on the surface of the stacked body 10 in a separated state. The fourth lead portion 32B and the sixth lead portion 32D are exposed on the surface of the stacked body 10 in a separated state.

[0112] Thus, the shape of the external electrode 40 of the present embodiment having the opening H described later can be realized. Furthermore, the distance between the second lead portion 31C of the first internal electrode layer 31 and the fifth lead portion 32C of the second internal electrode layer 32 can be shortened, and the distance between the third lead portion 31D of the first internal electrode layer 31 and the sixth lead portion 32D of the second internal electrode layer 32 can be shortened, so the path for current flow can be shortened. Therefore, ESL can be reduced.

[0113] In the present embodiment, the first counter electrode portion 31A and the second counter electrode portion 32A are opposed to each other via the dielectric layer 20 to form a capacitor, thereby exhibiting the characteristics of a capacitor.

[0114] The shapes of the first counter electrode portion 31A and the second counter electrode portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or may be formed to be inclined.

[0115] The shapes of the first lead portion 31B and the fourth lead portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or formed obliquely. In the present embodiment, the shapes of the first lead portion 31B and the fourth lead portion 32B are substantially T-shaped with a portion of the corner of the rectangular shape removed.

[0116] The shapes of the second lead portion 31C, the third lead portion 31D, the fifth lead portion 32C, and the sixth lead portion 32D are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or inclined.

[0117] It should be noted that the dimension of the width direction W of the portion of the first lead portion 31B exposed at the first end surface LS1 is larger than the dimension of the width direction of the first opposing electrode portion 31A. The dimension of the width direction W of the portion of the fourth lead portion 32B exposed at the second end surface LS2 is larger than the dimension of the width direction of the second opposing electrode portion 32A.

[0118] The length direction L dimensions of the portion of the first lead portion 31B and the fourth lead portion 32B exposed at a portion of the first side surface WS1 are preferably 30 μm or more and 230 μm or less. The length direction L dimensions of the portion of the first lead portion 31B and the fourth lead portion 32B exposed at a portion of the second side surface WS2 are preferably 30 μm or more and 230 μm or less. The length direction L dimensions of the portion of the second lead portion 31C and the fifth lead portion 32C exposed at a portion of the first side surface WS1 are preferably 30 μm or more and 230 μm or less. The length direction L dimensions of the portion of the third lead portion 31D and the sixth lead portion 32D exposed at a portion of the second side surface WS2 are preferably 30 μm or more and 230 μm or less.

[0119] The sizes of the lead portions exposed on the side surfaces of the stacked bodies 10 may be substantially equal. However, the size of the portion of the second lead portion 31C and the fifth lead portion 32C exposed on a portion of the first side surface WS1 in the length direction L may be longer than the size of the portion of the first lead portion 31B and the fourth lead portion 32B exposed on a portion of the first side surface WS1 in the length direction L. The size of the portion of the third lead portion 31D and the sixth lead portion 32D exposed on a portion of the second side surface WS2 in the length direction L may be longer than the size of the portion of the first lead portion 31B and the fourth lead portion 32B exposed on a portion of the second side surface WS2 in the length direction L.

[0120] The first internal electrode layer 31 and the second internal electrode layer 32 are made of a suitable conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0121] The thickness of each of the first internal electrode layer 31 and the second internal electrode layer 32 is preferably about 0.2 μm or more and 2.0 μm or less, for example. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 15 or more and 200 or less.

[0122] The first main surface side outer layer portion 12 is located on the first main surface TS1 side of the stack 10. The first main surface side outer layer portion 12 is a collection of a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. That is, the first main surface side outer layer portion 12 is formed by a plurality of dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 located closest to the first main surface TS1 among the plurality of internal electrode layers 30. The dielectric layer 20 used in the first main surface side outer layer portion 12 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0123] The second main surface side outer layer portion 13 is located on the second main surface TS2 side of the stacked body 10. The second main surface side outer layer portion 13 is an aggregate of a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. That is, the second main surface side outer layer portion 13 is formed by a plurality of dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 located closest to the second main surface TS2 among the plurality of internal electrode layers 30. The dielectric layer 20 used in the second main surface side outer layer portion 13 may be the same as the dielectric layer 20 used in the internal layer portion 11.

[0124] As described above, the laminated body 10 includes the plurality of laminated dielectric layers 20 and the plurality of internal electrode layers 30 laminated on the dielectric layers 20. That is, the laminated ceramic capacitor 1 includes the laminated body 10 in which the dielectric layers 20 and the internal electrode layers 30 are alternately laminated.

[0125] It should be noted that the laminate 10 has an opposing electrode portion 11E. The opposing electrode portion 11E is a portion where the first opposing electrode portion 31A of the first internal electrode layer 31 and the second opposing electrode portion 32A of the second internal electrode layer 32 face each other. The opposing electrode portion 11E is configured as a part of the inner layer portion 11. Fig. 8A and Figure 8B 2 shows the range of the opposing electrode portion 11E in the width direction W and the length direction L. It should be noted that the opposing electrode portion 11E is also referred to as a capacitor effective portion.

[0126] It should be noted that the stack 10 has an end face side outer layer portion. The end face side outer layer portion has a first end face side outer layer portion LG1 located on the first end face LS1 side, and a second end face side outer layer portion LG2 located on the second end face LS2 side. The first end face side outer layer portion LG1 is a portion including the dielectric layer 20 and the first lead portion 31B located between the opposing electrode portion 11E and the first end face LS1. That is, the first end face side outer layer portion LG1 is a collection of portions of the plurality of dielectric layers 20 on the first end face LS1 side and the plurality of first lead portions 31B. The second end face side outer layer portion LG2 is a portion including the dielectric layer 20 and the fourth lead portion 32B located between the opposing electrode portion 11E and the second end face LS2. That is, the second end face side outer layer portion LG2 is a collection of portions of the plurality of dielectric layers 20 on the second end face LS2 side and the plurality of fourth lead portions 32B. Figure 6 , Fig. 8A and Figure 8B , the range of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 in the length direction L is shown. It should be noted that the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2 are also referred to as L gaps or end gaps.

[0127] It should be noted that the stack 10 has a side outer layer portion. The side outer layer portion has a first side outer layer portion WG1 located on the first side WS1 side, and a second side outer layer portion WG2 located on the second side WS2 side. The first side outer layer portion WG1 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the first side WS1. That is, the first side outer layer portion WG1 is a collection of portions of the plurality of dielectric layers 20 on the first side WS1 side. The second side outer layer portion WG2 is a portion including the dielectric layer 20 located between the opposing electrode portion 11E and the second side WS2. That is, the second side outer layer portion WG2 is a collection of portions of the plurality of dielectric layers 20 on the second side WS2 side. Figure 7 , Fig. 8A and Figure 8B , the range of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2 in the width direction W is shown. It should be noted that the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2 are also referred to as W gaps or side gaps.

[0128] like Figures 6 to 8B As shown in FIG. 1 , when the length in the length direction L connecting the first end face LS1 and the second end face LS2 of the stacked body 10 is set to l, the length in the width direction W connecting the first side face WS1 and the second side face WS2 is set to w, and the length in the height direction T connecting the first main face TS1 and the second main face TS2 is set to t, the dimensional relationship between them is w>l>t. Thus, the width of the lead portion at the end face of the internal electrode layer 30 can be widened. In addition, the distance between the first external electrode 40A and the second external electrode 40B can be shortened, so that the ESL of the stacked ceramic capacitor 1 can be reduced.

[0129] The length l of the length direction L of the first end face LS1 and the second end face LS2 of the connecting stack 10 is preferably greater than 0.05mm and less than 0.7mm. In addition, the length w of the width direction W of the first side surface WS1 and the second side surface WS2 of the connecting stack 10 is preferably greater than 0.15mm and less than 1.5mm. In addition, the length t of the height direction T of the first main surface TS1 and the second main surface TS2 of the connecting stack 10 is preferably less than 150μm. Thus, high-density installation can be achieved. In addition, the length t of the height direction T of the first main surface TS1 and the second main surface TS2 of the connecting stack 10 is preferably less than 100μm, more preferably less than 50μm. Thus, higher-density installation can be achieved.

[0130] In addition, each dimension of l, w, and t of the laminated body 10 was measured by the following method.

[0131] First, the w dimension of the laminated body 10 is measured. Specifically, the w dimension of the laminated body 10 is measured using a micrometer at the center position in the longitudinal direction L of the laminated ceramic capacitor 1, that is, at the position L / 2 of the laminated ceramic capacitor 1.

[0132] Next, the l dimension and t dimension of the laminated body 10 are measured. First, the laminated ceramic capacitor 1 that is the same as the laminated ceramic capacitor 1 whose w dimension has been measured is ground until it reaches the center position in the width direction W of the laminated ceramic capacitor 1, that is, the W / 2 position of the laminated ceramic capacitor 1, so as to be parallel to the LT plane. Then, the LT cross section exposed by grinding is observed using a microscope. The l dimension of the laminated body 10 is measured using a microscope at the center position in the height direction T of the laminated body 10 in the LT cross section, that is, the t / 2 position of the laminated body 10. The t dimension of the laminated body 10 is measured using a microscope at the center position in the length direction L of the laminated body 10 in the LT cross section, that is, the l / 2 position of the laminated body 10.

[0133] The external electrode 40 includes a first external electrode 40A arranged on the first end surface LS1 side and a second external electrode 40B arranged on the second end surface LS2 side.

[0134] The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A of the present embodiment has a first face portion 40A1 located on the first end surface LS1, a second face portion 40A2 located on a portion of the first main surface TS1, a third face portion 40A3 located on a portion of the second main surface TS2, a fourth face portion 40A4 located on a portion of the first side surface WS1, and a fifth face portion 40A5 located on a portion of the second side surface WS2. It should be noted that the first external electrode 40A preferably has at least any one of the second face portion 40A2 located on a portion of the first main surface TS1 and the third face portion 40A3 located on a portion of the second main surface TS2, the first face portion 40A1 located on the first end surface LS1, the fourth face portion 40A4 located on a portion of the first side surface WS1, and the fifth face portion 40A5 located on a portion of the second side surface WS2.

[0135] The first surface portion 40A1 covers the entire first end surface LS1 and is a portion connected to the first internal electrode layer 31. Either the second surface portion 40A2 or the third surface portion 40A3 is a portion connected to a pad of the mounting substrate.

[0136] The fourth surface portion 40A4 is a portion connected to the first lead portion 31B and the second lead portion 31C exposed on the first side surface WS1. The fifth surface portion 40A5 is a portion connected to the first lead portion 31B and the third lead portion 31D exposed on the second side surface WS2. In this way, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31D are all connected to the first external electrode 40A which is the same external electrode.

[0137] The fourth surface 40A4 and the fifth surface 40A5 have openings H that expose the laminate 10. The openings H are surrounded by a material constituting the external electrode 40. The openings H are recessed from the surfaces of the fourth surface 40A4 and the fifth surface 40A5, and the surface of the laminate 10 is exposed at the bottom.

[0138] By forming such an opening portion H, in the fourth surface 40A4 and the fifth surface 40A5, connecting surfaces serving as solder-wetting bulges are formed on both sides of the opening portion H in the length direction L of the stack 10, and the connecting surfaces connect the second surface 40A2 and the third surface 40A3 in the height direction.

[0139] like Figure 2 As shown, the fourth face portion 40A4 has a first connection surface F1 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the center side of the opening portion H in the longitudinal direction L of the stacked body 10. In addition, the fourth face portion 40A4 has a second connection surface F2 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the first end surface LS1 side of the opening portion H. The second connection surface F2 is connected to the first face portion 40A1.

[0140] like Figure 3 As shown, the fifth face portion 40A5 has a third connecting surface F3 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the center side of the opening portion H in the longitudinal direction L of the stacked body 10. In addition, the fifth face portion 40A5 has a fourth connecting surface F4 connecting the second face portion 40A2 and the third face portion 40A3 in the height direction on the first end surface LS1 side of the opening portion H. The fourth connecting surface F4 is connected to the first face portion 40A1.

[0141] The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B of the present embodiment has a sixth face portion 40B1 located on the second end surface LS2, a seventh face portion 40B2 located on a portion of the first main surface TS1, an eighth face portion 40B3 located on a portion of the second main surface TS2, a ninth face portion 40B4 located on a portion of the first side surface WS1, and a tenth face portion 40B5 located on a portion of the second side surface WS2. It should be noted that the second external electrode 40B preferably has at least any one of the seventh face portion 40B2 located on a portion of the first main surface TS1 and the eighth face portion 40B3 located on a portion of the second main surface TS2, the first external electrode 40A, the sixth face portion 40B1 located on the second end surface LS2, the ninth face portion 40B4 located on a portion of the first side surface WS1, and the tenth face portion 40B5 located on a portion of the second side surface WS2.

[0142] The sixth surface portion 40B1 covers the entire second end surface LS2 and is a portion connected to the second internal electrode layer 32. Either the seventh surface portion 40B2 or the eighth surface portion 40B3 is a portion connected to a pad of the mounting substrate.

[0143] The ninth surface portion 40B4 is a portion connected to the fourth lead portion 32B and the fifth lead portion 32C exposed on the first side surface WS1. The tenth surface portion 40B5 is a portion connected to the fourth lead portion 32B and the sixth lead portion 32D exposed on the second side surface WS2. In this way, the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the second external electrode 40B which is the same external electrode.

[0144] The ninth surface 40B4 and the tenth surface 40B5 have openings H that expose the laminate 10. The openings H are surrounded by the material constituting the external electrode 40. The openings H are recessed from the surfaces of the ninth surface 40B4 and the tenth surface 40B5, and the surface of the laminate 10 is exposed at the bottom.

[0145] By forming such an opening portion H, in the ninth face portion 40B4 and the tenth face portion 40B5, connecting surfaces serving as solder-wetting bulges are formed on both sides of the opening portion H in the length direction L of the stack 10, and the connecting surfaces connect the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction.

[0146] like Figure 2As shown, the ninth face portion 40B4 has a fifth connecting surface F5 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the ninth face portion 40B4 has a sixth connecting surface F6 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the second end surface LS2 side of the opening H. The sixth connecting surface F6 is connected to the sixth face portion 40B1.

[0147] like Figure 3 As shown, the tenth face portion 40B5 has a seventh connecting surface F7 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the center side of the opening H in the longitudinal direction L of the stacked body 10. In addition, the tenth face portion 40B5 has an eighth connecting surface F8 connecting the seventh face portion 40B2 and the eighth face portion 40B3 in the height direction on the second end surface LS2 side of the opening H. The eighth connecting surface F8 is connected to the sixth face portion 40B1.

[0148] Thus, the amount of wetting and swelling of the solder relative to the first side surface WS1 and the second side surface WS2 of the stacked body 10 can be made appropriate. In addition, since the solder surrounds the opening H and swells, the solder can be divided into two parts with the opening H as a boundary and swell. Therefore, on the mounting surface side of the multilayer ceramic capacitor 1, the point where the stress is applied by the solder can be dispersed into two points. Therefore, the self-alignment effect is improved, and the mounting property of the multilayer ceramic capacitor 1 is stable. As a result, the multilayer ceramic capacitor 1 can be prevented from tilting. In addition, the multilayer ceramic capacitor 1 can be prevented from rotating and causing a short circuit failure.

[0149] It should be noted that the openings H provided on the fourth face 40A4, the fifth face 40A5, the ninth face 40B4 and the tenth face 40B5 are preferably formed in substantially the same size. It should be noted that the shape of the opening H is not particularly limited, and is preferably rectangular, polygonal, circular or elliptical.

[0150] The opening H formed in the fourth surface 40A4 and the fifth surface 40A5 is preferably arranged at the center of the fourth surface 40A4 and the fifth surface 40A5 in the height direction T. The opening H formed in the fourth surface 40A4 and the fifth surface 40A5 is preferably arranged to be offset to the first end surface LS1 side from the center of the length direction L of the fourth surface 40A4 and the fifth surface 40A5 or the center of the length direction L of the fourth surface 40A4 and the fifth surface 40A5. By arranging the opening H formed in the fourth surface 40A4 and the fifth surface 40A5 to be offset to the first end surface LS1 side, the area of ​​the first connection surface F1 and the third connection surface F3 as the solder wetted bulge can be ensured.

[0151] The opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 is preferably arranged at the center of the ninth face portion 40B4 and the tenth face portion 40B5 in the height direction T. The opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 is preferably arranged to be offset to the second end face LS2 side from the center of the length direction L of the ninth face portion 40B4 and the tenth face portion 40B5 or the center of the length direction L of the ninth face portion 40B4 and the tenth face portion 40B5. By arranging the opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 to be offset to the second end face LS2 side, the area of ​​the fifth connecting face F5 and the seventh connecting face F7, which are the solder wetted bulges, can be ensured.

[0152] As a result, the solder is easily divided into two parts with the opening H as the boundary and wetted and bulged. Therefore, on the mounting surface side of the multilayer ceramic capacitor 1, the point where the solder applies stress can be dispersed into two points. Therefore, the self-alignment effect is improved, and the mounting property of the multilayer ceramic capacitor 1 is stable. As a result, the multilayer ceramic capacitor can be prevented from tilting. In addition, the multilayer ceramic capacitor 1 can be prevented from rotating and causing a short circuit failure.

[0153] The area of ​​the opening H formed in the fourth face portion 40A4, the fifth face portion 40A5, the ninth face portion 40B4, and the tenth face portion 40B5 is preferably 1% or more and 50% or less relative to the area of ​​each of the fourth face portion 40A4, the fifth face portion 40A5, the ninth face portion 40B4, and the tenth face portion 40B5. More preferably, the area ratio of the opening H is 3% or more and 20% or less. Thus, the self-alignment effect can be exerted, and the effect of suppressing the short-circuit failure caused by the tilt or rotation of the multilayer ceramic capacitor 1 is more significant.

[0154] The area ratio of the opening H is measured using an optical microscope. Figure 2 A method for measuring the area ratio of the opening H in the fourth surface portion 40A4 will be described. In addition, the following description will focus on a method for measuring the area ratio when both the area of ​​the fourth surface portion 40A4 and the opening H are substantially rectangular.

[0155] First, the field of view is set to a magnification at which the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 enters the field of view of the microscope. Next, the contour of the opening H is identified, and the dimension d1 of the length direction L and the dimension d2 of the height direction T of the opening H are measured. Thereafter, the area A1 of the opening H is calculated by the calculation formula A1=d1×d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 of the length direction L and the dimension D2 of the height direction T of the fourth surface 40A4 are measured. Thereafter, the area A2 of the fourth surface 40A4 is calculated by the calculation formula A2=D1×D2. Thereafter, the area ratio of the opening H located on the fourth surface 40A4 to the area of ​​the fourth surface 40A4 is calculated by the calculation formula A1÷A2.

[0156] In the above, as a representative method of measuring the area ratio of the opening H, the method of measuring the area ratio of the opening H located in the fourth surface portion 40A4 is described, but the area ratios of the opening H located in the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are also calculated by the same measuring method. The area ratios of the opening H located in the fourth surface portion 40A4, the fifth surface portion 40A5, the ninth surface portion 40B4, and the tenth surface portion 40B5 are calculated respectively, and then the average value of the area ratios of the four openings H is calculated as the area ratio of the opening H in the multilayer ceramic capacitor 1.

[0157] like Fig. 10A As shown, the first external electrode 40A includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A is disposed on the surface of the laminate 10. The first plating layer 60A is disposed to cover the first base electrode layer 50A.

[0158] like Fig. 10B As shown, the second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B is disposed on the surface of the laminate 10. The second plating layer 60B is disposed to cover the second base electrode layer 50B.

[0159] The first foundation electrode layer 50A and the second foundation electrode layer 50B include at least one selected from a sintered layer, a thin film layer, and the like.

[0160] In this embodiment, the first foundation electrode layer 50A and the second foundation electrode layer 50B are thin film layers. The thin film layer is a layer where metal particles are deposited.

[0161] When the first foundation electrode layer 50A and the second foundation electrode layer 50B are formed of thin film layers, they are preferably formed by a thin film forming method such as sputtering or vapor deposition. Here, a sputtering electrode formed by sputtering will be described.

[0162] The first foundation electrode layer 50A of the present embodiment includes a first thin film layer 51A formed by a sputtering electrode. The second foundation electrode layer 50B includes a second thin film layer 51B formed by a sputtering electrode. When the foundation electrode layer is formed by a sputtering electrode, the sputtering electrode is preferably formed directly on the first main surface TS1 and the second main surface TS2 of the stacked body 10.

[0163] like Figure 6 , Fig. 10A As shown in FIG. 1 , the first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end surface LS1 side on the first main surface TS1 and a portion of the first end surface LS1 side on the second main surface TS2. Specifically, the first thin film layer 51A is preferably arranged on the first main surface TS1. Figure 4 The first thin film layer 51A is preferably arranged on the second main surface TS2. Figure 5 The portion covered by the first external electrode 40A is shown.

[0164] In addition, if Fig. 9 As shown, the first thin film layer 51A is preferably configured on a portion of the first main surface TS1, and is configured on a portion of the first side surface WS1 continuously and slightly around a portion of the first main surface TS1. The first thin film layer 51A is preferably configured on a portion of the second main surface TS2, and is configured on a portion of the first side surface WS1 continuously and slightly around a portion of the second main surface TS2.

[0165] In addition, although not shown in the figure, similarly to the first side surface WS1 side, on the second side surface WS2 side, the first thin film layer 51A is preferably arranged on a portion of the first main surface TS1, and is arranged continuously from a portion on the first main surface TS1 and slightly surrounding a portion of the second side surface WS2. In addition, the first thin film layer 51A is preferably arranged on a portion of the second main surface TS2, and is arranged continuously from a portion on the second main surface TS2 and slightly surrounding a portion of the second side surface WS2.

[0166] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the first main surface TS1, and the chamfered portion of the first side face WS1 side and the chamfered portion of the second side face WS2 side continuous with the portion. The first thin film layer 51A is preferably arranged on a portion of the first end face LS1 side of the second main surface TS2, and the chamfered portion of the first side face WS1 side and the chamfered portion of the second side face WS2 side continuous with the portion. Thus, it is easy to form a thin film layer by sputtering or the like.

[0167] By the above method, when forming the plating layer, the distance between the first thin film layer 51A disposed on a portion of the first side WS1 and a portion of the second side WS2 and the internal electrode layer 30 exposed on the first side WS1 and the second side WS2 can be controlled. Therefore, the plating layer can be easily deposited even on the surface of the stacked body 10 between the first thin film layer 51A disposed on a portion of the first side WS1 and a portion of the second side WS2 and the internal electrode layer 30 exposed on the first side WS1 and the second side WS2.

[0168] like Figure 6 , Fig. 10B As shown in FIG. 1 , the second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the first main surface TS1 on the second end surface LS2 side and a portion of the second main surface TS2 on the second end surface LS2 side. Specifically, the second thin film layer 51B is preferably arranged on the first main surface TS1. Figure 4 The second thin film layer 51B is preferably arranged on the second main surface TS2. Figure 5 The portion covered by the second outer electrode 40B is shown.

[0169] In addition, if Fig. 9 As shown, the second thin film layer 51B is preferably configured on a portion of the first main surface TS1, and is configured on a portion of the first side surface WS1 continuously and slightly around a portion of the first main surface TS1. The second thin film layer 51B is preferably configured on a portion of the second main surface TS2, and is configured on a portion of the first side surface WS1 continuously and slightly around a portion of the second main surface TS2.

[0170] In addition, although not shown in the figure, similarly to the first side surface WS1 side, on the second side surface WS2 side, the second thin film layer 51B is preferably arranged on a portion of the first main surface TS1, and is arranged continuously from a portion on the first main surface TS1 and slightly surrounding a portion of the second side surface WS2. In addition, the second thin film layer 51B is preferably arranged on a portion of the second main surface TS2, and is arranged continuously from a portion on the second main surface TS2 and slightly surrounding a portion of the second side surface WS2.

[0171] For example, when a chamfered portion such as a rounded corner is formed on the ridgeline portion of the stacked body 10, the second thin film layer 51B is preferably arranged on a portion of the second end face LS2 side of the first main surface TS1, and the chamfered portion of the first side face WS1 side and the chamfered portion of the second side face WS2 side continuous with the portion. The second thin film layer 51B is preferably arranged on a portion of the second end face LS2 side of the second main surface TS2, and the chamfered portion of the first side face WS1 side and the chamfered portion of the second side face WS2 side continuous with the portion. Thus, it is easy to form a thin film layer by sputtering or the like.

[0172] By the above method, when forming the plating layer, the distance between the second thin film layer 51B disposed on a portion of the first side WS1 and a portion of the second side WS2 and the internal electrode layer 30 exposed on the first side WS1 and the second side WS2 can be controlled. Therefore, the plating layer can be easily deposited even on the surface of the stacked body 10 between the second thin film layer 51B disposed on a portion of the first side WS1 and a portion of the second side WS2 and the internal electrode layer 30 exposed on the first side WS1 and the second side WS2.

[0173] The thin film layer formed by the sputtering electrode preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo and V. In this way, the fixing force of the external electrode 40 with respect to the stacked body 10 can be improved. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed by a double-layer structure of a Ni-Cr alloy layer and a Ni-Cu alloy layer.

[0174] The thickness of the sputtering electrode in the stacking direction connecting the first main surface TS1 and the second main surface TS2 is preferably 50 nm to 400 nm, and more preferably 50 nm to 130 nm.

[0175] In the case where a sputtering electrode is directly formed on the first main surface TS1 and the second main surface TS2 of the stacked body 10 to configure a base electrode layer, it is preferred to form a base electrode layer of a sintered layer on the first end surface LS1 and the second end surface LS2, or to directly form a plating layer described later without forming a base electrode layer. In the present embodiment, a plating layer described later is directly formed on the first end surface LS1 and the second end surface LS2 without forming a base electrode layer.

[0176] It should be noted that the first base electrode layer 50A and the second base electrode layer 50B may be sintered layers as described in a modified example later. The sintered layer preferably includes a metal component and any one of a glass component or a ceramic component, or includes both of them. The metal component, for example, includes at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component, for example, includes at least one selected from B, Si, Ba, Mg, Al, Li, etc. The ceramic component may use the same type of ceramic material as the dielectric layer 20, or a different type of ceramic material from the dielectric layer 20. The ceramic component, for example, includes at least one selected from BaTiO3, CaTiO3, (Ba, Ca)TiO3, SrTiO3, CaZrO3, etc.

[0177] The sintered layer is obtained, for example, by applying a conductive paste containing glass and metal to the stacked body 10 and sintering it. The sintered layer can also be obtained by simultaneously sintering a stacked chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the stacked chip, or by applying a conductive paste on the stacked body 10 and sintering it after sintering the stacked chip having an internal electrode layer and a dielectric layer to obtain the stacked body 10. It should be noted that, when simultaneously sintering a stacked chip having an internal electrode layer and a dielectric layer and a conductive paste applied to the stacked chip, the sintered layer is preferably formed by sintering a conductive paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. The sintered layer can also be a plurality of layers.

[0178] It should be noted that the first base electrode layer 50A and the second base electrode layer 50B may not be provided, and a first plating layer 60A and a second plating layer 60B described later may be directly disposed on the laminate 10 .

[0179] The first plating layer 60A is arranged to cover the first base electrode layer 50A.

[0180] The second plating layer 60B is arranged to cover the second base electrode layer 50B.

[0181] The first plating layer 60A and the second plating layer 60B may include, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of a plurality of layers.

[0182] When the base electrode layer is formed by a thin film layer, the plating layer is preferably formed by a three-layer structure of a Cu plating layer as a lower plating layer, a Ni plating layer as a middle plating layer, and a Sn plating layer as an upper plating layer. That is, the first plating layer 60A preferably has a first Cu plating layer 61A, a first Ni plating layer 62A, and a first Sn plating layer 63A. The second plating layer 60B preferably has a second Cu plating layer 61B, a second Ni plating layer 62B, and a second Sn plating layer 63B. However, the first plating layer 60A and the second plating layer 60B are not limited to a three-layer structure, and may also be other layer structures.

[0183] The first Cu plating layer 61A is configured to cover the first end surface LS1 of the stack 10, and the first thin film layer 51A as the first base electrode layer 50A configured on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the first Cu plating layer 61A is also configured to cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the first thin film layer 51A and the internal electrode layer 30 exposed on the surface of the stack 10, and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrowly, so the plating layer is also deposited in the region of these gaps. Therefore, the above-mentioned opening H is formed on the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A.

[0184] The first Ni plating layer 62A is arranged to cover the first Cu plating layer 61A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A. In the present embodiment, the first plating layer 60A is directly electrically connected to the first internal electrode layer 31 .

[0185] The second Cu plating layer 61B is configured to cover the second end surface LS2 of the stack 10, and the second thin film layer 51B as the second base electrode layer 50B configured on the first main surface TS1 and the second main surface TS2 of the stack 10. In the present embodiment, the second Cu plating layer 61B is also configured to cover the exposed portion of the internal electrode layer 30 in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the second thin film layer 51B and the internal electrode layer 30 exposed on the surface of the stack 10, and the gaps between the plurality of internal electrode layers 30 exposed on the surface of the stack 10 are formed narrowly, so the plating layer is also deposited in the region of these gaps. Therefore, the above-mentioned opening H is formed on the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B.

[0186] The second Ni plating layer 62B is arranged to cover the second Cu plating layer 61B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B. In the present embodiment, the second plating layer 60B is directly electrically connected to the second internal electrode layer 32 .

[0187] By providing the plated layer including the Cu plated layer and the Ni plated layer to cover the base electrode layer, the base electrode layer is prevented from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, by providing the Sn plated layer on the surface of the Ni plated layer, the wettability of the solder when mounting the multilayer ceramic capacitor 1 is improved. Thus, the multilayer ceramic capacitor 1 can be easily mounted.

[0188] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of the first Cu plating layer 61A, the first Ni plating layer 62A, the first Sn plating layer 63A, the second Cu plating layer 61B, the second Ni plating layer 62B and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of the first Cu plating layer 61A and the second Cu plating layer 61B is more preferably 5 μm or more and 8 μm or less. In addition, the average thickness of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0189] It should be noted that, when the dimension in the length direction connecting the first end surface LS1 and the second end surface LS2 of the multilayer ceramic capacitor 1 including the stack 10 and the external electrode 40 is set to the L dimension, the L dimension is preferably 0.1 mm or more and 0.8 mm or less. In addition, when the dimension in the width direction connecting the first side surface WS1 and the second side surface WS2 of the multilayer ceramic capacitor 1 is set to the W dimension, the W dimension is preferably 0.2 mm or more and 1.6 mm or less. In addition, when the dimension in the height direction connecting the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is set to the T dimension, the T dimension is preferably 0.05 mm or more and 0.2 mm or less. The L dimension in the length direction of the multilayer ceramic capacitor 1 of the present embodiment is smaller than the W dimension in the width direction of the multilayer ceramic capacitor 1. It should be noted that, in the present embodiment, the height direction connecting the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 is the stacking direction of the dielectric layer 20 and the internal electrode layer 30.

[0190] As described above, in the LW inversion type multilayer ceramic capacitor 1 of the present embodiment, the opening H through which the surface of the multilayer body 10 is exposed is formed on the fourth face 40A4 and the fifth face 40A5 of the first external electrode 40A and the ninth face 40B4 and the tenth face 40B5 of the second external electrode 40B. Thus, it is possible to suppress the deterioration of the self-alignment effect and perform stable mounting. It should be noted that the self-alignment effect refers to the effect that when soldering is performed, a force that reduces the surface area of ​​the molten solder, that is, surface tension, acts on the molten solder, thereby moving the electronic component to be mounted supported by the molten solder, thereby positioning the electronic component. By obtaining this self-alignment effect, it is possible to prevent positional deviation during mounting.

[0191] Hereinafter, a modification of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 of the present embodiment will be described. In the following description, the same reference numerals are given to the same structures as those in the above embodiment, and detailed descriptions thereof will be omitted. Fig.11A and Fig. 11B is a cross-sectional view showing a modified example of the layer structure of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Fig. 10A and Fig. 10B The corresponding figure.

[0192] In this modification, the structure of the external electrode 40 is different from that of the above-described embodiment.

[0193] The first external electrode 40A includes a first base electrode layer 50A and a first plated layer 60A. The first base electrode layer 50A of this modification includes a first sintered layer 52A. The first plated layer 60A of this modification includes a first Ni plated layer 62A and a first Sn plated layer 63A.

[0194] The second external electrode 40B includes a second base electrode layer 50B and a second plated layer 60B. The second base electrode layer 50B of this modification includes a second sintered layer 52B. The second plated layer 60B of this modification includes a second Ni plated layer 62B and a second Sn plated layer 63B.

[0195] In this modification, the first base electrode layer 50A has, for example, a first face portion located on the first end surface LS1, a second face portion located on a portion of the first main surface TS1, a third face portion located on a portion of the second main surface TS2, a fourth face portion located on a portion of the first side surface WS1, and a fifth face portion located on a portion of the second side surface WS2, similarly to the first external electrode 40A described above. It should be noted that openings corresponding to the above-described openings H are formed on the fourth and fifth faces of the first base electrode layer 50A. It should be noted that, in this modification, the first base electrode layer 50A is connected to the first internal electrode layer 31.

[0196] The first Ni plating layer 62A is arranged to cover the first base electrode layer 50A. The first Sn plating layer 63A is arranged to cover the first Ni plating layer 62A.

[0197] In this modification, the second base electrode layer 50B has, for example, a sixth face portion located on the second end surface LS2, a seventh face portion located on a portion of the first main surface TS1, an eighth face portion located on a portion of the second main surface TS2, a ninth face portion located on a portion of the first side surface WS1, and a tenth face portion located on a portion of the second side surface WS2, similarly to the second external electrode 40B described above. It should be noted that the ninth face portion and the tenth face portion of the second base electrode layer 50B have openings corresponding to the opening H described above. It should be noted that, in this modification, the second base electrode layer 50B is connected to the second internal electrode layer 32.

[0198] The second Ni plating layer 62B is arranged to cover the second base electrode layer 50B. The second Sn plating layer 63B is arranged to cover the second Ni plating layer 62B.

[0199] The first sintered layer 52A constituting the first base electrode layer 50A and the second sintered layer 52B constituting the second base electrode layer 50B may be obtained by, for example, applying a conductive paste containing glass and metal to the laminate and sintering the laminate. It should be noted that, when the laminated small pieces before sintering and the conductive paste applied to the laminated small pieces are sintered at the same time, the sintered layer is preferably formed by sintering a conductive paste to which a ceramic material is added instead of a glass component. In this case, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20.

[0200] When the base electrode layer is formed by a sintered layer, the first plating layer 60A and the second plating layer 60B preferably have a double-layer structure in which a Sn plating layer is formed on a Ni plating layer. In this case, the Ni plating layer prevents the base electrode layer from being corroded by the solder when mounting the multilayer ceramic capacitor 1. In addition, the Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1. As a result, the mounting of the multilayer ceramic capacitor 1 becomes easy.

[0201] It should be noted that the first plating layer 60A and the second plating layer 60B are not limited to a two-layer structure, and may be formed of a three-layer structure including Cu plating as in the above-mentioned embodiment, or may have other layer structures.

[0202] The thickness of each plating layer is preferably 2 μm or more and 15 μm or less. That is, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is preferably 2 μm or more and 15 μm or less. More specifically, the average thickness of each of the first Ni plating layer 62A, the first Sn plating layer 63A, the second Ni plating layer 62B, and the second Sn plating layer 63B is more preferably 2 μm or more and 4 μm or less.

[0203] Next, a method for manufacturing the multilayer ceramic capacitor 1 according to the present embodiment will be described.

[0204] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The conductive paste for the dielectric sheet and the internal electrode contains a binder and a solvent. The binder and the solvent may also be known materials. The paste containing the conductive material is, for example, a paste obtained by adding an organic binder and an organic solvent to metal powder.

[0205] For example, a conductive paste for the internal electrode layer 30 is printed on the dielectric sheet using a printing plate designed by screen printing or gravure printing so as to form the shape of the internal electrode layer 30 of the present embodiment. Thus, a dielectric sheet having a pattern of the first internal electrode layer 31 and a dielectric sheet having a pattern of the second internal electrode layer 32 are prepared. Here, the size of the opening H can be adjusted by controlling the interval between the first lead portion 31B and the second lead portion 31C and the third lead portion 31D, and the interval between the fourth lead portion 32B and the fifth lead portion 32C and the sixth lead portion 32D.

[0206] By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed, a portion of the first main surface side outer layer portion 12 on the first main surface TS1 side is formed. By alternately stacking dielectric sheets on which the pattern of the first internal electrode layer 31 is printed and dielectric sheets on which the pattern of the second internal electrode layer 32 is printed, a portion of the inner layer portion 11 is formed. By stacking a predetermined number of dielectric sheets on which the pattern of the internal electrode layer is not printed on the portion that is to become the inner layer portion 11, a portion of the second main surface side outer layer portion 13 on the second main surface TS2 side is formed. In this way, a laminated sheet is produced.

[0207] The stacked sheets are pressed in the stacking direction by a mechanism such as a fluid static press, thereby producing a stacked block.

[0208] The stacked blocks are cut into predetermined sizes to produce stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0209] The stacked small pieces are fired to produce the stacked body 10. The firing temperature is determined by the materials of the dielectric layer 20 and the internal electrode layer 30, but is preferably 900°C or higher and 1400°C or lower.

[0210] In this embodiment, the base electrode layer is formed of a thin film layer. When the base electrode layer is formed of a thin film layer, the thin film layer is formed on a portion of the laminate 10 where an external electrode is to be formed by masking or the like. The thin film layer is formed by a thin film forming method such as sputtering or evaporation. In this embodiment, a sputtering electrode as a thin film layer is formed by sputtering.

[0211] Figure 12 to Figure 14 1 is a diagram showing a state in the middle of the manufacturing process of the multilayer ceramic capacitor according to the present embodiment, and is a diagram showing a state after the thin film layer is arranged on the laminate 10 and before the plating layer is arranged. Fig.12 1 is a diagram showing a state in which a first thin film layer 51A and a second thin film layer 51B as thin film layers are arranged in a laminate 10, and is similar to Figure 6 The LT section corresponds to the figure. Fig.13is a diagram showing a state in which a first thin film layer 51A as a thin film layer is disposed in the laminate 10, and is similar to Figure 7 The WT cross section corresponds to Fig. Fig.14 The diagram shows a state where the first thin film layer 51A and the second thin film layer 51B are arranged in the laminate 10, and Fig. 9 The corresponding figure is a view of the surface of the first side surface WS1 of the stacked body 10 .

[0212] The first thin film layer 51A formed by the sputtering electrode is arranged on a portion of the first end surface LS1 side of the first main surface TS1 and a portion of the first end surface LS1 side of the second main surface TS2. The second thin film layer 51B formed by the sputtering electrode is arranged on a portion of the second end surface LS2 side of the first main surface TS1 and a portion of the second end surface LS2 side of the second main surface TS2.

[0213] In the present embodiment, the thin film layer formed by the sputtering electrode is arranged on a portion of the first main surface TS1 and a portion of the second main surface TS2, and is arranged continuously and slightly around a portion of the first side surface WS1 and a portion of the second side surface WS2 from a portion of the first main surface TS1 and a portion of the second main surface TS2. Thus, the distance between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode film exposed on the first side surface WS1 and the second side surface WS2 can be controlled. Therefore, even on the surface of the stacked body 10 between the thin film layer arranged on a portion of the first side surface WS1 and a portion of the second side surface WS2 and the internal electrode layer exposed on the first side surface WS1 and the second side surface WS2, a plating layer can be deposited.

[0214] Then, a plating layer is formed on the surface of the base electrode layer including the thin film layer and the laminate. In this embodiment, a three-layer plating layer of a Cu plating layer, a Ni plating layer, and a Sn plating layer is formed as the plating layer.

[0215] When forming the plated layer, it is formed by electrolytic plating. As the plating method, barrel plating is preferably used.

[0216] Here, when the thin film layer is formed to also wrap around a portion on the first side WS1 and a portion on the second side WS2, it is possible to control the distance between the thin film layer and the internal electrode layer exposed on the first side WS1 and the second side WS2 of the stacked body 10. Therefore, even on the surface of the stacked body 10 between the thin film layer disposed on a portion on the first side WS1 and a portion on the second side WS2 and the internal electrode layer exposed on the first side WS1 and the second side WS2, it is easy to deposit a plating layer.

[0217] In addition, the plating layer is configured to cover the exposed portion of the internal electrode layer in the first side surface WS1 and the second side surface WS2 of the stack 10. At this time, the gap between the thin film layer and the internal electrode layer exposed on the surface of the stack 10, and the gaps between the multiple internal electrode layers exposed on the surface of the stack 10 are formed narrower, so the plating layer is also deposited in the region of these gaps. Thus, the plating layer is formed in the portion other than the opening H in this embodiment.

[0218] It should be noted that, for example, when it is difficult to control the formation of the plating layer when the area of ​​the opening H is small, the plating layer may be formed by performing masking at the location where the opening is provided. This makes it easier to form the opening H.

[0219] It should be noted that, in the case where the base electrode layer is formed by the sintered layer, the conductive paste that becomes the first base electrode layer is applied to the first face portion located on the first end face LS1 of the stacked body 10, the second face portion located on a portion of the first main surface TS1, the third face portion located on a portion of the second main surface TS2, the fourth face portion located on a portion of the first side surface WS1, and the fifth face portion located on a portion of the second side surface WS2. In addition, the conductive paste that becomes the second base electrode layer is applied to the sixth face portion located on the second end face LS2 of the stacked body 10, the seventh face portion located on a portion of the first main surface TS1, the eighth face portion located on a portion of the second main surface TS2, the ninth face portion located on a portion of the first side surface WS1, and the tenth face portion located on a portion of the second side surface WS2.

[0220] It should be noted that masking is performed in advance on the portion where the base electrode layer is not to be formed, such as the portion to be the opening H. After masking, a conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping or screen printing. Thereafter, a sintering process is performed to form the base electrode layer. The sintering process temperature at this time is preferably 700° C. or higher and 900° C. or lower.

[0221] It should be noted that, when the stacked small pieces before firing and the conductive paste applied to the stacked small pieces are fired at the same time, the sintered layer is preferably formed by sintering the conductive paste to which a ceramic material is added instead of the glass component. At this time, as the added ceramic material, it is particularly preferred to use a ceramic material of the same type as the dielectric layer 20. In this case, the conductive paste is applied to the stacked small pieces before firing, and the stacked small pieces and the conductive paste applied to the stacked small pieces are sintered at the same time to form a stacked body 10 in which the sintered layer is formed.

[0222] After that, a plating layer is formed on the surface of the base electrode layer including the sintered layer and the laminate 10. When the base electrode layer is formed by the sintered layer, a double-layer plating layer of, for example, a Ni plating layer and a Sn plating layer is formed as the plating layer. When forming the plating layer, it is formed by an electrolytic plating method. As a plating method, barrel plating is preferably used.

[0223] It should be noted that, for example, when it is difficult to control the formation of the plating layer when the area of ​​the opening H is small, the plating layer may be formed by performing masking at the location where the opening is provided. Thus, the opening H can be formed more easily.

[0224] Through such manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0225] It should be noted that the structure of the external electrode 40 is not limited to the above-mentioned structure. Hereinafter, a modified example of the configuration position of the external electrode 40 of the multilayer ceramic capacitor 1 of this embodiment will be described. It should be noted that in the following description, the same reference numerals are given to the same structures as those in the above-mentioned embodiment, and detailed descriptions are omitted. Fig.15 is a cross-sectional view showing a modified example of the arrangement position of the external electrode 40 of the multilayer ceramic capacitor 1 according to the present embodiment, and is similar to Figure 1 The corresponding figure.

[0226] In this modification, the arrangement position of the external electrode 40 is different from that of the above-described embodiment. In this modification, the first external electrode 40A and the second external electrode 40B are arranged only on one of the first main surface TS1 and the second main surface TS2.

[0227] For example, the first external electrode 40A of this modification example has a first face 40A1 located on the first end surface LS1, a third face 40A3 located on a portion of the second main surface TS2, a fourth face 40A4 located on a portion of the first side surface WS1, and a fifth face 40A5 located on a portion of the second side surface WS2. That is, the first external electrode 40A of this modification example is not formed on the first main surface TS1.

[0228] For example, the second external electrode 40B of this modification example has a sixth face 40B1 located on the second end face LS2, an eighth face 40B3 located on a portion of the second main face TS2, a ninth face 40B4 located on a portion of the first side face WS1, and a tenth face 40B5 located on a portion of the second side face WS2. That is, the second external electrode 40B of this modification example is not formed on the first main face TS1.

[0229] In addition, similar to the above-described embodiment, the fourth surface portion 40A4 and the fifth surface portion 40A5 of the first external electrode 40A and the ninth surface portion 40B4 and the tenth surface portion 40B5 of the second external electrode 40B in this modification have openings H that expose the surface of the stacked body 10 .

[0230] With such a structure, it is also possible to suppress the deterioration of the self-alignment effect and perform stable mounting. In addition, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the dimension of the height direction T of the multilayer ceramic capacitor 1 can be reduced, and the multilayer ceramic capacitor 1 can be further thinned. In addition, by not configuring the first external electrode 40A and the second external electrode 40B on either the first main surface TS1 or the second main surface TS2, the height dimension of the multilayer body 10 can be ensured according to the thickness of the external electrode 40. Therefore, the volume of the effective layer portion of the multilayer body 10 can be increased, and the high capacitance of the multilayer ceramic capacitor 1 can be achieved.

[0231] According to the multilayer ceramic capacitor 1 of the present embodiment, the following effects are achieved.

[0232] (1) A multilayer ceramic capacitor 1 according to the present embodiment comprises: a multilayer body 10 having a plurality of laminated dielectric layers 20 and a plurality of internal electrode layers 30 laminated on the dielectric layers 20, and having a first main surface TS1 and a second main surface TS2 opposite to each other in a height direction, a first end surface LS1 and a second end surface LS2 opposite to each other in a length direction perpendicular to the height direction, and a first side surface WS1 and a second side surface WS2 opposite to each other in a width direction perpendicular to the height direction and the length direction; a first external electrode 40A having at least any one of a first face portion 40A1 located on the first end surface LS1, a second face portion 40A2 located partially on the first main surface TS1, and a third face portion 40A3 located partially on the second main surface TS2, a fourth face portion 40A4 located partially on the first side surface WS1, and a fifth face portion 40A5 located partially on the second side surface WS2; and a second The external electrode 40B includes at least one of a sixth face portion 40B1 located on the second end surface LS2, a seventh face portion 40B2 located on a portion of the first main surface TS1, and an eighth face portion 40B3 located on a portion of the second main surface TS2, a ninth face portion 40B4 located on a portion of the first side surface WS1, and a tenth face portion 40B5 located on a portion of the second side surface WS2, wherein when the length in the longitudinal direction connecting the first end surface LS1 and the second end surface LS2 of the stacked body 10 is set to l, the length in the width direction connecting the first side surface WS1 and the second side surface WS2 is set to w, and the length in the height direction connecting the first main surface TS1 and the second main surface TS2 is set to t, the dimensions are in a relationship of w>l>t, and the fourth face portion 40A4 and the fifth face portion 40A5, and the ninth face portion 40B4 and the tenth face portion 40B5 have an opening H that exposes the surface of the stacked body 10. Thus, an LW inversion type stacked ceramic capacitor that can suppress the deterioration of the self-alignment effect and can be stably mounted can be provided.

[0233] (2) The opening H of the multilayer ceramic capacitor 1 of the present embodiment is disposed at the center of the fourth and fifth surface portions 40A4 and 40A5 and the ninth and tenth surface portions 40B4 and 40B5 in the height direction. Thus, the solder surrounds the opening H and appropriately wets and swells.

[0234] (3) The opening H formed in the fourth face portion 40A4 and the fifth face portion 40A5 of the multilayer ceramic capacitor 1 of the present embodiment is arranged to be offset from the center portion in the longitudinal direction of the fourth face portion 40A4 and the fifth face portion 40A5 to the first end face LS1 side, and the opening H formed in the ninth face portion 40B4 and the tenth face portion 40B5 is arranged to be offset from the center portion in the longitudinal direction of the ninth face portion 40B4 and the tenth face portion 40B5 to the second end face LS2 side. Thus, the solder wetting bulge area can be appropriately secured on both sides of the opening H.

[0235] (4) The area of ​​the opening H of the multilayer ceramic capacitor 1 of the present embodiment is 3% or more and 20% or less of the area of ​​each of the fourth face portion 40A4 and the fifth face portion 40A5 and the ninth face portion 40B4 and the tenth face portion 40B5 where the opening H is arranged. This can produce a self-alignment effect, and the effect of suppressing short-circuit failure caused by tilting or rotating the multilayer ceramic capacitor 1 is more significant.

[0236] (5) The length t in the height direction of the first main surface TS1 and the second main surface TS2 of the connected laminate 10 of the multilayer ceramic capacitor 1 of the present embodiment is 150 μm or less. In such a thin multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0237] (6) The length t in the height direction of the first main surface TS1 and the second main surface TS2 of the connected laminate 10 of the multilayer ceramic capacitor 1 of the present embodiment is 100 μm or less. In such a thin multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0238] (7) The length t in the height direction of the first main surface TS1 and the second main surface TS2 of the connected laminate 10 of the multilayer ceramic capacitor 1 of the present embodiment is 50 μm or less. In such a thin multilayer ceramic capacitor, the effects of the present embodiment can be appropriately obtained.

[0239] (8) The internal electrode layer 30 of the multilayer ceramic capacitor 1 of the present embodiment includes a first internal electrode layer 31 and a second internal electrode layer 32, wherein the first internal electrode layer 31 includes: a first opposing electrode portion 31A located inside the multilayer body 10; a first lead portion 31B connected to the first opposing electrode portion 31A and exposed at the first end surface LS1, a portion of the first side surface WS1, and a portion of the second side surface WS2; a second lead portion 31C connected to the first opposing electrode portion 31A at a distance from the portion of the first lead portion 31B led to the first side surface WS1 and exposed at a portion of the first side surface WS1; and a third lead portion 31D connected to the first opposing electrode portion 31A at a distance from the portion of the first lead portion 31B led to the second side surface WS2. The second internal electrode layer 32 is connected to the second facing electrode portion 31A and is exposed at a portion of the second side surface WS2, and includes: a second facing electrode portion 32A located inside the stack 10; a fourth lead portion 32B connected to the second facing electrode portion 32A and exposed at the second end surface LS2, a portion of the first side surface WS1, and a portion of the second side surface WS2; a fifth lead portion 32C connected to the second facing electrode portion 32A at a distance from the portion of the fourth lead portion 32B led to the first side surface WS1 and exposed at a portion of the first side surface WS1; and a sixth lead portion 32D connected to the second facing electrode portion 32A at a distance from the portion of the fourth lead portion 32B led to the second side surface WS2 and exposed at a portion of the second side surface WS2. Thus, the opening H that exposes the surface of the stack 10 can be easily formed in the fourth face portion 40A4 and the fifth face portion 40A5 and the ninth face portion 40B4 and the tenth face portion 40B5. In addition, the distance between the lead-out portion of the first internal electrode layer 31 and the lead-out portion of the second internal electrode layer 32 can be shortened, so the path through which the current flows can be shortened. Therefore, ESL can be reduced.

[0240] (9) In the multilayer ceramic capacitor 1 of the present embodiment, the first lead portion 31B, the second lead portion 31C, and the third lead portion 31D are all connected to the first external electrode 40A, and the fourth lead portion 32B, the fifth lead portion 32C, and the sixth lead portion 32D are all connected to the second external electrode. Thus, the opening H that exposes the surface of the multilayer body 10 can be formed in the fourth surface portion 40A4 and the fifth surface portion 40A5 and the ninth surface portion 40B4 and the tenth surface portion 40B5, and the ESL can be reduced.

[0241] (10) The first external electrode 40A of the multilayer ceramic capacitor 1 of the present embodiment includes a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A, and the second external electrode 40B includes a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B, and the first base electrode layer 50A and the second base electrode layer 50B are sputtered electrodes. Thus, the thickness of the external electrodes can be formed thin, and the thickness of the multilayer body 10 can be easily ensured, so that the capacitance can be ensured and the strength of the multilayer body 10 can be ensured.

[0242] <Experimental example>

[0243] As samples of the experimental example, a multilayer ceramic capacitor was produced, and evaluation of mounting properties, capacitance, and thickness of the base electrode layer was performed.

[0244] First, as a sample of the embodiment, according to the above-mentioned manufacturing method, a Figure 1 to Figure 10B A multilayer ceramic capacitor 1 having the following specifications is shown. In addition, as a sample of Comparative Example 1, Fig.16A The multilayer ceramic capacitor 101 shown in FIG. 1 does not have an opening H in the external electrodes 140 (the first external electrode 140A and the second external electrode 140B). Fig.17A The illustrated multilayer ceramic capacitor 201 has no opening H in the external electrodes 240 (first external electrode 240A and second external electrode 240B) but has a recess R recessed from the edge of the external electrode toward the end surface of the stacked body 10 .

[0245] Fig.16A is a perspective view of the appearance of a multilayer ceramic capacitor 101 of Comparative Example 1. Figure 1 The corresponding figure. Fig. 16B is a diagram showing the first internal electrode layer 131 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Fig. 8A The corresponding figure. Fig. 16C is a diagram showing the second internal electrode layer 132 of the multilayer ceramic capacitor 101 of Comparative Example 1, and is similar to Figure 8B The corresponding figure. Fig.17A is a perspective view of the appearance of a multilayer ceramic capacitor 201 of Comparative Example 2. Figure 1 The corresponding figure. Fig. 17B is a diagram showing the first internal electrode layer 231 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Fig. 8A The corresponding figure. Fig. 17C is a diagram showing the second internal electrode layer 232 of the multilayer ceramic capacitor 201 of Comparative Example 2, and is similar to Figure 8B The corresponding figure. It should be noted that Fig. 16B , Fig. 16C , Fig. 17B , Fig. 17C The external electrodes are omitted.

[0246] (Structure of Embodiment)

[0247] Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0248] Ceramic material of dielectric layer: BaTiO3

[0249] Capacitance: 0.47μF

[0250] Rated voltage: 4V

[0251] Internal electrode material: Ni

[0252] Pattern of internal electrode layer: Fig. 8A , Figure 8B The pattern shown

[0253] ·Construction of external electrodes:

[0254] Substrate electrode layer: thin film layer (sputtered electrode)

[0255] Material of base electrode layer: Double-layer structure of NiCr layer and NiCu layer

[0256] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0257] Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating

[0258] Cu plating thickness: 5.5μm

[0259] Ni plating thickness: 2.5μm

[0260] Sn plating thickness: 3.2μm

[0261] The area ratio of the opening H where the laminated body of the fourth and fifth surfaces and the ninth and tenth surfaces is exposed: See Table 2

[0262] (Structure of Comparative Example 1)

[0263] Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0264] Ceramic material of dielectric layer: BaTiO3

[0265] Capacitance: 0.36μF

[0266] Rated voltage: 4V

[0267] Internal electrode material: Ni

[0268] Pattern of internal electrode layer: Fig. 16B , Fig. 16C The pattern shown

[0269] ·Construction of external electrodes:

[0270] Base electrode layer: A sintered layer obtained by applying a conductive paste and sintering it

[0271] Material of base electrode layer: Ni

[0272] Thickness of the underlying electrode layer: end surface thickness 10 μm, side surface thickness 5 μm, main surface thickness 5 μm (the thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2, respectively)

[0273] Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating

[0274] Cu plating thickness: 5.5μm

[0275] Ni plating thickness: 2.5μm

[0276] Sn plating thickness: 3.2μm

[0277] (Structure of Comparative Example 2)

[0278] Dimensions of multilayer ceramic capacitors: L×W×T=0.520mm×1.000mm×0.100mm

[0279] Ceramic material of dielectric layer: BaTiO3

[0280] Capacitance: 0.47μF

[0281] Rated voltage: 4V

[0282] Internal electrode material: Ni

[0283] Pattern of internal electrode layer: Fig. 17B , Fig. 17C The pattern shown

[0284] ·Construction of external electrodes:

[0285] Substrate electrode layer: thin film layer (sputtered electrode)

[0286] Material of base electrode layer: double layer of NiCr layer and NiCu layer

[0287] Thickness of the underlying electrode layer: main surface thickness 0.2 μm (thickness of the underlying electrode layer disposed on the first main surface TS1 and the second main surface TS2 )

[0288] Plating layer: Three-layer structure of Cu plating, Ni plating, and Sn plating

[0289] Cu plating thickness: 5.5μm

[0290] Ni plating thickness: 2.5μm

[0291] Sn plating thickness: 3.2μm

[0292] Next, using the produced samples, evaluation of mounting properties, and evaluation of capacitance and thickness of the base electrode layer were performed.

[0293] (Installation evaluation 1)

[0294] First, the mountability was evaluated using the samples of the embodiment in which the area ratio of the opening H was 13% and the samples of Comparative Examples 1 and 2. The evaluation was performed using 100 samples respectively. Table 1 shows the results of the mountability evaluation.

[0295] [Table 1]

[0296]

[0297] Eight samples suffered from rotation failure in Comparative Example 1. By increasing the amount of solder for evaluation, it is presumed that the rotation failure occurred because of a difference in the way the solder wetted and bulged onto the first external electrode and the second external electrode.

[0298] In Comparative Example 2, 15 samples were produced that had poor rotation. Two of them were installed so that the rotation amount was large and one external electrode crossed a pad with different polarity, and a short circuit failure occurred. In the samples of Comparative Example 2, it is believed that due to the deviation in the formation position and thickness of the base electrode layer and the plating layer provided on the base electrode layer, the area and shape of the external electrode covering the ridgeline of the first side and second side of the stacked body are deviated, and the wetting mode of the solder relative to the external electrode of the first side and second side is prone to change, sometimes resulting in a large difference in the amount of solder wetting bulge. As a result, it is speculated that the difference in the way the solder applies tensile stress to the laminated ceramic capacitor causes poor rotation.

[0299] (Installation evaluation 2)

[0300] Next, samples of the examples in which the area ratio of the opening H was changed as follows were prepared, and the mountability was evaluated. Evaluation was performed using 100 samples respectively. Table 2 shows the results of the mountability evaluation.

[0301] [Table 2]

[0302]

[0303] In the samples of the examples, it was confirmed that good results were obtained, and in particular, it was confirmed that the area ratio of the opening H was preferably 1% or more and 50% or less, and more preferably 3% or more and 20% or less.

[0304] (Evaluation of capacitance and thickness of base electrode layer)

[0305] Next, the capacitance and the thickness of the base electrode layer were evaluated. Table 3 shows the evaluation results.

[0306] [Table 3]

[0307]

[0308] As shown in Table 3, in Comparative Example 1, the thickness of the external electrodes is thicker than in Example and Comparative Example 2, so it is difficult to ensure the size of the laminated body. When the laminated ceramic capacitor is made to fall within the specified size, the capacitance becomes small.

[0309] The evaluation method in this experimental example is shown below.

[0310] (Evaluation method for installability)

[0311] FIG. 18A to FIG. 18D This is a diagram for explaining the evaluation method of installability. Fig.18A Solder (solder composition Sn-3.0Ag-0.5Cu) is printed on two pads 310A and 310B on the glass epoxy substrate 300 shown in the figure. The amount of solder at this time is set to 1.5 times the amount of the normal test, making the conditions more stringent than the normal test. Specifically, a solder with a thickness of 150um is printed on each pad. It should be noted that Fig.18A As shown, the length of the pad in the width direction is 1.0 mm, the length of the pad in the length direction is 0.3 mm, and the distance between the two pads is 0.2 mm.

[0312] Next, the multilayer ceramic capacitor is placed on the pads coated with solder. Fig.18B As shown in FIG. 1 , a reference line is set perpendicular to the width direction of the pad at the center of the width direction of the pad, and the multilayer ceramic capacitor is placed so that the center of the width direction W of the multilayer ceramic capacitor is located at a position offset by 0.1 mm from the reference line in the width direction of the pad. It should be noted that at this time, the multilayer ceramic capacitor is placed Fig. 18CThe angle θ formed between the shown pad and the multilayer ceramic capacitor, that is, the acute angle θ formed between any one of the opposing inner sides of the two pads and the surface on the first end face LS1 side or the second end face LS2 side of the external electrode of the multilayer ceramic capacitor, is within 5°.

[0313] After that, the external electrodes of the multilayer ceramic capacitor are soldered to the pads by reflow soldering, and the multilayer ceramic capacitor is mounted on the substrate. After mounting, the mounting state of the multilayer ceramic capacitor is observed, and the case where the angle θ between the pads and the multilayer ceramic capacitor is tilted by more than 5° is considered as rotation failure. Fig.18D As shown, a case where the multilayer ceramic capacitor is mounted with a large rotation so that the first external electrode or the second external electrode straddles two pads is regarded as a short-circuit failure.

[0314] (Calculation method of area ratio of opening H)

[0315] The area ratio of the opening H is measured using an optical microscope. First, the field of view is set to a magnification at which the first external electrode 40A located on the first side surface WS1 of the multilayer ceramic capacitor 1 enters the field of view of the microscope. Next, the contour of the opening H is identified, and the dimension d1 of the opening H in the length direction L and the dimension d2 in the height direction T are measured (refer to Figure 2 ). Then, the area A1 of the opening H is calculated by the calculation formula A1=d1×d2. Next, the contour of the first external electrode 40A is identified, and the dimension D1 in the length direction L and the dimension D2 in the height direction T of the fourth surface 40A4 are measured (refer to Figure 2 ). Then, the area A2 of the fourth face 40A4 is calculated by the calculation formula A2=D1×D2. Then, the area ratio of the opening H located on the fourth face 40A4 relative to the area of ​​the fourth face 40A4 is calculated by the calculation formula A1÷A2. Similarly, the area ratios of the openings H located on the fifth face 40A5, the ninth face 40B4, and the tenth face 40B5 are also calculated. Then, the average value of the area ratios of the four openings H, that is, the average value of the area ratios of the openings H located on the fourth face 40A4, the fifth face 40A5, the ninth face 40B4, and the tenth face 40B5 is calculated as the area ratio of the openings H in the multilayer ceramic capacitor 1.

[0316] (Method for measuring capacitance)

[0317] The capacitance of the multilayer ceramic capacitor was measured using an LCR meter (automatic balancing bridge method) at a measurement voltage of 0.5 Vrms and a measurement frequency of 1 kHz.

[0318] As can be seen from the above results, according to the multilayer ceramic capacitor 1 of the present embodiment, even if there is a deviation in the amount of solder, for example, it is possible to appropriately suppress the wetting and swelling of the solder with respect to the first side surface WS1 and the second side surface WS2 of the multilayer body 10, and thus it is possible to suppress the stress applied in the rotation direction of the multilayer ceramic capacitor 1. Therefore, the self-alignment effect is improved, and the mounting property of the multilayer ceramic capacitor 1 is stabilized. As a result, short-circuit failures and the like can be prevented.

[0319] The present invention is not limited to the configuration of the above-mentioned embodiment, and can be applied with appropriate changes within the scope of the present invention. It should be noted that a configuration obtained by combining two or more of the preferred configurations described in the above-mentioned embodiment also belongs to the present invention.

Claims

1. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a height direction, a first end surface and a second end surface opposite to each other in a length direction orthogonal to the height direction, and a first side surface and a second side surface opposite to each other in a width direction orthogonal to the height direction and the length direction; a first external electrode having at least any one of a first face portion located on the first end surface, a second face portion located on a portion of the first main surface, and a third face portion located on a portion of the second main surface, a fourth face portion located on a portion of the first side surface, and a fifth face portion located on a portion of the second side surface; and a second external electrode having at least any one of a sixth face portion located on the second end surface, a seventh face portion located on a portion of the first main surface, and an eighth face portion located on a portion of the second main surface, a ninth face portion located on a portion of the first side surface, and a tenth face portion located on a portion of the second side surface, in, When the length in the longitudinal direction connecting the first end face and the second end face of the stack is set to l, the length in the width direction connecting the first side face and the second side face is set to w, and the length in the height direction connecting the first main face and the second main face is set to t, the dimensions are in a relationship of w>l>t. The fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion have openings that expose the surface of the laminate, and the openings are surrounded by a material constituting an external electrode.

2. The multilayer ceramic capacitor according to claim 1, wherein The opening is arranged at a center portion of the fourth surface portion, the fifth surface portion, the ninth surface portion, and the tenth surface portion in the height direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The openings formed in the fourth surface and the fifth surface are arranged to be closer to the first end surface than the central portions in the longitudinal direction of the fourth surface and the fifth surface. The openings formed in the ninth surface portion and the tenth surface portion are arranged to be offset toward the second end surface side relative to the center portions in the longitudinal direction of the ninth surface portion and the tenth surface portion.

4. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The area of ​​the opening is greater than or equal to 3% and less than or equal to 20% of the area of ​​each of the fourth and fifth face portions, and the ninth and tenth face portions on which the opening is arranged.

5. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length in the height direction connecting the first main surface and the second main surface of the stacked body is 150 μm or less.

6. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length in the height direction connecting the first main surface and the second main surface of the stacked body is 100 μm or less.

7. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The length in the height direction connecting the first main surface and the second main surface of the stacked body is 50 μm or less.

8. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The internal electrode layer includes a first internal electrode layer and a second internal electrode layer, The first internal electrode layer has: a first counter electrode portion located inside the stack; a first lead portion connected to the first opposing electrode portion and exposed at the first end surface, a portion of the first side surface, and a portion of the second side surface; a second lead portion connected to the first counter electrode portion at a distance from a portion of the first lead portion led out to the first side surface and exposed at a portion of the first side surface; as well as a third lead portion connected to the first counter electrode portion at a distance from a portion of the first lead portion led out to the second side surface and exposed at a portion of the second side surface; The second internal electrode layer has: a second counter electrode portion located inside the stack; a fourth lead portion connected to the second opposing electrode portion and exposed at the second end surface, a portion of the first side surface, and a portion of the second side surface; a fifth lead portion connected to the second opposing electrode portion at a distance from a portion of the fourth lead portion led out to the first side surface and exposed at a portion of the first side surface; as well as The sixth lead portion is connected to the second counter electrode portion at a distance from the portion of the fourth lead portion led out toward the second side surface and is exposed at a portion of the second side surface.

9. The multilayer ceramic capacitor according to claim 8, wherein: The first lead portion, the second lead portion, and the third lead portion are all connected to the first external electrode. The fourth lead portion, the fifth lead portion, and the sixth lead portion are all connected to the second external electrode.

10. The multilayer ceramic capacitor according to claim 1 or 2, wherein: The first external electrode includes a first base electrode layer and a first plating layer disposed on the first base electrode layer. The second external electrode includes a second base electrode layer and a second plating layer disposed on the second base electrode layer. The first base electrode layer and the second base electrode layer are sputtered electrodes.

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