Silicon-based gallium arsenide epitaxial structure, laser and preparation method

Abstract

Embodiments of the present application relate to a preparation method of a silicon-based gallium arsenide epitaxial structure, a silicon-based gallium arsenide epitaxial structure, a preparation method of a laser, and a laser, wherein the method comprises: providing a silicon substrate; epitaxially growing a nucleation layer on the silicon substrate, the material of the nucleation layer comprising a first semiconductor material; epitaxially growing a first transition layer on the nucleation layer, the material of the first transition layer comprising a second semiconductor material; the first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between silicon and the second semiconductor material, and the lattice constant of the second semiconductor material is between the first semiconductor material and gallium arsenide; epitaxially growing a second transition layer on the first transition layer, the material of the second transition layer comprising a third semiconductor material; epitaxially growing a gallium arsenide layer on the second transition layer; and the band gap of the third semiconductor material is between the second semiconductor material and gallium arsenide.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a silicon-based gallium arsenide epitaxial structure, a silicon-based gallium arsenide epitaxial structure, a method for preparing a laser, and a laser. Background Art

[0002] With the rapid development of optoelectronics and information technology, the high carrier mobility and high saturation rate properties of III-V compounds such as gallium arsenide (GaAs) have attracted widespread attention. However, compared with silicon substrates, GaAs substrates are very expensive. Therefore, growing GaAs on silicon substrates to fabricate silicon-based integrated III-V semiconductor devices has great application prospects.

[0003] Currently, the difficulty in epitaxially growing GaAs on silicon substrates lies in the large lattice mismatch and significant difference in thermal expansion coefficient between silicon and GaAs materials. The stress generated by this mismatch is primarily released through threading dislocations. Therefore, when growing GaAs directly on a silicon substrate, a large number of threading dislocations are generated, severely impacting device performance and, in particular, significantly reducing device lifespan. To reduce threading dislocations, the industry has proposed a three-step growth method for growing GaAs epitaxial layers. This involves first growing a low-temperature GaAs nucleation layer on a silicon substrate, then growing a medium-temperature GaAs layer on the low-temperature GaAs nucleation layer, and finally growing a high-temperature GaAs layer on the medium-temperature GaAs layer. This method reduces the possibility of threading dislocations propagating to the active layer. However, the low-temperature GaAs nucleation layer, acting as a buffer layer, is difficult to reduce the dislocation density. The three-step growth method is very limited in its effectiveness in blocking threading dislocations, resulting in a high threading dislocation density exceeding 1E7 per square centimeter and difficulty in reducing it further.

[0004] How to effectively grow high-quality gallium arsenide materials epitaxially on silicon substrates remains an important challenge that needs to be overcome in this field. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a method for preparing a silicon-based gallium arsenide epitaxial structure, a method for preparing a silicon-based gallium arsenide epitaxial structure, a laser, and a laser to solve at least one problem existing in the background technology.

[0006] In a first aspect, an embodiment of the present application provides a method for preparing a silicon-based gallium arsenide epitaxial structure, the method comprising:

[0007] providing a silicon substrate;

[0008] epitaxially growing a nucleation layer on the silicon substrate, wherein the material of the nucleation layer includes a first semiconductor material;

[0009] epitaxially growing a first transition layer on the nucleation layer, wherein the material of the first transition layer includes a second semiconductor material;

[0010] The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, and the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide;

[0011] epitaxially growing a second transition layer on the first transition layer, wherein the material of the second transition layer includes a third semiconductor material;

[0012] epitaxially growing a gallium arsenide layer on the second transition layer;

[0013] The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide.

[0014] In combination with the first aspect of the present application, in an optional embodiment, the first semiconductor material includes gallium phosphide; the second semiconductor material includes indium gallium phosphide; and the third semiconductor material includes aluminum gallium indium arsenic phosphide.

[0015] In conjunction with the first aspect of the present application, in an optional embodiment, the epitaxial growth of the first transition layer on the nucleation layer includes:

[0016] During the epitaxial growth process, the content of the indium source is increased to epitaxially grow a first transition layer on the nucleation layer, wherein the indium component increases and the gallium component decreases in a direction away from the nucleation layer.

[0017] In conjunction with the first aspect of the present application, in an optional embodiment, after epitaxially growing a first transition layer on the nucleation layer and before epitaxially growing a second transition layer on the first transition layer, the method includes:

[0018] A third transition layer is epitaxially grown on the first transition layer; wherein the second transition layer is grown on the third transition layer, and the lattice constant of the material of the third transition layer is equal to the lattice constant of gallium arsenide.

[0019] In conjunction with the first aspect of the present application, in an optional embodiment, the step of epitaxially growing the second transition layer on the first transition layer includes:

[0020] As the epitaxial growth process proceeds, the amount of phosphorus source introduced is reduced and the amount of arsenic source introduced is increased to obtain the following second transition layer: in the direction away from the silicon substrate, the phosphorus content in the second transition layer decreases from 100% to 0 and the arsenic content increases from 0 to 100%.

[0021] In conjunction with the first aspect of the present application, in an optional embodiment, the epitaxially growing a gallium arsenide layer on the second transition layer includes:

[0022] epitaxially growing a first gallium arsenide layer on the second transition layer;

[0023] A superlattice layer is epitaxially generated on the first gallium arsenide layer. The superlattice layer includes aluminum arsenide layers and second gallium arsenide layers that are periodically and alternately arranged.

[0024] In combination with the first aspect of the present application, in an optional embodiment, the arrangement period of the aluminum arsenide layer and the second gallium arsenide layer is 9 to 11; the second gallium arsenide layer is arranged on a side of the superlattice layer away from the first gallium arsenide layer.

[0025] In combination with the first aspect of the present application, in an optional embodiment, the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is in the range of (1-3):1.

[0026] In a second aspect, an embodiment of the present application provides a silicon-based gallium arsenide epitaxial structure, comprising:

[0027] Silicon substrate;

[0028] a nucleation layer located on the silicon substrate, wherein the material of the nucleation layer comprises a first semiconductor material;

[0029] a first transition layer located on the nucleation layer, wherein the material of the first transition layer comprises a second semiconductor material;

[0030] The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, and the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide;

[0031] a second transition layer located on the first transition layer, wherein the material of the second transition layer includes a third semiconductor material;

[0032] a gallium arsenide layer located on the second transition layer;

[0033] The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide.

[0034] In conjunction with the second aspect of the present application, in an optional embodiment, the first semiconductor material includes gallium phosphide; the second semiconductor material includes indium gallium phosphide; and the third semiconductor material includes aluminum gallium indium arsenic phosphide.

[0035] In combination with the second aspect of the present application, in an optional embodiment, the indium component in the first transition layer increases in a direction away from the nucleation layer and the gallium component decreases in a direction away from the nucleation layer.

[0036] In conjunction with the second aspect of the present application, in an optional implementation manner, the method further includes:

[0037] The third transition layer is located between the first transition layer and the second transition layer. The lattice constant of the material of the third transition layer is equal to the lattice constant of gallium arsenide.

[0038] In combination with the second aspect of the present application, in an optional embodiment, along a direction away from the silicon substrate, the phosphorus content in the second transition layer decreases from 100% to 0 and the arsenic content increases from 0 to 100%.

[0039] In conjunction with the second aspect of the present application, in an optional embodiment, the gallium arsenide layer includes: a first gallium arsenide layer and a second gallium arsenide layer;

[0040] The first gallium arsenide layer is located on the second transition layer;

[0041] The second gallium arsenide layer and the aluminum arsenide layer are periodically and alternately arranged to form a superlattice layer, and the superlattice layer is located on the first gallium arsenide layer.

[0042] In combination with the second aspect of the present application, in an optional embodiment, the arrangement period of the aluminum arsenide layer and the second gallium arsenide layer is 9 to 11; the second gallium arsenide layer is arranged on a side of the superlattice layer away from the first gallium arsenide layer.

[0043] In conjunction with the second aspect of the present application, in an optional embodiment, the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is in the range of (1-3):1.

[0044] In a third aspect, an embodiment of the present application provides a method for preparing a laser, which includes the steps in the method for preparing a silicon-based gallium arsenide epitaxial structure as described in the first aspect above, or includes preparing a laser using the silicon-based gallium arsenide epitaxial structure described in the second aspect above.

[0045] In a fourth aspect, an embodiment of the present application provides a laser, comprising: the silicon-based gallium arsenide epitaxial structure described in the second aspect above; and a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer located on the silicon-based gallium arsenide epitaxial structure; wherein the first conductive semiconductor layer and the second conductive semiconductor layer have opposite conductivity types, and the materials of the first conductive semiconductor layer and the second conductive semiconductor layer include gallium arsenide-based semiconductor materials.

[0046] The methods for preparing a silicon-based gallium arsenide epitaxial structure, the silicon-based gallium arsenide epitaxial structure, the methods for preparing a laser, and the laser provided in the embodiments of the present application achieve a transition in lattice constant from silicon to gallium arsenide through a first gallium phosphide-based semiconductor material and a second gallium phosphide-based semiconductor material, thereby reducing stress, reducing threading dislocations, and improving crystal growth quality; the energy band difference problem between the gallium phosphide-based semiconductor material and the gallium arsenide material is further resolved by transitioning through a third semiconductor material, greatly reducing the problem of increased series resistance caused by the use of gallium phosphide-based semiconductor materials, and ultimately achieving the growth of high-quality gallium arsenide materials on a silicon substrate.

[0047] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0049] Figure 1 A schematic flow chart of a method for preparing a silicon-based gallium arsenide epitaxial structure provided in an embodiment of the present application;

[0050] Figures 2 to 7 is a schematic diagram of the cross-sectional structure of a silicon-based gallium arsenide epitaxial structure during the preparation process in a specific example;

[0051] Figure 8 is a schematic diagram of the cross-sectional structure of the first gallium arsenide layer and the superlattice layer in a specific example;

[0052] Figure 9 Schematic diagram of the cross-sectional structure of a laser in a specific example. DETAILED DESCRIPTION

[0053] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0054] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to the extent that they would obscure the understanding of the present application. In this document, the terms "couple" or "coupled" and "communicate" or "communicating" mean direct or indirect communication or coupling.

[0055] In the drawings, the size of layers, regions, elements, and the like, can be exaggerated for clarity. Like reference numerals can represent like elements throughout the several figures.

[0056] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section.

[0057] Spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items. The term "between" includes the endpoints; e.g., the term "between A and C" means A, C or any number between A and C. However, the term "between A and C, D and F" clearly indicates that A and D are on one side and C and F are on the other side, with D being closer to F than A is.

[0059] For a thorough understanding of the present application, reference will be made to the following detailed description taken in conjunction with the accompanying drawings, in which:

[0060] First, refer to Figure 1 Embodiments of the present application provide a method for preparing a silicon-based gallium arsenide epitaxial structure, which comprises the following steps:

[0061] Step 101, providing a silicon substrate;

[0062] Step 102, epitaxially growing a nucleation layer on the silicon substrate, the material of the nucleation layer comprising a first semiconductor material;

[0063] Step 103, epitaxially growing a first transition layer on the nucleation layer, the material of the first transition layer comprising a second semiconductor material;

[0064] The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, and the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide;

[0065] Step 104, epitaxially growing a second transition layer on the first transition layer, the material of the second transition layer comprising a third semiconductor material;

[0066] Step 105, epitaxially growing a gallium arsenide layer on the second transition layer;

[0067] The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide.

[0068] Compared with the prior art, the present application no longer uses a low-temperature gallium arsenide nucleation layer as a buffer layer, but uses a gallium phosphide-based first semiconductor material to make a nucleation layer, and further grows a gallium phosphide-based second semiconductor material to make a first transition layer, so as to realize the transition of the lattice constant from silicon to gallium arsenide through the gallium phosphide-based first semiconductor material and the second semiconductor material, reduce the stress size caused by lattice mismatch, improve the problem of threading dislocations, and improve the crystal growth quality; considering that although the gallium phosphide-based semiconductor material and the gallium arsenide material are lattice matched, there is a band difference between them, the present application further realizes the band gap transition through the third semiconductor material, greatly reduces the problem of increased series resistance value caused by the use of the gallium phosphide-based semiconductor material, and finally realizes the growth of high-quality gallium arsenide material on the silicon substrate.

[0069] In the following, the present application will be described in detail with reference to the specific examples shown in the drawings. Figures 2 to 7 The cross-sectional structure of the silicon-based gallium arsenide epitaxial structure in the preparation process will be further described in detail.

[0070] First, refer to Figure 2 Step 101, providing a silicon substrate 210.

[0071] The silicon substrate 210 may also be referred to as a silicon (Si) wafer, and the silicon substrate 210 will serve as a carrier for subsequent epitaxial growth. The silicon substrate 210 includes a top surface and a bottom surface opposite to each other; the top surface generally refers to the side on which the epitaxial layer is formed. Ignoring the flatness of the top and bottom surfaces, the direction perpendicular to the top and bottom surfaces is defined as the thickness direction of the silicon substrate 210. The epitaxial layers subsequently grown on the silicon substrate 210 are stacked in sequence along the thickness direction of the silicon substrate 210. The thickness direction of the silicon substrate 210 may also be referred to as the height direction of the device.

[0072] In actual preparation, before the epitaxial growth process is performed, the surface of the silicon substrate 210 can be treated. Specifically, the silicon substrate 210 can be placed in a thermostatic bath, set at a temperature of 50°C to 300°C, and cleaned under ultrasonic oscillation. During the cleaning process, a liquid can be circulated into the thermostatic bath. Specifically, a cleaning agent, such as an isopropyl alcohol (IPA) solution, can be first introduced for a certain period of time; then, deionized water can be introduced for a certain period of time.

[0073] Next, please refer to Figure 3 Step 102 is performed to epitaxially grow a nucleation layer 220 on a silicon substrate 210 , wherein the material of the nucleation layer 220 includes a first semiconductor material.

[0074] The first semiconductor material is a gallium phosphide-based semiconductor material, and the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material. Specifically, the first semiconductor material is, for example, gallium phosphide (GaP).

[0075] In actual production, GaP can be grown using a MOCVD (Metal Organic Chemical Vapor Deposition) process. The growth temperature is, for example, 600°C to 800°C, and the growth pressure is, for example, 50mbar to 600mbar. The growth thickness is approximately 5nm to 50nm.

[0076] The growth mode of the nucleation layer 220 is specifically a 3D mode. This 3D mode, also known as an island mode, generally features rapid vertical growth with discontinuous horizontal growth. This can be achieved by setting a relatively low growth temperature. For the 3D growth mode of the nucleation layer 220, the growth temperature is, for example, a relatively low temperature within the range of 600°C to 800°C.

[0077] To epitaxially grow high-quality GaAs materials on a silicon substrate, a 3D-mode followed by a 2D-mode growth method can be employed. In this embodiment, the nucleation layer 220 is first grown in a 3D mode. After the nucleation layer 220 is formed, the temperature is increased, allowing the subsequent epitaxial layer to be grown in a 2D mode. After switching to the 2D mode, the surface of the epitaxial layer gradually becomes smoother, and the problem of poor lattice matching between the materials at the growth interface is gradually reduced.

[0078] Next, please refer to Figure 4 Step 103 is executed to epitaxially grow a first transition layer 231 on the nucleation layer 220 , wherein the material of the first transition layer 231 includes a second semiconductor material.

[0079] The second semiconductor material is a gallium phosphide-based semiconductor material; the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide, thereby achieving a gradual transition in lattice constant from silicon to gallium arsenide. Specifically, the second semiconductor material is, for example, indium gallium phosphide (InGaP).

[0080] Since there is about 6% lattice mismatch between GaP and GaAs, InGaP can be used for further transition.

[0081] As an optional embodiment, epitaxially growing a first transition layer 231 on the nucleation layer 220 specifically includes: during the epitaxial growth process, increasing the content of the indium source to epitaxially grow a first transition layer 231 on the nucleation layer 220 in which the indium component increases and the gallium component decreases in a direction away from the nucleation layer 220.

[0082] The chemical formula of the second semiconductor material is In x1 Ga 1-x1 Taking P as an example, as the epitaxial growth process proceeds, x1 gradually increases and 1-x1 gradually decreases.

[0083] Considering In 0.5 Ga 0.5 The lattice constant of P is equal to that of GaAs, so x1 can be increased from 0 to 0.5 (or close to 0.5); accordingly, 1-x1 decreases from 1 to 0.5 (or close to 0.5). It is easy to understand that when x1 is equal to 0, In x1 Ga 1-x1 P is GaP, that is, the material of the first transition layer 231 on the side close to the nucleation layer 220 is basically the same as the material of the nucleation layer 220, and the lattice constant is basically equal; the lattice constant of the material of the first transition layer 231 on the side away from the nucleation layer 220, that is, the side closer to the subsequent growth of GaAs, is basically equal to the lattice constant of GaAs.

[0084] The first transition layer 231 gradually reduces the stress between GaP and InGaP, reduces threading dislocations, and reduces defect density.

[0085] In addition, the present application does not exclude the use of other semiconductor materials with lattice constants between the lattice constant of Si and the lattice constant of GaAs as the second semiconductor material. For example, the second semiconductor material can also be aluminum gallium indium phosphide (AlGaInP); (Al y Ga (1-y) ) 0.5 In 0.5 The lattice constant of P is basically equal to the lattice constant of GaAs at room temperature. Therefore, in the direction away from the nucleation layer 220, the total content of Al and Ga can increase from 0 to 0.5 (or increase to close to 0.5); correspondingly, the content of In decreases from 1 to 0.5 (or decreases to close to 0.5).

[0086] In actual preparation, the first transition layer 231 can also be grown using an MOCVD process. Specifically, after the core layer 220 is grown, the growth temperature is slowly lowered to 500°C to 700°C. A phosphorus source, such as PH3, is first introduced for 30 seconds. A gallium source (such as TmGa) and an indium source are then introduced. The amount of indium source introduced increases as the reaction proceeds. The total thickness of the growth is 50nm to 200nm, and the growth pressure is 50mbar to 600mbar.

[0087] Next, please refer to Figure 5 After epitaxially growing the first transition layer 231 on the nucleation layer 220 , the method may further include: epitaxially growing a third transition layer 232 on the first transition layer 231 ; wherein the lattice constant of the material of the third transition layer 232 is equal to the lattice constant of gallium arsenide.

[0088] The material of the third transition layer 232 can also be a gallium phosphide-based semiconductor material. The material of the third transition layer 232 can be, for example, In 0.5 Ga 0.5 P.

[0089] The indium content of the material of the third transition layer 232 is greater than or equal to the indium content of the second semiconductor material. x1 Ga 1-x1 P, the chemical formula of the material of the third transition layer 232 is In x2 Ga 1-x2Taking P as an example, X2 ≥ X1. Since the indium composition varies during the formation of the first transition layer 231 during the actual fabrication process, it can be assumed that the portion formed when the indium composition increases to 0.5 belongs to the third transition layer 232, while the portion formed before the indium composition increases to 0.5 belongs to the first transition layer 231. Thus, X2 > X1. It is understandable that this difference is simply due to the artificial definition of the layers; the actual fabricated structure does not differ.

[0090] The lattice constant of the material in the third transition layer 232 remains unchanged, that is, the indium composition remains unchanged.

[0091] The third transition layer 232 is made of a material whose lattice matches that of GaAs, providing higher crystal quality and further improving threading dislocations.

[0092] In actual preparation, when the lattice constant of InGaP is equal to that of GaAs, a certain growth thickness needs to be maintained, that is, the third transition layer 232 has a certain thickness. Exemplarily, the thickness of the third transition layer 232 is between 50 nm and 5000 nm.

[0093] The growth temperature of the third transition layer 232 is, for example, 500 degrees Celsius to 700 degrees Celsius; the growth pressure is, for example, 50 mbar to 600 mbar.

[0094] Next, please refer to Figure 6 Step 104 is performed to epitaxially grow a second transition layer 233 on the first transition layer 231. In an optional specific example, the second transition layer 233 is grown on the third transition layer 232. The material of the second transition layer 233 includes a third semiconductor material.

[0095] The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide.

[0096] Exemplarily, the third semiconductor material is aluminum gallium indium phosphide arsenide (AlGaInPAs).

[0097] The second transition layer 233 further realizes band gap transition while improving lattice matching, reduces the energy band difference between the first transition layer 231 / the second transition layer 233 and gallium arsenide, and improves series resistance.

[0098] The lattice constant of the material of the second transition layer 233 may also be equal to the lattice constant of gallium arsenide, so as to always maintain lattice matching.

[0099] In actual fabrication, after forming the third transition layer 232, the temperature can be rapidly raised to 600°C to 800°C; the growth pressure can be, for example, 50 mbar to 600 mbar. The growth thickness can be, for example, 50 nm to 5000 nm. As the epitaxial growth process progresses, the phosphorus source dosage is reduced and the arsenic source dosage is increased, to obtain the following second transition layer 233: As the direction away from the silicon substrate 210, the phosphorus content in the second transition layer 233 decreases from 100% to 0, while the arsenic content increases from 0 to 100%. It can be understood that the phosphorus source dosage decreases from high to low, and the arsenic source dosage increases from low to high, thereby gradually transitioning the material from indium gallium phosphide to gallium arsenide.

[0100] The amount of aluminum, gallium, and indium introduced is slowly adjusted to always maintain lattice matching.

[0101] Next, please refer to Figure 7 Step 105 is executed to epitaxially grow a gallium arsenide layer 234 on the second transition layer 233 .

[0102] Because the lattice constant of the epitaxial layer gradually transitions to that of GaAs (even to the same lattice constant as GaAs) and the band gap gradually transitions to that of GaAs (even to the same band gap as GaAs) in the aforementioned steps, the GaAs layer 234 grown using this method has a low defect density and few threading dislocations, thereby significantly reducing the full width at half maximum. Furthermore, the crack problem caused by lattice mismatch is greatly improved, thereby enabling the growth of a high-quality GaAs layer.

[0103] Please refer to Figure 8 As an optional embodiment, epitaxially growing a gallium arsenide layer 234 on the second transition layer 233 includes: epitaxially growing a first gallium arsenide layer 2341 on the second transition layer 233; epitaxially growing a superlattice layer 235 on the first gallium arsenide layer 2341, the superlattice layer 235 including periodically alternately arranged aluminum arsenide layers and second gallium arsenide layers (the aluminum arsenide layers and the second gallium arsenide layers can refer to Figure 8 a and b in the figure, wherein the reference numeral of the second gallium arsenide layer can also be represented by 2342).

[0104] By alternately growing an aluminum arsenide layer and a second gallium arsenide layer on the first gallium arsenide layer 2341, the dislocation density of the material can be further reduced and the crystal quality can be improved. Specifically, there is a small deviation in the lattice constants of AlAs and GaAs, which can produce an effect of burying threading dislocations at the interface between the two. If a small amount of threading dislocations still exist after the epitaxial layer grows to the first gallium arsenide layer 2341, the threading dislocations can be further buried by the superlattice layer 235. Optionally, the aluminum arsenide layer and the second gallium arsenide layer (please refer to Figure 8The arrangement period of a) and b) is 9 to 11. After 9 to 11 periods of burial, the threading dislocations can be basically eliminated.

[0105] In addition, in order to further grow a gallium arsenide-based semiconductor material layer, a second gallium arsenide layer 2342 is arranged on a side of the superlattice layer 235 away from the first gallium arsenide layer 2341 .

[0106] The thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer can be in the range of (1-3):1. This ratio range is more conducive to burying threading dislocations and repairing crystal quality. When the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is greater than 3:1, the aluminum arsenide layer is too thick, resulting in increased resistance; and when the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is less than 1:1, the effect of burying threading dislocations is not ideal. In actual preparation, the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is, for example, 1:1 or 2:1.

[0107] On this basis, the present application embodiment also provides a silicon-based gallium arsenide epitaxial structure, please continue to refer to Figure 7 and Figure 8 The silicon-based gallium arsenide epitaxial structure includes:

[0108] Silicon substrate 210;

[0109] a nucleation layer 220 located on the silicon substrate 210, wherein the material of the nucleation layer 220 includes a first semiconductor material;

[0110] a first transition layer 231 located on the nucleation layer 220 , wherein the material of the first transition layer 231 includes a second semiconductor material;

[0111] The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, and the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide;

[0112] a second transition layer 233 located on the first transition layer 231 , wherein the material of the second transition layer 233 includes a third semiconductor material;

[0113] a gallium arsenide layer 234 located on the second transition layer 233;

[0114] The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide.

[0115] As an optional implementation, the first semiconductor material is gallium phosphide; the second semiconductor material is gallium indium phosphide; and the third semiconductor material is aluminum gallium indium arsenide phosphide.

[0116] As an optional embodiment, the indium component in the first transition layer 231 increases in a direction away from the nucleation layer 220 and the gallium component decreases in a direction away from the nucleation layer 220 .

[0117] As an optional embodiment, the silicon-based GaAs epitaxial structure further includes: a third transition layer 232 located between the first transition layer 231 and the second transition layer 233 , wherein the lattice constant of the material of the third transition layer 232 is equal to that of GaAs.

[0118] As an optional implementation, the thickness of the third transition layer 232 is between 50 nm and 5000 nm.

[0119] As an optional embodiment, in a direction away from the silicon substrate 210 , the phosphorus content in the second transition layer 233 decreases from 100% to 0 and the arsenic content increases from 0 to 100%.

[0120] As an optional embodiment, the gallium arsenide layer 234 includes: a first gallium arsenide layer 2341 and a second gallium arsenide layer 2342;

[0121] The first gallium arsenide layer 2341 is located on the second transition layer 233;

[0122] The second gallium arsenide layer 2342 and the aluminum arsenide layer are periodically and alternately arranged to form a superlattice layer 235 . The superlattice layer 235 is located on the first gallium arsenide layer 2341 .

[0123] As an optional embodiment, the aluminum arsenide layer and the second gallium arsenide layer (please refer to Figure 8 The arrangement period of a) and b) is 9 to 11; the second gallium arsenide layer 2342 is arranged on the side of the superlattice layer 235 away from the first gallium arsenide layer 2341 .

[0124] As an optional embodiment, the thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is in the range of (1-3):1.

[0125] On this basis, an embodiment of the present application also provides a method for preparing a laser, which includes the steps in the method for preparing a silicon-based gallium arsenide epitaxial structure as described in any of the above embodiments, or includes preparing a laser using the silicon-based gallium arsenide epitaxial structure described in any of the above embodiments.

[0126] For example, the laser may be a vertical-cavity surface-emitting laser (VCSEL). In addition, the present application does not exclude the possibility that the laser is an edge-emitting laser.

[0127] Next, the method for preparing the laser provided in the embodiment of the present application is further described in detail with reference to specific examples.

[0128] Please refer to Figure 9 .exist Figure 7 On the basis of the prepared silicon-based gallium arsenide epitaxial structure shown, a first conductive semiconductor layer 240, an active layer 250 and a second conductive semiconductor layer 270 are further epitaxially grown; wherein the first conductive semiconductor layer 240 and the second conductive semiconductor layer 270 have opposite conductivity types, and the materials of the first conductive semiconductor layer 240 and the second conductive semiconductor layer 270 include gallium arsenide-based semiconductor materials.

[0129] Illustratively, the first conductive semiconductor layer 240 is an N-type Bragg reflective layer (N-type DBR layer), and the second conductive semiconductor layer 270 is a P-type Bragg reflective layer (P-type DBR layer).

[0130] The material of the first conductive semiconductor layer 240 includes, for example, aluminum gallium arsenide, and the first conductive semiconductor layer 240 can be specifically Al 0.1 Ga 0.9 As and Al 0.9 Ga 0.1 As is arranged periodically and alternately in a superlattice structure. The arrangement period is, for example, 40. The first conductive semiconductor layer 240 is arranged on the side close to the silicon substrate 210 with Al 0.1 Ga 0.9 As, Al is arranged on the side away from the silicon substrate 210 0.9 Ga 0.1 As.

[0131] The active layer 250 is, for example, a multi-quantum well layer (MQw), which may be similar to the corresponding structure in a general VCSEL and will not be described in detail here.

[0132] The material of the second conductive semiconductor layer 270 includes, for example, aluminum gallium arsenide, and the second conductive semiconductor layer 270 can be specifically Al 0.1 Ga 0.9 As and Al 0.9 Ga 0.1 As is arranged periodically and alternately in a superlattice structure. The arrangement period is, for example, 18. The second conductive semiconductor layer 270 is arranged on the side close to the silicon substrate 210 with Al 0.1 Ga 0.9 As, Al is arranged on the side away from the silicon substrate 210 0.9 Ga 0.1 As.

[0133] A functional layer 260 for forming an oxide layer may be further included between the active layer 250 and the second conductive semiconductor layer 270. The material of the functional layer 260 includes, for example, aluminum gallium arsenide, and may specifically be Al 0.98 Ga 0.02 As.

[0134] A gallium arsenide capping layer may also be epitaxially grown on the second conductive semiconductor layer 270 , which will not be described in detail here.

[0135] On this basis, the embodiment of the present application also provides a laser, please continue to refer to Figure 9 The laser includes: the silicon-based gallium arsenide epitaxial structure described in any of the above embodiments; and a first conductive semiconductor layer 240, an active layer 250, and a second conductive semiconductor layer 270 located on the silicon-based gallium arsenide epitaxial structure; wherein the first conductive semiconductor layer 240 and the second conductive semiconductor layer 270 have opposite conductivity types, and the materials of the first conductive semiconductor layer 240 and the second conductive semiconductor layer 270 include gallium arsenide-based semiconductor materials.

[0136] It should be noted that the embodiments of the method for preparing a silicon-based gallium arsenide epitaxial structure, the embodiment of the silicon-based gallium arsenide epitaxial structure, the embodiment of the method for preparing a laser, and the embodiment of the laser provided in this application belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict.

[0137] It should be understood that the above embodiments are exemplary and are not intended to encompass all possible implementations of the claims. Various modifications and variations may be made to the above embodiments without departing from the scope of the present disclosure. Similarly, the various technical features of the above embodiments may be arbitrarily combined to form additional embodiments of the present application that may not be explicitly described. Therefore, the above embodiments merely illustrate several implementations of the present application and do not limit the scope of protection of the patent application.

Claims

1. A method for preparing a silicon-based gallium arsenide epitaxial structure, characterized in that: The method comprises: providing a silicon substrate; epitaxially growing a nucleation layer on the silicon substrate, wherein the material of the nucleation layer includes a first semiconductor material; epitaxially growing a first transition layer on the nucleation layer, wherein the material of the first transition layer includes a second semiconductor material; The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide, and the lattice constant of the material of the first transition layer gradually transitions to the lattice constant of gallium arsenide in a direction away from the silicon substrate; epitaxially growing a second transition layer on the first transition layer, wherein the material of the second transition layer includes a third semiconductor material; epitaxially growing a gallium arsenide layer on the second transition layer; The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide, the lattice constant of the material of the second transition layer is equal to the lattice constant of gallium arsenide, and the band gap of the material of the second transition layer gradually transitions to the band gap of gallium arsenide in the direction away from the silicon substrate.

2. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 1, characterized in that: The first semiconductor material includes gallium phosphide; the second semiconductor material includes indium gallium phosphide; and the third semiconductor material includes aluminum gallium indium phosphide.

3. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 2, characterized in that: The epitaxial growth of the first transition layer on the nucleation layer comprises: During the epitaxial growth process, the content of the indium source is increased to epitaxially grow a first transition layer on the nucleation layer, wherein the indium component increases and the gallium component decreases in a direction away from the nucleation layer.

4. The method for preparing a silicon-based gallium arsenide epitaxial structure according to any one of claims 1 to 3, characterized in that: After epitaxially growing a first transition layer on the nucleation layer and before epitaxially growing a second transition layer on the first transition layer, the method includes: A third transition layer is epitaxially grown on the first transition layer; wherein the second transition layer is grown on the third transition layer, and the lattice constant of the material of the third transition layer is equal to the lattice constant of gallium arsenide.

5. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 2, wherein: The step of epitaxially growing a second transition layer on the first transition layer comprises: As the epitaxial growth process proceeds, the amount of phosphorus source introduced is reduced and the amount of arsenic source introduced is increased to obtain the following second transition layer: in the direction away from the silicon substrate, the phosphorus content in the second transition layer decreases from 100% to 0 and the arsenic content increases from 0 to 100%.

6. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 1, characterized in that: The epitaxial growth of the gallium arsenide layer on the second transition layer includes: epitaxially growing a first gallium arsenide layer on the second transition layer; A superlattice layer is epitaxially generated on the first gallium arsenide layer. The superlattice layer includes aluminum arsenide layers and second gallium arsenide layers that are periodically and alternately arranged.

7. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 6, characterized in that: The arrangement period of the aluminum arsenide layer and the second gallium arsenide layer is 9 to 11; the second gallium arsenide layer is arranged on a side of the superlattice layer away from the first gallium arsenide layer.

8. The method for preparing a silicon-based gallium arsenide epitaxial structure according to claim 6, characterized in that: The thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is in the range of (1-3):

1.

9. A silicon-based gallium arsenide epitaxial structure, characterized in that: include: Silicon substrate; a nucleation layer located on the silicon substrate, wherein the material of the nucleation layer comprises a first semiconductor material; a first transition layer located on the nucleation layer, wherein the material of the first transition layer comprises a second semiconductor material; The first semiconductor material and the second semiconductor material are both gallium phosphide-based semiconductor materials, the lattice constant of the first semiconductor material is between the lattice constant of silicon and the lattice constant of the second semiconductor material, the lattice constant of the second semiconductor material is between the lattice constant of the first semiconductor material and the lattice constant of gallium arsenide, and the lattice constant of the material of the first transition layer gradually transitions to the lattice constant of gallium arsenide in a direction away from the silicon substrate; a second transition layer located on the first transition layer, wherein the material of the second transition layer includes a third semiconductor material; a gallium arsenide layer located on the second transition layer; The band gap of the third semiconductor material is between the band gap of the second semiconductor material and the band gap of gallium arsenide, the lattice constant of the material of the second transition layer is equal to the lattice constant of gallium arsenide, and the band gap of the material of the second transition layer gradually transitions to the band gap of gallium arsenide in the direction away from the silicon substrate.

10. The silicon-based gallium arsenide epitaxial structure according to claim 9, characterized in that: The first semiconductor material includes gallium phosphide; the second semiconductor material includes indium gallium phosphide; and the third semiconductor material includes aluminum gallium indium phosphide.

11. The silicon-based gallium arsenide epitaxial structure according to claim 10, characterized in that: The indium component in the first transition layer increases in a direction away from the nucleation layer and the gallium component decreases in a direction away from the nucleation layer.

12. The GaAs-on-Si epitaxial structure according to any one of claims 9 to 11, characterized in that: Also includes: The third transition layer is located between the first transition layer and the second transition layer. The lattice constant of the material of the third transition layer is equal to the lattice constant of gallium arsenide.

13. The silicon-based gallium arsenide epitaxial structure according to claim 10, characterized in that: In a direction away from the silicon substrate, the phosphorus content in the second transition layer decreases from 100% to 0 and the arsenic content increases from 0 to 100%.

14. The silicon-based gallium arsenide epitaxial structure according to claim 9, characterized in that: The gallium arsenide layer includes: a first gallium arsenide layer and a second gallium arsenide layer; The first gallium arsenide layer is located on the second transition layer; The second gallium arsenide layer and the aluminum arsenide layer are periodically and alternately arranged to form a superlattice layer, and the superlattice layer is located on the first gallium arsenide layer.

15. The silicon-based gallium arsenide epitaxial structure according to claim 14, characterized in that: The arrangement period of the aluminum arsenide layer and the second gallium arsenide layer is 9 to 11; the second gallium arsenide layer is arranged on a side of the superlattice layer away from the first gallium arsenide layer.

16. The silicon-based gallium arsenide epitaxial structure according to claim 14, characterized in that: The thickness ratio of the aluminum arsenide layer to the second gallium arsenide layer is in the range of (1-3):

1.

17. A method for preparing a laser, characterized in that: The method comprises the steps of the method for preparing a silicon-based gallium arsenide epitaxial structure according to any one of claims 1 to 8, or comprises preparing a laser using the silicon-based gallium arsenide epitaxial structure according to any one of claims 9 to 16.

18. A laser, characterized in that: include: The silicon-based gallium arsenide epitaxial structure according to any one of claims 9 to 16; and a first conductive semiconductor layer, an active layer, and a second conductive semiconductor layer located on the silicon-based gallium arsenide epitaxial structure; wherein the first conductive semiconductor layer and the second conductive semiconductor layer have opposite conductivity types, and the materials of the first conductive semiconductor layer and the second conductive semiconductor layer include gallium arsenide-based semiconductor materials.

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