LDMOS device and method of manufacturing the same

Abstract

The application provides an LDMOS device and a manufacturing method thereof. A hole field plate is formed on a blocking layer of a drift region between a polysilicon field plate and a gate, and the thickness of the blocking layer at the bottom of the hole field plate is greater than the thickness of a gate oxide layer at the bottom of the polysilicon field plate. Thus, by using the feature that the thickness of the blocking layer is greater than the thickness of the gate oxide layer, a better RESURF result can be achieved by making the thickness of the dielectric film under the field plate of the drift region thicker near the drain and thinner near the gate, and thus a higher breakdown voltage and a lower on-resistance can be achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to an LDMOS device and its manufacturing method. Background Technology

[0002] Laterally diffused metal-oxide transistors (LDMOS) have advantages such as high voltage withstand capability, high gain, and low distortion, and are more easily compatible with complementary metal-oxide transistor (CMOS) processes, thus they are widely used in integrated circuits.

[0003] For LDMOS devices, a high breakdown voltage (BV) and a low on-resistance (Rsp) are required. The mainstream approach is to improve the breakdown voltage using RESURF (Reduced Surface Field) technology. One type of RESURF technology involves forming a polysilicon field during the fabrication of the gate to reduce the surface electric field.

[0004] However, this RESURF technology can no longer meet the requirements of LDMOS devices with higher breakdown voltage and lower on-resistance. Summary of the Invention

[0005] The purpose of this invention is to provide an LDMOS device and its manufacturing method, which can achieve better RESURF effect, thereby increasing the breakdown voltage of the device and reducing the on-resistance.

[0006] To achieve the above objectives, the present invention provides a method for manufacturing an LDMOS device, comprising:

[0007] A substrate is provided in which a well region and a drift region are formed, an active region is formed in the well region, a drain region is formed in the drift region, a gate and a polysilicon field plate are formed on the substrate, the polysilicon field plate is located on the drift region between the drain region and the gate, and a gate oxide layer is provided between the polysilicon field plate and the drift region and between the gate and the substrate.

[0008] A barrier layer is formed, which covers the drift region between the gate and the polysilicon field plate;

[0009] A perforated field plate is formed on the barrier layer, and the thickness of the barrier layer at the bottom of the perforated field plate is greater than the thickness of the gate oxide layer at the bottom of the polycrystalline silicon field plate.

[0010] Optionally, the step of providing a substrate having the gate, the polysilicon field plate, the source region, and the drain region formed includes:

[0011] A substrate is provided, and a portion of the substrate is ion implanted to form a well region of a first conductivity type;

[0012] Ion implantation is performed on a portion of the substrate outside the well region to form a drift region of a second conductivity type;

[0013] A gate oxide layer and a polysilicon layer are sequentially deposited on the substrate, and the polysilicon layer and the gate oxide layer are etched to form the gate and the polysilicon field plate;

[0014] Source and drain ion implantation is performed on the substrate to form the source region in the well region and the drain region in the drift region.

[0015] Optionally, before forming the barrier layer on the substrate, the method further includes forming a dielectric sidewall on the sidewalls of the gate and the polysilicon field plate.

[0016] Optionally, the barrier layer includes at least two dielectric layers of different materials stacked sequentially, wherein at least one of the dielectric layers serves as an etching stop layer in the step of forming a hole field plate located on the barrier layer.

[0017] Optionally, the step of forming a perforated plate on the barrier layer includes:

[0018] An interlayer dielectric layer is formed on the substrate, which buries the gate, the polysilicon field plate, and the barrier layer.

[0019] At least the interlayer dielectric layer above the barrier layer is etched to form at least one field plate hole;

[0020] The field plate holes are filled with conductive material to form the hole field plate.

[0021] Optionally, the method for manufacturing the LDMOS device further includes:

[0022] The interlayer dielectric layer on the polysilicon field plate, the gate, the source region and the drain region is etched to form polysilicon field plate contact holes, gate contact holes, source contact holes and drain contact holes, respectively.

[0023] The contact holes, gate contact holes, source contact holes, and drain contact holes of the polycrystalline silicon field plate are filled with conductive material;

[0024] A gate metal layer, a source metal layer, and a drain metal layer are formed on the interlayer dielectric layer. The drain metal layer is electrically connected to the via field plate and is electrically connected to the drain region and the polysilicon field plate through the drain contact hole and the polysilicon field plate contact hole. The gate metal layer is electrically connected to the gate through the gate contact hole, and the source metal layer is electrically connected to the source region through the source contact hole.

[0025] Optionally, the manufacturing method further includes forming a metal silicide layer on the surfaces of the source region, the drain region, the polysilicon field plate, and the gate before forming the aperture field plate.

[0026] Optionally, the manufacturing method further includes forming a shallow trench isolation structure or a localized oxide isolation structure in the drift region covered by the barrier layer before forming the gate and the polysilicon field plate.

[0027] Based on the same inventive concept, the present invention also provides an LDMOS device, comprising:

[0028] A substrate having a well region and a drift region formed therein, wherein an active region is formed in the well region and a drain region is formed in the drift region;

[0029] Both the gate and the polysilicon field plate are formed on the substrate. A gate oxide layer is provided between the gate and the substrate and between the polysilicon field plate and the drift region. The polysilicon field plate is located on the drift region between the gate and the drain region.

[0030] A barrier layer covers the drift region between the polysilicon field plate and the gate.

[0031] A perforated field plate is formed on the barrier layer, and the thickness of the barrier layer at the bottom of the perforated field plate is greater than the thickness of the gate oxide layer at the bottom of the polycrystalline silicon field plate.

[0032] Optionally, the barrier layer includes at least two dielectric layers of different materials stacked sequentially, wherein at least one of the dielectric layers serves as an etching stop layer at the bottom of the aperture plate.

[0033] Optionally, the LDMOS device further includes an interlayer dielectric layer formed on the substrate, which buries the barrier layer, the gate, and the polysilicon field plate therein, and at least one field plate hole is formed in the interlayer dielectric layer above the barrier layer, and each of the field plate holes is filled with conductive material to form the hole field plate.

[0034] Optionally, the interlayer dielectric layer further includes drain contact holes, polysilicon field plate contact holes, source contact holes, and gate contact holes, and the drain contact holes, source contact holes, and gate contact holes are all filled with conductive material; the LDMOS device further includes a gate metal layer, a source metal layer, and a drain metal layer formed on the interlayer dielectric layer, the drain metal layer being electrically connected to the field plate and electrically connected to the drain region and the polysilicon field plate through the drain contact holes and the polysilicon field plate contact holes, the gate metal layer being electrically connected to the gate through the gate contact holes, and the source metal layer being electrically connected to the source region through the source contact holes.

[0035] Optionally, the LDMOS device further includes metal silicide layers formed on the surfaces of the source region, the drain region, the polysilicon field plate, and the gate, respectively, with the interlayer dielectric layer covering the metal silicide layers.

[0036] Optionally, the LDMOS device further includes a shallow trench isolation structure or a localized oxide isolation structure formed in the drift region covered by the barrier layer.

[0037] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0038] 1. A barrier layer with a thickness greater than that of the gate oxide is added to the drift region between the gate and the polysilicon field plate, and a hole field plate is further formed on the barrier layer. By taking advantage of the fact that the thickness of the barrier layer is greater than that of the gate oxide layer, the dielectric film under the field plate in the drift region is thicker, thinner near the drain region and thicker near the gate, which achieves better RESURF results, thereby improving the breakdown voltage BV and reducing the on-resistance Rsp of the LDMOS device.

[0039] 2. A barrier layer is formed by stacking at least two dielectric layers of different materials. This allows the corresponding dielectric layer in the barrier layer to serve as a stop layer (etch termination layer) in the hole field plate formation step. This enables more precise control of the bottom depth of the hole field plate. Furthermore, the entire barrier layer can be completed in a single photolithography step without increasing the number of photolithography steps. Therefore, no additional mask layers are required. Only simple process adjustments are needed to make it compatible with existing processes, resulting in low cost. Attached Figure Description

[0040] Figures 1 to 2 This is a schematic diagram of the cross-sectional structure of an LDMOS device in an existing manufacturing method.

[0041] Figure 3 This is a schematic flowchart illustrating the manufacturing method of an LDMOS device according to a specific embodiment of the present invention.

[0042] Figures 4 to 8 This is a schematic cross-sectional view of an example device in a method for manufacturing an LDMOS device according to an embodiment of the present invention.

[0043] Figures 9 to 12 This is a schematic cross-sectional view of another example device in the manufacturing method of an LDMOS device according to an embodiment of the present invention. Detailed Implementation

[0044] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the disclosure thorough and complete, and to fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when a layer is referred to as being formed on other layers, it may be formed directly on the other layers, or an intervening film layer may be present. The terms “upper,” “lower,” “top,” “bottom,” “inner,” “middle,” “longitudinal,” and “lateral,” etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. “Longitudinal” can be understood as a direction perpendicular to the substrate surface, and “lateral” can be understood as a direction parallel to the substrate surface. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “comprising” is used to determine the presence of possible features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items. The terms “identical” and “consistent” include the meaning of being completely equal and identical, and may also include the meaning of being approximately identical or approximately equal within permissible process tolerances. The terms "first," "second," etc., used in this specification are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, used so in this way, may be replaced where appropriate, for example, to allow embodiments of the invention described herein to operate in a different order than that described or shown herein. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which these steps can be performed, and some described steps may be omitted and / or some other steps not described herein may be added to the method. If a component in one figure is identical to a component in another figure, although these components are readily identifiable in all figures, this specification will not label all identical components in every figure for the sake of clarity.

[0045] Please refer to Figure 1 and Figure 2An existing method for manufacturing LDMOS devices is described below:

[0046] First, a well region 101 (e.g., a P-type well) and a drift region 102 (e.g., an N-type drift region) are sequentially formed in a substrate 100 (e.g., a P-type substrate) using a corresponding ion implantation process.

[0047] Then, a gate oxide layer and a polysilicon layer are deposited and etched to form a gate 103 and a polysilicon field plate 104.

[0048] Next, source region 105 and drain region 106 are formed in substrate 100 by source-drain ion implantation process;

[0049] Then, silicon dioxide (SiO2) is deposited as a barrier layer 108 (silicide block layer), and excess barrier layer is etched away. Furthermore, a metal silicide layer 107 is formed through a self-aligned metal silicide process.

[0050] Subsequently, the interlayer medium layer 109 is deposited and the subsequent contact CT and metal layer 110 processes are completed.

[0051] In the aforementioned LDMOS device manufacturing method, a polysilicon field plate is formed simultaneously with the gate fabrication. This polysilicon field plate is electrically connected to the drain region via a field plate plug on its top, achieving equipotential with the drain region to reduce the surface electric field. However, this RESURF technology can no longer meet the requirements of LDMOS devices with higher breakdown voltage and lower on-resistance.

[0052] This invention proposes an LDMOS device and its manufacturing method. Based on the prior art, a barrier layer with a thickness greater than that of the gate oxide is added to the drift region between the gate and the polysilicon field plate, and a via field plate is further formed on the barrier layer. By utilizing the characteristic that the thickness of the barrier layer is greater than that of the gate oxide layer, the dielectric film under the field plate in the drift region is thicker, thinner near the drain region and thicker near the gate, achieving better RESURF results, thereby improving the breakdown voltage BV and reducing the on-resistance Rsp of the LDMOS device.

[0053] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0054] Please refer to Figure 3 An embodiment of the present invention provides a method for manufacturing an LDMOS device, comprising:

[0055] S1, a substrate is provided, wherein a well region and a drift region are formed in the substrate, an active region is formed in the well region, a drain region is formed in the drift region, a gate and a polysilicon field plate are formed on the substrate, the polysilicon field plate is located on the drift region between the drain region and the gate, and a gate oxide layer is provided between the polysilicon field plate and the substrate and between the gate and the substrate.

[0056] S2, forming a barrier layer that covers the drift region between the gate and the polysilicon field plate;

[0057] S3, forming a perforated field plate on the barrier layer, wherein the thickness of the barrier layer at the bottom of the perforated field plate is greater than the thickness of the gate oxide layer at the bottom of the polycrystalline silicon field plate.

[0058] The substrate 100 provided in step S1 can be any suitable substrate material, such as silicon, silicon-on-insulator, germanium, silicon carbide, silicon germanide, etc., or a substrate material on which a semiconductor epitaxial layer such as silicon carbide is epitaxially grown. The conductivity type of the substrate is, for example, P-type.

[0059] Please refer to Figure 7 In step S1, a well region 101 and a drift region 102 are formed in the substrate 100. An active region 105 is formed in the well region 101, and a drain region 106 is formed in the drift region 102. A gate 103 and a polysilicon field plate 104 are formed on the substrate 100. The polysilicon field plate 104 is located on the drift region 102 between the drain region 106 and the gate 103. Gate oxide layers 103' are provided between the gate 103 and the substrate 100, and between the polysilicon field plate 104 and the drift region 102. The specific process of forming these structures on the substrate 100 includes the following steps:

[0060] S1.1, please refer to Figure 4 A photoresist (PR) layer 201 is coated on the substrate 100. The photoresist layer 201 is photolithographically etched (including exposure and development) to expose a portion of the surface of the substrate 100 (i.e., the area to be formed as the well region 101). Then, using the photolithographically etched photoresist layer 201 as a mask, ion implantation is performed on the exposed area of ​​the substrate 100 to form a well region 101 of the first conductivity type (e.g., P-type).

[0061] S1.2, please refer to Figure 5The photoresist layer 201 is removed, and a photoresist material is recoated on the substrate 100 to form a photoresist layer 202. The photoresist layer 202 is photolithographically etched (including exposure and development) to mask the well region 101 and expose a portion of the substrate 100 outside the well region 101 (i.e., the region where the drift region 102 is to be formed). Then, using the photolithographically etched photoresist layer 202 as a mask, ion implantation is performed on the exposed area of ​​the substrate 100 to form a drift region 102 of the second conductivity type (e.g., N-type), which serves as the voltage withstand region of the LDMOS device.

[0062] S1.3, please refer to Figure 6 The photoresist layer 202 is removed, and a gate oxide layer (e.g., silicon oxide) 103' is formed on the surface of the substrate 100 through a suitable process such as thermal oxidation. The formed gate oxide layer 103' covers the surface of the well region 101 and the drift region 102. A polysilicon layer is further deposited on the gate oxide layer 103', a photoresist (not shown) is coated, and the photoresist is photolithographically etched using a mask layer. Using the photolithographically etched photoresist layer as a mask, the polysilicon layer and the gate oxide layer 103' are etched until the surface of the well region 101 and the drift region 102 is exposed, forming the gate 103 and the polysilicon field plate 104. The gate 103 spans the boundary region between the well region 101 and the drift region 102 to extend from the well region 101 to the drift region 102. The polysilicon field plate 104 is located on the drift region 102, and the polysilicon field plate 104 and the gate 103 are spaced apart, that is, a gap 103a is formed between the polysilicon field plate 104 and the gate 103, exposing a portion of the surface of the drift region 102.

[0063] S1.4, please refer to Figure 7 Ion implantation of the second conductivity type and the first conductivity type are performed on the corresponding regions of the well region 101 on one side of the gate 103 to form the source region 105 in the well region 101 and the bulk contact region 105' of the well region 101 outside the source region 105; then, ion implantation of the second conductivity type is performed on the drift region 102 outside the polysilicon field plate 104 to form the drain region 106. After that, a high-temperature annealing treatment between 800°C and 1000°C is performed to fully activate the ions (i.e., impurities) in the substrate 100.

[0064] As an example, both the substrate 100 and the well region 101 are of a first conductivity type, specifically P-type, and the second conductivity type is N-type. In other embodiments of the invention, the first conductivity type may be N-type, and the second conductivity type may be P-type.

[0065] Furthermore, the ion doping concentrations of both the drift region 102 and the well region 101 need to be rationally designed based on the breakdown voltage requirements and on-resistance requirements of the LDMOS device. In steps S1.1 and S1.2, annealing can be performed during ion implantation, or annealing can be performed after ion implantation in step S1.2, to ensure that the implanted ions in the well region 101 and drift region 102 diffuse to the required extent in both the lateral and vertical directions. Vertically, the depth of the drift region 102 can be equal to, greater than, or less than the depth of the well region 101; laterally, the drift region 102 can be connected to or spaced apart from the well region 101.

[0066] After the gate 103 and polysilicon field plate 104 are formed and before the source region 105 and drain region 106 are formed, a dielectric sidewall (not shown) can be formed on the sidewalls of the gate 103 and polysilicon field plate 104 to prevent impurities in the gate 103 and polysilicon field plate 104 from diffusing into the subsequent interlayer dielectric layer 109.

[0067] Please refer to Figure 7 In step S2, a barrier layer 107 is formed on the substrate 100, gate 103, and polysilicon field plate 104 using processes such as chemical vapor deposition. A photoresist (not shown) is then coated onto the photoresist, and photolithography is performed on the photoresist using a mask layer. Using the photolithographically etched photoresist layer as a mask, the barrier layer 107 is etched to define the metallized region. The remaining barrier layer 107 covers the drift region 102 between the gate 103 and the polysilicon field plate 104. One side of the remaining barrier layer 107 extends further to the sidewall and part of the top surface of the gate 103, and another layer extends to the sidewall and part of the top surface of the polysilicon field plate 104. In this step, the remaining barrier layer 107 not only exposes the source region 105, body contact region 105', drain region 106, gate 103, and polysilicon field plate 104 for subsequent formation of metal silicides or external connections, but also covers the surface of the drift region 102 between the gate 103 and the polysilicon field plate 104 to provide the process area for the subsequently formed via field plate.

[0068] In this embodiment, the barrier layer 107 includes at least two dielectric layers of different materials stacked sequentially, one of which serves as the etching stop layer in the subsequent step S3. As an example, the barrier layer 107 is formed by alternating layers of silicon dioxide (SiO2) layer 107a and silicon nitride (SiN) layer 107b, such as a SiO2-SiN bilayer dielectric structure, a SiO2-SiN-SiO2-SiN four-layer dielectric structure, or a SiO2-SiN-SiO2-SiN-SiO2 five-layer dielectric structure. The thickness range of each SiO2 layer in the barrier layer 107 is... The thickness range of each SiN layer is as follows: A certain SiN layer in the barrier layer 107 serves as an etching stop layer in the subsequent step S3, used to precisely define the depth of the bottom of the formed aperture field plate, ensuring that the thickness of the barrier layer 107 at the bottom of the formed aperture field plate is greater than the thickness of the gate oxide layer 103' at the bottom of the polysilicon field plate 104.

[0069] In other examples of this embodiment, in step S1, other dielectric isolation structures may also be formed in the drift region 102 below the bottom of the barrier layer 107 (i.e., the drift region 102 below the gap 103a) to further optimize the RESURF effect. For example, please refer to... Figure 11 A shallow trench isolation (STI) structure 111 can also be formed in the drift region 102 below the bottom of the barrier layer 107. The gate 103 overlaps with the shallow trench isolation (STI) structure 111, and the polysilicon field plate 104 also overlaps with the shallow trench isolation (STI) structure 111. This shallow trench isolation (STI) structure 111 can serve as a field oxide plate, further optimizing the RESURF effect. For example, please refer to... Figure 12 A localized oxide isolation structure (LOCOS) 112 can also be formed in the drift region 102 below the bottom of the barrier layer 107. The top surface of the localized oxide structure 112 is higher than the substrate 100. The gate 103 extends to one end sidewall and top surface of the localized oxide isolation structure 112 to overlap with it. The polysilicon field plate 104 extends to the other end sidewall and top surface of the localized oxide isolation structure 112 to also overlap with it. The barrier layer 107 covers the top surface of the localized oxide isolation structure 112 exposed by the polysilicon field plate 104 and the gate 103, with one end extending to a portion of the top surface of the gate 103 and the other end extending to a portion of the top surface of the polysilicon field plate 104. This localized oxide isolation structure 112 can serve as a field oxide plate to further optimize the RESURF effect.

[0070] Of course, in other embodiments of the present invention, other different isolation techniques can be used to form a dielectric isolation structure located below the bottom of the barrier layer 107 in the drift region 102 of the gap 103a or on the top surface of the drift region 102 of the gap 103a, so as to further optimize the RESURF effect.

[0071] Furthermore, in other examples of this embodiment, in step S2, after etching the barrier layer 107, a self-aligned metal silicide process (including metal deposition, annealing, removal of unreacted metal, etc.) is further performed to form metal silicide layers 108 on the top surfaces of the source region 105, body contact region 105', drain region 106, gate 103, and polysilicon field plate 104 exposed by the barrier layer 107.

[0072] Please refer to Figure 7 and Figure 8 In step S3, firstly, an interlayer dielectric layer 109 is deposited using a suitable process such as chemical vapor deposition, and then the top surface of the interlayer dielectric layer 109 is planarized using a process such as chemical mechanical polishing. This interlayer dielectric layer 109 can embed structures such as the metal silicide layer 108 and the barrier layer 107 within it.

[0073] Please refer to Figure 7 and Figure 8 In step S3, a photoresist layer (not shown) is then coated, and the photoresist is photolithographically etched using a contact hole mask. Using the photolithographically etched photoresist layer as a mask, the interlayer dielectric layer 109 is etched to form at least one source contact hole CTs, at least one body contact hole CTp, at least one gate contact hole CTg, at least one field plate hole CT1, at least one polysilicon field plate contact hole CT2, and at least one drain contact hole CTd in the interlayer dielectric layer 109.

[0074] In this embodiment, source contact holes CTs penetrate the interlayer dielectric layer 109 and expose the top surface of the metal silicide layer 108 on the top surface of the source region 105; body contact holes CTp penetrate the interlayer dielectric layer 109 and expose the top surface of the metal silicide layer 108 on the top surface of the body contact region 105'; and drain contact holes CTd penetrate the interlayer dielectric layer 109 and expose the top surface of the metal silicide layer 108 on the top surface of the drain region 106. Polysilicon field plate contact holes CT2 penetrate the interlayer dielectric layer 109 and expose the top surface of the metal silicide layer 108 on the top surface of the polysilicon field plate 104. Field plate holes CT1 are located in the gap 103a between the polysilicon gate 103 and the polysilicon field plate 104, and penetrate the interlayer dielectric layer 109. In this embodiment, the field plate holes CT1 stop on the top surface of the top dielectric layer of the barrier layer 107 (i.e., the top surface of the silicon nitride layer 107b), and there is only one such hole. Figure 8 As shown. At this time, the top dielectric layer of the barrier layer 107 (e.g., a silicon nitride SiN layer) serves as an etching stop layer during the process of etching the interlayer dielectric layer 109 to form each contact hole.

[0075] As another example of this embodiment, the field plate hole CT1 located in the gap 103a between the polysilicon gate 103 and the polysilicon field plate 104 stops on the top surface of the top dielectric layer (e.g., silicon nitride SiN layer) of the barrier layer 107, and the number can also be at least two, such as... Figure 9 As shown.

[0076] As another example of this embodiment, the field plate hole CT1 located in the gap 103a between the polysilicon gate 103 and the polysilicon field plate 104 can also stop on a corresponding dielectric layer (e.g., a silicon nitride SiN layer) below the top dielectric layer (e.g., a silicon oxide SiO2 layer) of the barrier layer 107, but never penetrates the barrier layer 107. The number of such holes can be one or more, such as... Figure 10 As shown.

[0077] It should be understood that in the above examples, the thickness of the barrier layer 107 at the bottom of the field plate hole CT1 is greater than the thickness of the gate oxide layer 103' at the bottom of the polysilicon field plate 104. Furthermore, the shape, number, and width of the field plate hole CT1 depend on the gap 103a between the gate 103 and the polysilicon field plate 104, as well as the device performance requirements; this embodiment does not impose specific limitations on these parameters.

[0078] Optionally, the width of the field plate hole CT1 ranges from 0.1 μm to 10 μm.

[0079] Please refer to Figures 8 to 11 In step S3, the contact holes and field plate holes are then filled with a suitable conductive material (e.g., metals such as tungsten or copper, or doped polysilicon) to form a hole field plate (unmarked) in the field plate holes and plugs in each contact hole. For example, the conductive material filled in the source contact holes CTs forms a source plug (unmarked), the conductive material filled in the body contact holes CTp forms a body contact plug (unmarked), the conductive material filled in the drain contact holes CTd forms a drain plug (unmarked), and the conductive material filled in the polysilicon field plate contact hole CT2 forms a polysilicon field plate contact plug (unmarked) on the polysilicon field plate 104. At this time, the barrier layer 107 at the bottom of the formed hole field plate is thicker than the gate oxide layer 103' at the bottom of the polysilicon field plate 104, and the thickness difference is d. This thickness difference d can be controlled by controlling the deposition thickness of the barrier layer 107 in step S2 and controlling the bottom depth of the field plate hole CT1 in step S3.

[0080] Please refer to Figures 8 to 11In step S3, a metal layer is then deposited and etched to form a source metal layer 110s, a gate metal layer 110g, and a drain metal layer 110d. The source metal layer 110s is electrically connected to each body contact plug and the source plug, such that the body contact region 105' and the source region 105 are at the same potential. The gate metal layer 110g is electrically connected to each gate plug, electrically connecting the gate 103. The drain metal layer 110d is electrically connected to the drain plug, the field plate filled in the field plate hole CT1, and the polysilicon field plate contact plug filled in the polysilicon field plate contact hole CT2. Thus, the formed field plate is electrically connected to the polysilicon field plate 104 and the drain region 106 through the drain metal layer 110d, such that the field plate, polysilicon field plate 104, and drain region 106 are at the same potential.

[0081] The LDMOS device manufacturing method of this embodiment forms a hole field plate located in the drift region on the barrier layer between the polysilicon field plate and the gate. The thickness of the barrier layer at the bottom of the hole field plate is greater than the thickness of the gate oxide layer at the bottom of the polysilicon field plate near the drain region. Thus, in the direction from the gate to the drain region, a dielectric arrangement of different thicknesses is achieved at the bottom of the field plate in the drift region. The film thickness near the gate (i.e., the film thickness of the barrier layer) is thicker, and the film thickness near the drain region (i.e., the film thickness of the gate oxide at the bottom of the polysilicon field plate) is thinner. This does not increase the process difficulty, but improves the effect of optimizing the surface electric field (RESURF), thereby achieving the effect of increasing the breakdown voltage BV and reducing the on-resistance Rsp of the LDMOS device.

[0082] Furthermore, by using a barrier layer composed of at least two dielectric layers of different materials, the corresponding dielectric layer in the barrier layer can serve as a stop layer (etch termination layer) in the hole field plate formation step. This allows for more precise control of the bottom depth of the hole field plate, and the entire multilayer dielectric layer of the barrier layer can be completed in one photolithography step without increasing the number of photolithography steps. Therefore, no additional mask layers are needed, and only simple process adjustments are required to make it compatible with existing processes, resulting in low cost.

[0083] It should be understood that the technical solution of the present invention is not limited to the manufacturing method of the LDMOS device in the above embodiments. Those skilled in the art can make any reasonable modifications based on the above embodiments to obtain other embodiments of the present invention.

[0084] Based on the same inventive concept, one embodiment of the present invention also provides an LDMOS device, which can be formed using the manufacturing method of the LDMOS device described in any of the above embodiments. Please refer to... Figures 8 to 12 The LDMOS device in this embodiment includes: a substrate 100, a gate 103, a polysilicon field plate 104, a source region 105 and a drain region 106, a barrier layer 107 and a via field plate.

[0085] The substrate 100 has a well region 101 and a drift region 102. A gate 103 is formed on the substrate 100, extending on one side to a portion of the top surface of the well region 101 and on the other side to a portion of the top surface of the drift region 102. The gate 103 can be polysilicon, metal, or a combination of both.

[0086] The source region 104 is formed in the sink region 101, and the drain region 105 is formed in the drift region 102.

[0087] Polysilicon field plate 104 is formed on drift region 102 between gate 103 and drain region 106, and has a gap with gate 103 (e.g. Figure 6 (As shown in 103a). A gate oxide layer 103' is provided between the gate 103 and the substrate 100, and between the polysilicon field plate 104 and the drift region 102.

[0088] A barrier layer 107 covers the drift region 102 between the gate 103 and the polysilicon field plate 104. Further, the barrier layer extends continuously from a portion of the top surface of the gate 103 through the drift region 102 of the sidewalls and bottom surface of the gap 103a to a portion of the top surface of the polysilicon field plate 104. The barrier layer 107 can be a single dielectric layer (e.g., silicon dioxide), or it can comprise at least two dielectric layers of different materials stacked sequentially, for example, the barrier layer 107 is formed by alternating layers of silicon dioxide (SiO2) layer 107a and silicon nitride (SiN) layer 107b.

[0089] Hole field plate (unmarked, corresponding to) Figure 12 CT1) is formed on the barrier layer 107, and the thickness of the barrier layer 107 at the bottom of the perforated field plate is greater than the thickness of the gate oxide layer 103' at the bottom of the polysilicon field plate 104.

[0090] Furthermore, the LDMOS device in this embodiment also includes an interlayer dielectric layer 109, a source metal layer 110s, a gate metal layer 110g, and a drain metal layer 110d.

[0091] The interlayer dielectric layer 109 is formed on the substrate 100 and buries both the gate 103 and the polysilicon field plate 104 within the barrier layer 107. The interlayer dielectric layer 109 has drain contact vias CTd, source contact vias CTs, body contact vias CTp, gate contact vias CTg, polysilicon field plate contact vias CT2, and at least one field plate via CT1. The field plate via CT1 is located on the barrier layer 107 between the polysilicon field plate 104 and the gate 103; the polysilicon field plate contact via CT2 is located on the polysilicon field plate 104; the drain contact via CTd is located on the drain region 106; the source contact vias CTs are located on the source region 105; and the body contact via CTp is located on the body contact region 105'.

[0092] The field plate CT1 is formed by filling the field plate hole CT1 with conductive materials such as metal. Optionally, the width of the field plate hole CT1 is in the range of 0.1μm to 10μm.

[0093] The drain contact hole CTd, source contact hole CTs, body contact hole CTp, gate contact hole CTg, and polysilicon field plate contact hole CT2 are filled with corresponding conductive materials such as metal to form corresponding plugs.

[0094] The drain metal layer 110d is formed on the interlayer dielectric layer 109 above the drift region 102, and is electrically connected (i.e., electrically contacted) to the via field plate. It is also electrically connected to the drain region 106 through the drain contact hole CTd, and electrically connected to the polysilicon field plate 104 through the polysilicon field plate contact hole CT2, so that the via field plate, the drain region 106 and the polysilicon field plate 104 are at the same potential.

[0095] The source metal layer 110s is electrically connected to the source region 105 through the source contact hole CTs, and is electrically connected to the body contact region 105' through the body contact hole CTp, so that the body contact region 105' and the source region 105 are at the same potential. The gate metal layer 110g is electrically connected to the gate 103 through the gate contact hole CTg.

[0096] Optionally, the gate 103 and the polysilicon field plate 104 are formed using the same polysilicon layer. The gate oxide layer 103' at the bottom of the gate 103 and the gate oxide layer 103' at the bottom of the polysilicon field plate 104 are formed using the same gate oxide layer.

[0097] The LDMOS device in this embodiment further includes a metal silicide layer 108 formed on the surfaces of the source region 105, drain region 106, polysilicon field plate 104, and gate 103, with an interlayer dielectric layer 109 covering the metal silicide layer 108. The metal silicide layer 108 is used to reduce the on-resistance between the corresponding plug and the corresponding structure in the substrate 100.

[0098] Alternatively, please refer to Figure 11 and Figure 12 The LDMOS device in this embodiment also includes a dielectric isolation structure formed in the drift region 103 at the gap 103a. The dielectric isolation structure can be a shallow trench isolation structure 111, a local oxidation isolation structure 112, or other dielectric isolation structures.

[0099] The LDMOS device in this embodiment utilizes the characteristic that the barrier layer thickness is greater than the gate oxide layer thickness, which enables the dielectric film thickness under the drift region field plate to be thinner near the drain region and thicker near the gate, thereby achieving better RESURF results and thus achieving higher breakdown voltage and lower on-resistance.

[0100] It should be understood that the corresponding structure and materials of the LDMOS device in this embodiment can be referred to the corresponding content in the above-described LDMOS device manufacturing method, and will not be repeated here.

[0101] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the present invention.

Claims

1. A method for manufacturing an LDMOS device, characterized in that, include: A substrate is provided in which a well region and a drift region are formed, an active region is formed in the well region, a drain region is formed in the drift region, a gate and a polysilicon field plate are formed on the substrate, the polysilicon field plate is located on the drift region between the drain region and the gate, and a gate oxide layer is provided between the polysilicon field plate and the drift region and between the gate and the substrate. A barrier layer is formed, which covers the drift region between the gate and the polysilicon field plate; An aperture field plate is formed on the barrier layer, and the thickness of the barrier layer at the bottom of the aperture field plate is greater than the thickness of the gate oxide layer at the bottom of the polysilicon field plate. In the direction from the gate to the drain region, a dielectric arrangement of different thicknesses is realized at the bottom of the field plate in the drift region.

2. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The step of providing a substrate having the gate, the polysilicon field plate, the source region, and the drain region formed thereon includes: A substrate is provided, and a portion of the substrate is ion implanted to form a well region of a first conductivity type; Ion implantation is performed on a portion of the substrate outside the well region to form a drift region of a second conductivity type; A gate oxide layer and a polysilicon layer are sequentially deposited on the substrate, and the polysilicon layer and the gate oxide layer are etched to form the gate and the polysilicon field plate; Source and drain ion implantation is performed on the substrate to form the source region in the well region and the drain region in the drift region.

3. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, Before forming the barrier layer on the substrate, the method further includes forming a dielectric sidewall on the sidewalls of the gate and the polysilicon field plate.

4. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The barrier layer comprises at least two dielectric layers of different materials stacked sequentially, wherein at least one of the dielectric layers serves as an etching stop layer in the step of forming a perforated plate located on the barrier layer.

5. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, The step of forming a perforated field plate located on the barrier layer includes: An interlayer dielectric layer is formed on the substrate, which buries the gate, the polysilicon field plate, and the barrier layer. At least the interlayer dielectric layer above the barrier layer is etched to form at least one field plate hole; The field plate holes are filled with conductive material to form the hole field plate.

6. The method for manufacturing an LDMOS device as described in claim 5, characterized in that, Also includes: The interlayer dielectric layer on the polysilicon field plate, the gate, the source region and the drain region is etched to form polysilicon field plate contact holes, gate contact holes, source contact holes and drain contact holes, respectively. The contact holes, gate contact holes, source contact holes, and drain contact holes of the polycrystalline silicon field plate are filled with conductive material; A gate metal layer, a source metal layer, and a drain metal layer are formed on the interlayer dielectric layer. The drain metal layer is electrically connected to the via field plate and is electrically connected to the drain region and the polysilicon field plate through the drain contact hole and the polysilicon field plate contact hole. The gate metal layer is electrically connected to the gate through the gate contact hole, and the source metal layer is electrically connected to the source region through the source contact hole.

7. The method for manufacturing an LDMOS device as described in claim 1, characterized in that, Also includes: Before forming the aperture field plate, a metal silicide layer is first formed on the surface of the source region, the drain region, the polysilicon field plate, and the gate.

8. The method for manufacturing an LDMOS device as described in any one of claims 1-7, characterized in that, Also includes: Before forming the gate and the polysilicon field plate, a shallow trench isolation structure or a localized oxide isolation structure is also formed in the drift region covered by the barrier layer.

9. An LDMOS device, characterized in that, include: A substrate having a well region and a drift region formed therein, wherein an active region is formed in the well region and a drain region is formed in the drift region; Both the gate and the polysilicon field plate are formed on the substrate. A gate oxide layer is provided between the gate and the substrate and between the polysilicon field plate and the drift region. The polysilicon field plate is located on the drift region between the gate and the drain region. A barrier layer covers the drift region between the polysilicon field plate and the gate. A perforated field plate is formed on the barrier layer, and the thickness of the barrier layer at the bottom of the perforated field plate is greater than the thickness of the gate oxide layer at the bottom of the polysilicon field plate. In the direction from the gate to the drain region, a dielectric arrangement of different thicknesses is realized at the bottom of the field plate in the drift region.

10. The LDMOS device as claimed in claim 9, characterized in that, The barrier layer comprises at least two dielectric layers of different materials stacked sequentially, wherein at least one of the dielectric layers serves as an etching stop layer at the bottom of the aperture plate.

11. The LDMOS device as claimed in claim 9, characterized in that, It also includes an interlayer dielectric layer formed on the substrate, which buries the barrier layer, the gate and the polysilicon field plate therein, and at least one field plate hole is formed in the interlayer dielectric layer above the barrier layer, and each of the field plate holes is filled with conductive material to form the hole field plate.

12. The LDMOS device as claimed in claim 11, characterized in that, The interlayer dielectric layer also forms drain contact holes, polysilicon field plate contact holes, source contact holes and gate contact holes, and the drain contact holes, the source contact holes and the gate contact holes are all filled with conductive material; The LDMOS device further includes a gate metal layer, a source metal layer, and a drain metal layer formed on the interlayer dielectric layer. The drain metal layer is electrically connected to the via field plate and is electrically connected to the drain region and the polysilicon field plate through the drain contact hole and the polysilicon field plate contact hole. The gate metal layer is electrically connected to the gate through the gate contact hole, and the source metal layer is electrically connected to the source region through the source contact hole.

13. The LDMOS device as claimed in claim 11, characterized in that, It also includes metal silicide layers formed on the surfaces of the source region, the drain region, the polysilicon field plate, and the gate, respectively, with the interlayer dielectric layer covering the metal silicide layers.

14. The LDMOS device according to any one of claims 9-13, characterized in that, It also includes shallow trench isolation structures or localized oxidation isolation structures formed in the drift area covered by the barrier layer.

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