Semiconductor device and method for forming a bump pad array on a substrate for ground connection of a heat sink / shield structure

Abstract

A semiconductor device has a substrate and a plurality of first bumps formed in an array on the substrate. An array of second bumps is formed on the substrate on at least two sides of the first bumps. An electrical component is disposed on the first bumps. A packaging structure is disposed on the substrate and the electrical component. The packaging structure has a horizontal member and a leg extending from the horizontal member to form a cavity. The packaging structure is coupled to the array of second bumps. The packaging structure includes a material that operates as a heat sink or a shielding layer. The shielding layer is grounded through the array of second bumps. The first bump and the second bump have similar heights and widths so as to be formed in the same manufacturing step. A protective layer, such as a conductive epoxy, is disposed on the array of second bumps.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to a semiconductor device and method of forming a bump pad array on a substrate for ground connection of a heat sink / shield structure. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communications, often contain one or more integrated passive devices (IPDs) to perform necessary electrical functions. IPDs are susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference (such as capacitive, inductive, or conductive coupling, also known as crosstalk), which may interfere with their operation. High-speed switching of digital circuits can also generate interference.

[0004] For higher density in a small space and expanded electrical functionality, multiple semiconductor dies and discrete IPDs can be integrated. The semiconductor die and discrete IPDs are mounted to a substrate with die bumps for structural support and electrical interconnection. The sealant is deposited on the semiconductor die, discrete IPDs, and substrate. A shielding layer is formed on the sealant to isolate sensitive circuits. The shielding layer needs to be grounded to the substrate to shunt the charge away and effectively reduce RFI / EMI.

[0005] The ground connection between the shielding layer and the substrate can be a conductive glue or conductive epoxy resin, which has a ground bump on the ground pad. Conductive glue and ground bumps are required for the ground connection of the shielding layer and to prevent oxidation. The ground bump is usually much larger than the die bump. Therefore, the ground bump cannot be formed together with the die bump, and vice versa. The difference in the height and width of the die bump and the ground bump requires different bump formation steps, for example, a first bump process for the die bump and a second bump process for the ground bump. In addition to forming the die bump to electrically connect the semiconductor die, the conductive glue and the bump material also require more manufacturing steps. Additional manufacturing steps increase costs and the chance of introducing defects in the manufacturing process. In addition, the difference in the height and width of the die bump and the ground bump may form a gap and cause the shielding layer to be in a skewed or tilted state. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0007] Figure 2a-2k A process for forming an array of bump pads on a substrate for ground connections of a heat sink / shield structure is illustrated;

[0008] Figure 3 illustrates a perspective view of a semiconductor package having an array of bump pads on a substrate for ground connections to a heat sink / shield structure; and

[0009] Figure 4 A printed circuit board (PCB) is illustrated with different types of packages mounted to a surface of the PCB. DETAILED DESCRIPTION

[0010] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0011] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the circuit function.

[0012] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scored and broken along the non-functional areas of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the package. Electrical connections can be made with conductive layers, bumps, stud bumps, conductive glue, or wire bonding. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0013] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0014] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), power amplifiers, application specific integrated circuits (ASICs), memory, or other signal processing circuits. The semiconductor die 104 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0015] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0016] exist Figure 1c In the process, semiconductor wafer 100 is singulated into individual semiconductor die 104 through saw streets 106 using a saw blade or laser cutting tool 118. Individual semiconductor die 104 may be inspected and electrically tested for identification of KGDs after singulation.

[0017] Figure 2a-2k The process of forming an array of bump pads on a substrate for ground connections of a heat sink / shield structure is illustrated. Figure 2a A cross-sectional view of an interconnect substrate or PCB 120 including a conductive layer 122 and an insulating layer 124 is shown. The conductive layer 122 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 122 provides horizontal electrical interconnections across the substrate 120 and vertical electrical interconnections between the top surface 126 and the bottom surface 128 of the substrate 120. Portions of the conductive layer 122 may be electrically common or electrically isolated, depending on the design and function of the semiconductor die 104 and other electrical components. The insulating layer 124 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials having similar insulating and structural properties. The insulating layer 124 provides isolation between the conductive layers 122.

[0018] exist Figure 2bIn the embodiment of the present invention, an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process is used to deposit a conductive bump material on a conductive layer 122 on a surface 126 of an interconnect substrate 120 within a component attachment area 130. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 132. In one embodiment, the bump 132 is formed on an under bump metallization (UBM) having a wetting layer, a barrier layer and an adhesion layer. The bump 132 can also be pressed or thermocompressed to the conductive layer 112. The bump 132 represents a type of interconnect structure that can be formed on the conductive layer 112. The interconnect structure may also use stud bumps, micro bumps, or other electrical interconnects.

[0019] In a similar manner, an evaporation, electrolytic plating, electroless plating, ball drop or screen printing process is used to deposit a conductive bump material on the conductive layer 122 on the surface 126 of the interconnect substrate 120 within the ground pad array area 136a-136b. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 138. In one embodiment, the bump 138 is formed on a UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 138 can also be crimped or hot pressed to the conductive layer 122. The bump 138 represents a type of interconnect structure that can be formed on the conductive layer 122. The interconnect structure may also use stud bumps, micro bumps, or other electrical interconnects.

[0020] The bumps 132 in the component attachment area 130 are arranged in an array, such as Figure 2c , to accommodate electrical components and make electrical interconnections with the electrical components. The bumps 132 in the component attachment area 130 have a height and width for accommodating electrical components and making electrical interconnections with the electrical components. In one embodiment, the bumps 132 have a height of 5-30 microns (μm) and a width of 20-120 μm above the surface 126, so that the manufacturing process can use one template and one SOP process for both the component attachment area 130 and the ground pad array 136a-136d. The bumps 138 on the ground pad array 136a-136d are arranged in a two-dimensional array, as shown in FIG. Figure 2c, to provide a ground connection for a shielding layer formed later. In particular, the two-dimensional array (X, Y) of bumps 138 on ground pad arrays 136a-136d has N1 number of bumps in the X direction and N2 number of bumps in the Y direction. For example, the two-dimensional array of bumps 138 on ground pad arrays 136a-136d can be a bump array with N1=4 and N2=3 or 4x3. Alternatively, the number of bumps 138 on ground pad arrays 136a-136d can be any value of N1 and N2.

[0021] The bump 138 on the ground pad array 136a-136d has a height and width for accommodating the shielding layer and making electrical interconnections with the shielding layer. In one embodiment, the bump 138 has the same height and width above the surface 126 as the bump 132, that is, a height of 5-30 μm and a width of 20-120 μm above the surface 126, so the manufacturing process can use a template and a SOP process for both the component attachment area 130 and the ground pad array 136a-136d. The process of making the bumps 132 and 138 the same height and width simplifies the process of forming the bumps on the surface 126 of the interconnect substrate 120. The bumps 132 and 138 can be formed simultaneously by the same steps using the same processing equipment, for example, the bumps 132 and 138 can be made with a printing template 140, which has a substrate having openings 141, 142 for each of the bumps 132 and 138, respectively. Figure 2d A printing template 140 is shown, wherein the opening 141 is Figure 2c The component attachment area 130 is aligned with the opening 142 Figure 2c The ground pad arrays 136a-136d in the printing template 140 are aligned. The bumps 132 and 138 can be formed simultaneously using the same equipment, that is, all the bumps are formed simultaneously through the openings 141 and 142 in the printing template 140. The process of forming the bumps 132 and 138 simultaneously reduces the manufacturing cost and simplifies the manufacturing process.

[0022] Figure 2e An alternative arrangement of ground pad arrays 136a-136d is shown on surface 126 around component attachment area 130. Bumps 132 and bumps 138 may be formed simultaneously using the same processing equipment and in the same steps, for example, bumps 132 and 138 may be made using one printing template 143 having a substrate with openings 144, 145 for each of bumps 132 and 138, respectively. Figure 2f A printing template 143 is shown, wherein the opening 144 is Figure 2e The component attachment area 130 is aligned with the opening 145. Figure 2eThe ground pad arrays 136a-136d in the printing template 143 are aligned. The bumps 132 and 138 can be formed simultaneously using the same equipment, that is, all the bumps are formed simultaneously through the openings 144 and 145 in the printing template 143. The process of forming the bumps 132 and 138 reduces the manufacturing cost and simplifies the manufacturing process.

[0023] exist Figure 2g In the embodiment, electrical components 146 are mounted to surface 126 of interconnect substrate 120 in component attachment area 130 and are electrically and mechanically connected to bumps 132 and conductive layer 122. Electrical components 146 are positioned on substrate 120 using a pick and place operation. For example, electrical components 146 may be from Figure 1c 1 , wherein active surface 110 is oriented toward surface 126 of substrate 120 over component attachment area 130. Alternatively, electrical components 146 may include other semiconductor dies, semiconductor packages, surface mount devices, discrete electrical devices or IPDs, such as resistors, capacitors, and inductors. Figure 2h An electrical component 146 is illustrated that is electrically and mechanically connected to the bumps 132 and the conductive layer 122 of the substrate 120. An underfill material 148, such as epoxy, is deposited beneath the electrical component 146.

[0024] The electrical components 146 may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components 146 provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 146 include digital circuits that switch at high frequencies, which may interfere with the operation of IPDs in adjacent packages or modules.

[0025] Figure 2iA package structure 150 is shown disposed on the interconnect substrate 120 and the electrical component 146. In one embodiment, the package structure 150 includes a material that operates as a heat sink or heat spreader to dissipate heat from the electrical component 146. In another embodiment, the package structure 150 includes a material that operates as an electromagnetic shielding layer to reduce or suppress EMI, RFI, and other inter-device interference. In yet another embodiment, the package structure 150 includes a material that operates as either or both of a heat sink and an electromagnetic shielding layer, i.e., a heat sink / shielding structure 150. The heat sink / shielding structure 150 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally and electrically conductive materials. Alternatively, the heat sink / shielding structure 150 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress the effects of heat and / or EMI, RFI, and other inter-device interference.

[0026] The heat sink / shield structure 150 includes a horizontal member 151 and legs 152 extending from the horizontal member on at least two sides. Alternatively, the legs 152 extend around the perimeter of the heat sink / shield structure 150 forming a cavity 154. Figure 2j A bottom view of the heat sink / shield structure 150, legs 152, and cavity 154 is shown. Figure 2i 136a-136d to cover the bumps 138. In one embodiment, the protective layer 156 is a conductive epoxy. A thermal interface material (TIM) 158 is deposited on the back surface 108 of the electrical component 146. The heat sink / shield structure 150 is positioned on the interconnect substrate 120 with the cavity 154 aligned with the electrical component 146 and the leg 152 aligned with the ground pad array 136a-136d.

[0027] Figure 2k A heat sink / shield structure 150 is shown mounted to an interconnect substrate 120, wherein an electrical component 146 is at least partially disposed within a cavity 154, and legs 152 are bonded to the surface 126 of the interconnect substrate 120 in an array of ground pads 136a-136d with an adhesive 156. The electrical component 146 dissipates heat and other thermal energy to the heat sink / shield structure 150 through a TIM 158. The heat sink / shield structure 150 is electrically connected to the conductive layer 122 of the interconnect structure through the legs 152 and the bumps 138 to provide a ground for a shielding function. The heat sink / shield structure 150 shunts charge to ground to reduce or suppress EMI, RFI, and other inter-device interference.

[0028] Conductive bump material is deposited on the conductive layer 122 on the surface 128 of the interconnect substrate 120 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 160. In one embodiment, the bump 160 is formed on a UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 160 can also be crimped or hot pressed to the conductive layer 122. The bump 160 represents a type of interconnect structure that can be formed on the conductive layer 122. The interconnect structure can also use bonding wires, conductive glues, stud bumps, micro bumps or other electrical interconnects.

[0029] Figure 3 A perspective view of a semiconductor package 162 is shown having heat dissipation and RFI / EMI shielding for an electrical component 146 in the form of a heat sink / shield structure 150. The heat sink / shield structure 150 is grounded by bumps 138 formed as a two-dimensional array in an array of ground pads 136a-136d. The bumps 138 can be made to have the same height and width as the bumps 132 used to provide electrical interconnection between the electrical component 146 and the interconnect substrate 120. Therefore, the bumps 132 and the bumps 138 can be formed simultaneously with the same processing equipment by the same steps, for example, all the bumps 132, 138 are formed through openings 141, 142 in a single printing template 140, or through openings 144, 145 in a single printing template 143. The array format for the bumps 132 and 138 allows for easy selection of the number of bumps and bump pads used for both grounding and die interconnection. The array of bumps 138 on the ground pad arrays 136a-136d reduces the chance of oxidation around and under the ground connections. The process of forming the bumps 132 and 138 both reduces manufacturing costs and simplifies the manufacturing process.

[0030] Figure 4 An electronic device 400 is illustrated having a chip carrier substrate or PCB 402 with multiple semiconductor packages, including semiconductor package 162, mounted on a surface of PCB 402. Electronic device 400 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0031] Electronic device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 400 may be a subcomponent of a larger system. For example, electronic device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, electronic device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. Semiconductor packages may include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and lightweighting are essential for making products accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0032] exist Figure 4 4, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on the surface or within layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0033] In some embodiments, the semiconductor device has two packaging levels. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging involves mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only the first level of packaging, where the die is mechanically and electrically mounted directly to the PCB.

[0034] For illustrative purposes, several types of first-level packages are shown on the PCB 402, including a wire bond package 406 and a flip chip 408. Additionally, several types of second-level packages are shown mounted on the PCB 402, including a ball grid array (BGA) 410, a bump chip carrier (BCC) 412, a land grid array (LGA) 416, a multi-chip module (MCM) or SIP module 418, a quad flat package (QFN) 420, a quad flat package 422, an embedded wafer-level ball grid array (eWLB) 424, and a wafer-level chip scale package (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer-level package (Fo-WLP), and the WLCSP 426 is a fan-in wafer-level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages configured in any combination of first and second level packaging styles and other electronic components can be connected to the PCB 402. In some embodiments, electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and simplified manufacturing processes. The resulting devices are less likely to fail and are less expensive to manufacture, resulting in lower costs for consumers.

[0035] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the invention as set forth in the following claims.

Claims

1. A method for forming a semiconductor device, comprising: providing a substrate; forming a conductive layer on the substrate; forming a plurality of first bumps on the conductive layer of the substrate; forming a plurality of M×N arrays of second bumps on the conductive layer of the substrate, wherein M>1 and N>1, and the first bumps and the second bumps are formed such that a distance between a first array of the plurality of M×N arrays of second bumps and a second array of the plurality of M×N arrays of second bumps is greater than a distance between a first one of the second bumps in the first array and a second one of the second bumps adjacent to the first one of the second bumps, and can be simultaneously formed by the same processing equipment and through the same steps; and A package structure is disposed on the substrate, wherein the package structure is coupled to the M×N array of second bumps.

2. The method according to claim 1, further comprising: An electrical component is disposed on the first bump. 3 . The method of claim 1 , wherein the package structure comprises a material that operates as a heat sink or a shielding layer. The method of claim 1 , wherein the first bump and the second bump have similar height and width.

5. A semiconductor device comprising: substrate; forming a conductive layer on the substrate; forming a plurality of first bumps on the conductive layer of the substrate; forming a plurality of M×N arrays of second bumps on the conductive layer of the substrate, wherein M>1 and N>1, and the first bumps and the second bumps are formed such that a distance between a first array of the plurality of M×N arrays of second bumps and a second array of the plurality of M×N arrays of second bumps is greater than a distance between a first one of the second bumps in the first array and a second one of the second bumps adjacent to the first one of the second bumps, and can be formed simultaneously by the same processing equipment and through the same steps; an electrical component disposed on the first bump; as well as A package structure is disposed on the substrate and the electrical component, wherein the package structure is coupled to the M×N array of second bumps. The semiconductor device according to claim 5 , wherein the plurality of first bumps are arranged in an array. 7 . The semiconductor device of claim 5 , wherein the package structure comprises a material that operates as a heat sink or a shielding layer. 8 . The semiconductor device according to claim 7 , wherein the shielding layer is grounded through an M×N array of second bumps. 9 . The semiconductor device according to claim 5 , wherein the first bump and the second bump have similar height and width.

10. A semiconductor device comprising: substrate; forming a conductive layer on the substrate; a plurality of first bumps formed on the conductive layer of the substrate; a plurality of M×N arrays of second bumps formed on the conductive layer of the substrate, wherein M>1 and N>1, and the first bumps and the second bumps are formed such that a distance between a first array of the plurality of M×N arrays of second bumps and a second array of the plurality of M×N arrays of second bumps is greater than a distance between a first one of the second bumps in the first array and a second one of the second bumps adjacent to the first one of the second bumps, and can be simultaneously formed by the same process using the same processing equipment and through the same steps; and A packaging structure is disposed on the substrate, wherein the packaging structure is electrically connected via an M×N array of second bumps. 11 . The semiconductor device according to claim 10 , further comprising an electrical component disposed on the first bump. 12 . The semiconductor device according to claim 10 , wherein the plurality of first bumps are arranged in an array.

13. The semiconductor device of claim 10, wherein the package structure comprises a material that operates as a heat sink or a shielding layer. 14 . The semiconductor device according to claim 13 , wherein the shielding layer is grounded through an M×N array of second bumps. 15 . The semiconductor device of claim 10 , further comprising a protection layer disposed on the M×N array of second bumps.

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