A trench gate semiconductor device and a manufacturing method thereof

Abstract

The embodiment of the present application provides a kind of trench gate semiconductor device and its manufacturing method, trench gate semiconductor device includes: first substrate layer, first doped region, second doped region, first conductive component, second conductive component, source electrode;It further includes two third doped regions, forms on the first substrate layer and corresponds to be located below second conductive component, the doping type of the third doped region is all second doped type, and the ratio of the sum of the amount of electric charge in two third doped regions and the amount of electric charge in the first substrate layer between them is 0.9-1.1.The semiconductor device provided by the present application improves the electric field distribution and improves the withstand voltage of the device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of power semiconductor devices, and particularly relates to a trench gate semiconductor device and a manufacturing method thereof. BACKGROUND

[0002] With the development of power electronic systems, power semiconductor devices, as the core of electric energy conversion and power applications, are widely used in important fields such as industrial control, power transmission, and new energy. As an important part of power semiconductor devices, power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) plays an important role in power conversion due to its fast switching speed, high input impedance, and small driving power. Power MOSFET has experienced development from lateral to vertical and from planar gate to trench gate. As one of the power MOSFETs, trench gate MOSFET, compared with planar gate MOSFET, has no parasitic JFET region and is very easy to integrate high-density cells with the progress of process technology, so it has lower on-resistance and is the mainstream structure of medium-low voltage and high-power MOS field effect tubes.

[0003] Unfortunately, in the existing trench gate MOSFET structure, when the device is reverse biased, the electric field at the corner of the gate trench is very concentrated and the gate oxide layer is relatively thin, so it is easy to cause the gate oxide layer to be damaged or broken down, thereby affecting the voltage withstand characteristics of the device, poor reliability, and easy to fail. SUMMARY

[0004] In view of this, the technical problem to be solved by the embodiments of the present application is to provide a trench gate semiconductor device and a manufacturing method thereof for the problem of easy breakdown of the gate oxide layer in the existing trench gate MOSFET, and the trench gate semiconductor device has good reliability performance.

[0005] The first aspect of the embodiments of the present application provides a trench gate semiconductor device, comprising:

[0006] a first substrate layer having a first doping type;

[0007] a first doped region having a second doping type formed above the first substrate layer;

[0008] a second doped region having the first doping type formed above a partial region of the first doped region;

[0009] a first conductive member extending from a surface of the first doped region into the first substrate layer, a first insulating layer being formed around the first conductive member to isolate the first conductive member from the first substrate layer, the first doped region, and the second doped region;

[0010] two second conductive members extending from the surface of the first doped region into the first substrate layer and located at opposite sides of the first conductive member, the lower surface of the second conductive member being lower than the lower surface of the first conductive member, the periphery of the second conductive member being formed with a second insulating layer to isolate the second conductive member from the first substrate layer and the first doped region;

[0011] a source electrode formed above the first doped region, the source electrode being in contact with the two second conductive members, the first doped region and the second doped region respectively, and the fourth insulating layer being provided between the source electrode and the first conductive member;

[0012] two third doped regions formed on the first substrate layer and located below the second conductive member respectively, the third doped regions being of the second doped type, and the ratio of the sum of the charge amount in the two third doped regions to the charge amount in the first substrate layer between the two third doped regions being in the range of 0.9-1.1.

[0013] Optionally, the third doped region comprises a plurality of first doped columns, the plurality of first doped columns being arranged in a longitudinal direction, and the doping concentration of adjacent two first doped columns being different or the same; or,

[0014] the third doped region comprises one first doped column.

[0015] Optionally, the doping concentration of the third doped region is greater than the doping concentration of the first substrate layer.

[0016] Optionally, the ratio of the difference between the doping concentration of the third doped region and the doping concentration of the first substrate layer to the doping concentration of the first substrate layer is in the range of 1%-10%.

[0017] Optionally, the doping concentration of the two third doped regions is equal, and the ratio of the difference between the doping concentration of the third doped region and the doping concentration of the first substrate layer to the doping concentration of the first substrate layer is less than or equal to 5%.

[0018] Optionally, the semiconductor device further comprises a fifth doped region formed below the first conductive member, the fifth doped region being of the second doped type.

[0019] Optionally, the first substrate layer comprises a first sub-substrate layer and a second sub-substrate layer, the second sub-substrate layer being formed above the first sub-substrate layer, and the upper surface of the first sub-substrate layer being flush with the upper surface of the third doped region.

[0020] Optionally, the semiconductor device further comprises a second substrate layer having a first doping type, and the first substrate layer is formed above the second substrate layer, and the doping concentration of the second substrate layer is greater than that of the first substrate layer; or

[0021] The thickness of the second insulating layer is greater than that of the first insulating layer; or

[0022] The sum of the charge amounts in the two third doping regions is equal to the charge amount in the first substrate layer between the two third doping regions; or

[0023] The first doping type is one of an N-type doping type and a P-type doping type, and the second doping type is the other doping type.

[0024] The second aspect of the embodiments of the present application provides a manufacturing method of a trench gate semiconductor device, comprising:

[0025] Forming two first protection trenches on a first substrate layer having a first doping type;

[0026] Doping at the bottom of the two first protection trenches to obtain two third doping regions having a second doping type, wherein the ratio of the sum of the charge amounts in the two third doping regions to the charge amount in the first substrate layer between the two third doping regions ranges from 0.9 to 1.1;

[0027] Forming a second insulating layer on the inner wall of each of the two first protection trenches;

[0028] Forming a second conductive member in the second insulating layer;

[0029] Forming a gate trench in the first substrate layer between the two second conductive members, and the depth of the gate trench is less than that of the first protection trench;

[0030] Forming a first insulating layer on the inner wall of the gate trench;

[0031] Forming a first conductive member in the first insulating layer;

[0032] Doping on the first substrate layer between the first conductive member and the second conductive member to obtain a first doping region having a second doping type, and the depth of the first doping region is less than that of the gate trench;

[0033] Doping on part of the first doping region to obtain a second doping region having a first doping type;

[0034] Forming a fourth insulating layer above the first conductive member;

[0035] forming a source electrode in contact with the second conductive member, the first doped region and the second doped region respectively.

[0036] Optionally, before the step of forming the first insulating layer on the inner wall of the gate trench, the method further comprises:

[0037] doping the bottom of the gate trench to obtain a fifth doped region having the second doping type.

[0038] Optionally, before the step of forming the source electrode, the method further comprises:

[0039] forming a contact hole on the fourth insulating layer, the contact hole being used to contact the source electrode with the second conductive member.

[0040] Optionally, before the step of forming two first protection trenches on the first substrate layer having the first doping type, the method further comprises:

[0041] forming the first substrate layer above the second substrate layer, the doping concentration of the second substrate layer being greater than that of the first substrate layer.

[0042] The third aspect of the embodiments of the present application provides a manufacturing method of a trench gate semiconductor device, comprising:

[0043] doping the first sub-substrate layer having the first doping type to obtain two third doped regions having the second doping type, wherein the ratio of the sum of the amount of charges in the two third doped regions to the amount of charges in the first sub-substrate layer between the two third doped regions ranges from 0.9 to 1.1;

[0044] forming a second sub-substrate layer having the first doping type above the first sub-substrate layer;

[0045] removing part of the second sub-substrate layer to form two first protection trenches, the two first protection trenches corresponding to being above the two third doped regions, and the third doped regions being exposed through the first protection trenches;

[0046] correspondingly forming a second insulating layer on the inner wall of the two first protection trenches;

[0047] correspondingly forming a second conductive member in the two second insulating layers;

[0048] forming a gate trench in the second sub-substrate layer between the two second conductive members, the depth of the gate trench being less than the depth of the first protection trench;

[0049] forming a first insulating layer on the inner wall of the gate trench;

[0050] forming a first conductive member in the first insulating layer;

[0051] doping is performed on the second sub-substrate layer between the first conductive member and the second conductive member to obtain a first doped region having a second doping type, the depth of the first doped region being less than the depth of the gate trench;

[0052] doping is performed on a partial region of the first doped region to obtain a second doped region having a first doping type;

[0053] a fourth insulating layer is formed above the first conductive member;

[0054] a source electrode is formed, which is in contact with the second conductive member, the first doped region and the second doped region respectively.

[0055] The semiconductor device provided by the application embodiment has the beneficial effect that two second conductive members deeper than the first conductive member are added in the trench gate semiconductor device, and a third doped region is formed below the two second conductive members. The addition of the second conductive member forms an electric field field plate effect in the longitudinal direction and the first doped region, which can effectively smooth the electric field and increase the withstand voltage. Moreover, the first substrate layer between the two third doped regions and the third doped region form a lateral PN junction, which increases the lateral depletion and further improves the electric field distribution, avoids the premature breakdown of the gate oxide layer, and improves the withstand voltage of the device. BRIEF DESCRIPTION OF DRAWINGS

[0056] In order to more clearly illustrate the technical solutions in the application embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0057] Figure 1 is a cross-sectional structure schematic diagram of a trench gate semiconductor device provided by the application embodiment;

[0058] Figure 2 is an electric field distribution curve diagram of the trench gate semiconductor device provided by the application embodiment when the device is reverse biased;

[0059] Figure 3 is a cross-sectional structure schematic diagram of another trench gate semiconductor device provided by the application embodiment;

[0060] Figure 4a is a cross-sectional structure schematic diagram of a semiconductor device corresponding to one step of a trench gate semiconductor device manufacturing method provided by the application embodiment;

[0061] Figure 4b is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of a trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0062] Figure 4c is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of a trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0063] Figure 4d is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of a trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0064] Figure 4e is a flow chart of a trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0065] Figure 5a is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of another trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0066] Figure 5b is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of another trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0067] Figure 5c is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of another trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0068] Figure 5d is a schematic diagram of a cross-sectional structure of a semiconductor device corresponding to one step of another trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure;

[0069] Figure 5e is a flow chart of another trench gate semiconductor device manufacturing method provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work fall within the scope of protection of the present application.

[0071] The terms "comprise", "comprising", "include", "including", "have" and "having" and any variations thereof in the specification and throughout the claims are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or apparatus that comprises a list of steps or units is not necessarily limited to the listed steps or units, but can optionally include additional steps or units not expressly listed or can also include steps or units inherent to such process, method, product or apparatus. In addition, the terms "first", "second" and "third" and the like are used to distinguish different objects, not to describe a particular order. The connection in the present application includes direct connection and indirect connection, and the indirect connection means that there can be other electronic components, pins and the like between the two connected components. The XX terminal mentioned in the present application may or may not be an actually existing terminal, for example, it may be only one end of a component or one end of a wire. The present application refers to and / or includes three cases, for example, A and / or B, including A, B, A and B.

[0072] The embodiment of the present disclosure provides a trench gate semiconductor device 10, the trench semiconductor device 10 is a power MOSFET, in order to facilitate understanding, the following will be combined with Figures 1-3 The trench gate semiconductor device 10 is described in detail.

[0073] As Figure 1As shown, the trench gate semiconductor device 10 comprises: a first substrate layer 11 having a first doping type; a first doped region 12 having a second doping type formed above the first substrate layer 11, wherein the number of the first doped region 12 is two; a second doped region 13 having the first doping type formed above a partial region of the first doped region 12, wherein there is one second doped region 13 in each first doped region 12; a first conductive member 16 extending from the surface of the first doped region 12 into the first substrate layer 11, the periphery of the first conductive member 16 is formed with a first insulating layer 151 to isolate the first conductive member 16 from the first substrate layer 11, the first doped region 12 and the second doped region 13, the first conductive member 16 is a gate, the first insulating layer 151 is in a U shape in the figure, wherein the first conductive member 16 is located between the two second doped regions 13, and the two second doped regions 13 are located between the two first doped regions 12. Two second conductive members 20 extending from the surface of the first doped region 12 into the first substrate layer 11 and located on the opposite sides of the first conductive member 16, one of which is located on the left side of the first conductive member 16 and the other is located on the right side of the first conductive member 16 in the figure, the lower surface of the second conductive member 20 is lower than the lower surface of the first conductive member 16, and the periphery of the second conductive member 20 is formed with a second insulating layer 19 to isolate the second conductive member 20 from the first substrate layer 11 and the first doped region 12, wherein the second insulating layer 19 is also in a U shape (part of the second insulating layer is not shown in the figure). A source electrode 23 is formed above the first doped region 12, the second conductive member 20, the second doped region 13 and the first conductive member 16, the source electrode 23 is in contact with the two second conductive members 20, the first doped region 12 and the second doped region 13 respectively, and a fourth insulating layer 152 is provided between the source electrode 23 and the first conductive member 16.

[0074] The trench gate semiconductor device 10 further comprises two third doped regions 24 formed on the first substrate layer 11 and located below the second conductive member 20, the doping type of the third doped region 24 is the second doping type, and the ratio of the sum of the charge amount in the two third doped regions 24 to the charge amount in the first substrate layer 11 between the two third doped regions 24 (the region of the first substrate layer 11 between the two dashed lines in the figure) ranges from 0.9 to 1.1, for example, the ratio is 0.9, 0.95, 0.98, 1, 1.02, 1.05, 1.1, etc., preferably, the sum of the charge amount in the two third doped regions 24 is equal to the charge amount in the first substrate layer 11 between the two third doped regions 24, which can better form a lateral depletion. Figure 1

[0075] ​The first insulating layer 151, the second insulating layer 19 and the fourth insulating layer 152 can be oxide layers or nitride layers, and more specifically, the oxide layers can be silicon dioxide layers. The first conductive member 16 and the second conductive member 20 can be polysilicon, but the present disclosure is not limited thereto, one or more of the first conductive member 16 and the second conductive member 20 can also be conductive members such as Si, metal and the like which can be easily deduced according to the present embodiment, and one or more of the first insulating layer 15, the second insulating layer 19 and the fourth insulating layer 152 can also be other insulating layers which can be easily deduced according to the present embodiment.

[0076] As to the beneficial effects of the trench gate semiconductor device 10, as shown in Figure 2 The electric field distribution curve reflects the distribution of the electric field intensity in the longitudinal direction from the first doped region 12 to the first substrate layer 11. Since the trench gate semiconductor device 10 is provided with the deeper second conductive member 20, when the trench gate semiconductor device 10 is reverse biased, a PN junction is formed at the interface between the first substrate layer 11 and the first doped region 12, which increases the longitudinal depletion, and the increase of the second conductive member 20 forms an electric field field plate effect in the longitudinal direction and the first doped region 12, which can effectively smooth the electric field and increase the withstand voltage (see the curve corresponding to the provision of the second conductive member). In addition, the first substrate layer 11 between the two third doped regions 24 forms a lateral PN junction with the third doped region 24, which increases the lateral depletion, improves the electric field distribution according to the charge balance principle, and shifts the strong electric field originally located at the corner of the first conductive member 16 to the bottom of the first conductive member 16, thereby avoiding premature breakdown of the insulating layer and improving the withstand voltage of the device (see the curve corresponding to the provision of the third doped region). Figure 2 As shown in Figure 2 As shown in

[0077] It is worth mentioning that, due to the improved electric field distribution is more concentrated at the bottom of the second conductive member 20, it is preferred that the thickness of the second insulating layer 19 is greater than the thickness of the first insulating layer 151, and the thickness of the second insulating layer 19 is set to be relatively large, for example, 1000A-2000A, to avoid breakdown, further improving the reliability of the device.

[0078] Specifically, as a preferred example of the structure of the trench gate semiconductor device 10 described above, continue as Figure 1 As shown, the third doped region 24 includes a plurality of first doped columns 241, and of course can only include one first doped column 241. In this embodiment, a plurality of first doped columns are arranged in the longitudinal direction, and the doping concentrations of adjacent two first doped columns are different; in other embodiments of the present application, the doping concentrations of adjacent two first doped columns can also be the same. Continue as Figure 1 As shown, the third doped region 24 has 3 first doped columns 241, the first first doped column 241 and the second first doped column 241 have different concentrations, and the second first doped column 241 and the third first doped column 241 have different concentrations. In this embodiment, Figure 1 The third doped region 24 on the left side in the figure and the third doped region 24 on the right side can be completely the same or have some differences. The trench gate semiconductor device 10 in this embodiment has the beneficial effect that, since the third doped region 24 includes a plurality of first doped columns 241, by adjusting the doping concentrations of the plurality of first doped columns 241, the sum of the electric charges in the two third doped regions 24 can be equal to or close to the electric charge in the first substrate layer 11 located between the two third doped regions 24, which can greatly simplify the process and reduce the difficulty.

[0079] In this embodiment, as a preferred example of the structure of the trench gate semiconductor device 10 described above, the doping concentration of the third doped region 24 is greater than the doping concentration of the first substrate layer 11, which can make up for the fact that the area of the two third doped regions 24 is smaller than the area of the first substrate layer 11 between the two third doped regions 24 Figure 1The doping concentration of the third doped region 24 can be calculated as follows. If the doping concentration of each region in the third doped region 24 (e.g. any one of the first doped columns 241) is equal, the doping concentration of the third doped region 24 is equal to the doping concentration of any one of the regions. If there are multiple regions in the third doped region 24 with different doping concentrations, e.g. different first doped columns 241 have different doping concentrations, the doping concentration of the third doped region 24 is equal to the average of the doping concentrations of all the first doped columns 241. The trench gate semiconductor device 10 of the present embodiment has the advantage that, since the doping concentration of the third doped region 24 is greater than the doping concentration of the first substrate layer 11, by adjusting the doping concentration of the third doped region 24, the sum of the amount of electric charges in the two third doped regions 24 can be more easily equal to the amount of electric charges in the first substrate layer 11 located between the two third doped regions 24, and according to the principle of charge balance, the withstand voltage of the device can be significantly improved.

[0080] Preferably, the ratio of the difference between the doping concentration of the third doped region 24 and the doping concentration of the first substrate layer 11 to the doping concentration of the first substrate layer 11 is between 1% and 10%, e.g. 1%, 2%, 3%, 4%, 5%, 6%, 7%, 8%, 9%, 10%, etc. With the concentration difference in this range, a better withstand voltage of the device can be obtained.

[0081] Preferably, the doping concentrations of the two third doped regions 24 are equal, and the ratio of the difference between the doping concentration of the third doped region 24 and the doping concentration of the first substrate layer 11 to the doping concentration of the first substrate layer 11 is less than or equal to 5%, e.g. 1%, 2%, 3%, 4%, 5%. With the concentration difference in this range, a better withstand voltage of the device can be obtained.

[0082] Specifically, as a better example of the structure of the trench gate semiconductor device 10 described above, as shown in FIG. 1, the semiconductor device 10 further comprises a third doped region 24, the third doped region 24 is formed below the first conductive member 16, the third doped region 24 and the first conductive member 16 are separated by a first insulating layer 151, and the doping type of the third doped region 24 is the same as that of the first doped region 21. Figure 1 The semiconductor device 10 of the present embodiment has the advantage that the third doped region 24 formed below the first conductive member 16 can further protect the first insulating layer 151 from strong electric field attack.

[0083] In another embodiment of the present application, as a better example of the structure of the trench gate semiconductor device 10 described above, as shown in FIG. 1, the semiconductor device 10 further comprises a third doped region 24, the third doped region 24 is formed below the first conductive member 16, the third doped region 24 and the first conductive member 16 are separated by a first insulating layer 151, and the doping type of the third doped region 24 is the same as that of the first doped region 21. Figure 3As shown, the first substrate layer 11 includes a first sub-substrate layer 111 and a second sub-substrate layer 112, the second sub-substrate layer 112 is formed above the first sub-substrate layer 111, and the upper surface of the first sub-substrate layer 111 is flush with the upper surface of the third doped region 24. The trench gate semiconductor device 10 in this embodiment has the advantage that by forming the first substrate layer 11 in layers, the third doped layer 24 can be formed without high-energy implantation, improving process yield and saving energy. It should be noted that, to further simplify the process, the doping concentration of the first sub-substrate layer 111 and the second sub-substrate layer 112 can be set to be the same.

[0084] In this embodiment, as an example of the structure of the trench gate semiconductor device 10 described above, the fourth insulating layer 152 is also formed on the surface of the second conductive member 20, and a contact hole is formed on the surface of the fourth insulating layer 152 to enable the source electrode 23 to be electrically connected to the second conductive member 20. In the illustration, the contact hole also exposes the first doped region 12 and the second doped region 13, so that the source electrode 23 can also be electrically connected to the first doped region 12 and the second doped region 13.

[0085] Specifically, as an example of the trench gate semiconductor device 10 described above, the doping concentration of the first doped region 12 and the second doped region 13 is higher than the doping concentration of the first substrate layer.

[0086] As an example, the material of the first substrate layer 11 described above can be Si, silicon carbide or other substrate material. It can be understood that the lower surface of the first substrate layer 11 is used to contact the drain electrode to form a MOSFET device.

[0087] It should be noted that, as a variant of the structure of the trench gate semiconductor device 10 described above, as shown in Figure 1 and Figure 3 As shown, the trench gate semiconductor device 10 also includes a second substrate layer 27 having a first doping type, the first substrate layer 11 is formed above the second substrate layer 27, and the doping concentration of the second substrate layer 27 is higher than the doping concentration of the first substrate layer 11. Specifically, the first substrate layer 11 can be formed based on the epitaxy of the second substrate layer 27, i.e. the first substrate layer 11 is an epitaxial layer of the second substrate layer 27, and the first substrate layer 11 and the second substrate layer 27 are respectively called epi layer and sub layer. The formation of the epitaxial layer is beneficial to ensure the withstand voltage of the device while further reducing the on-resistance of the device.

[0088] Specifically, the material of the second substrate layer 27 described above can also be Si, silicon carbide or other substrate material. It can be understood that under this structure, the lower surface of the second substrate layer 27 will be used to contact the drain electrode to form a MOSFET device.

[0089] Specifically, asFigure 1 and Figure 3 As shown, the first doping type and the second doping type are N-type doping type and P-type doping type, respectively. N-type doping involves doping with pentavalent elements, such as nitrogen (N), phosphorus (P), arsenic (As), and antimony (Sb); P-type doping involves doping with trivalent elements, such as boron (B) and aluminum (Al). However, this disclosure is not limited to this. As another embodiment of this disclosure, the first doping type and the second doping type can also be P-type doping type and N-type doping type, respectively.

[0090] This disclosure also provides a method for manufacturing a trench gate semiconductor device. For ease of understanding, the following describes the method in conjunction with... Figure 1 , Figure 3 , Figures 4a-4e The method will be explained in detail.

[0091] The method for manufacturing this trench gate semiconductor device includes the following steps:

[0092] S101: Two first protective trenches 17 are formed on the first substrate layer 11 having a first doping type.

[0093] S102: Doping is performed at the bottom of the two first protective trenches 17 to obtain two third doped regions 24 with a second doping type, wherein the ratio of the sum of the charges in the two third doped regions 24 to the charge in the first substrate layer 11 located between them is in the range of 0.9-1.1.

[0094] Specifically, such as Figure 4a As shown, the specific operations of steps S101-S102 are as follows: the first N-type substrate layer 11 is blocked with photoresist, and after development and opening of the window, two first protective trenches 17 are etched to obtain the first protective trenches 17. The depth of the first protective trenches 17 is, for example, 1.8um-3.0um. Then the photoresist is cleaned, and then the bottom of the first protective trenches 17 is subjected to 3-5 high-energy (e.g., 1MV) boron implantation, thereby forming a third doped region 24 at the bottom of the two first protective trenches 17 respectively.

[0095] Preferably, since the first protective trench 17 is relatively deep, in order to prevent damage to the photoresist during etching, an oxide layer of about 5000 Å can be deposited before coating the photoresist, and then the oxide layer is covered by the photoresist. After developing and opening the window, the oxide layer at the window is etched, and the etching continues to obtain the first protective trench 17. Then the photoresist and the oxide layer are cleaned before proceeding with the subsequent steps.

[0096] S103: A second insulating layer 19 is formed on the inner wall of each of the two first protective trenches 17.

[0097] S104: forming a second conductive member 20 in the second insulating layer 19, wherein the second conductive member 20 fills up the first protective trench 17.

[0098] Specifically, as shown in FIG. 3, the specific operations of steps S103-S104 are, for example, thermally and oxidatively growing or depositing an oxide layer (i.e., forming the second insulating layer 19, in the shape of a U) of, for example, 1000A-2000A on the inner walls of the two first protective trenches 17; and then depositing polysilicon in the oxide layer and etching back to flush with the upper surface of the first substrate layer 11 (i.e., forming the two second conductive members 20). Figure 4b

[0099] S105: forming a gate trench 14 in the first substrate layer 11 between the two first protective trenches 17, the depth of the gate trench 14 being less than the depth of the first protective trench 17.

[0100] S106: forming a first insulating layer 151 on the inner walls of the gate trench 14, the first insulating layer 151 being in the shape of a U.

[0101] S107: forming a first conductive member 16 in the first insulating layer 151.

[0102] Specifically, as shown in FIG. 3, the specific operations of steps S105-S107 are, for example, shielding the first substrate layer 11 with a photoresist, etching to obtain the gate trench 14 after developing the window, the depth of the trench being, for example, about 1.2um-1.5um, and then cleaning the photoresist, followed by thermally and oxidatively growing an oxide layer (i.e., the first insulating layer 151) of 200-600A; depositing polysilicon (i.e., the first conductive member 16) in the first insulating layer 151 and etching back to flush with the upper surface of the first substrate layer 11, i.e., filling up the gate trench 14. Figure 4c

[0103] S108: doping the first substrate layer 11 between the first conductive member 16 and the second conductive member 20 to obtain a first doped region 12 having a second doping type, the depth of the first doped region 12 being less than the depth of the gate trench 14.

[0104] S109: doping a partial region of the first doped region 12 to obtain a second doped region 13 having a first doping type.

[0105] S110: forming a fourth insulating layer 152 above the first conductive member 16;

[0106] S111: forming a source electrode 23, the source electrode 23 being in contact with the second conductive member 20, the first doped region 12, and the second doped region 13, respectively.

[0107] Specifically, as shown in FIG. 3, the specific operations of steps S105-S107 are, for example, shielding the first substrate layer 11 with a photoresist, etching to obtain the gate trench 14 after developing the window, the depth of the trench being, for example, about 1.2um-1.5um, and then cleaning the photoresist, followed by thermally and oxidatively growing an oxide layer (i.e., the first insulating layer 151) of 200-600A; depositing polysilicon (i.e., the first conductive member 16) in the first insulating layer 151 and etching back to flush with the upper surface of the first substrate layer 11, i.e., filling up the gate trench 14. Figure 4d ​​As shown, the specific operations of step S108-step S110 are, for example, Pwell implantation, P+ implantation, N+ implantation are completed according to conventional manufacturing procedures to form the first doped region 12 and the second doped region 13, the fourth insulating layer 152 is formed, and the deposition and etching of the source electrode metal layer are completed to form the source electrode 23.

[0108] The semiconductor device manufacturing method provided by the present disclosure has the beneficial effects that: by setting the first protection groove 17 deeper than the gate groove 14, and forming the third doped region 24 at the bottom of the first protection groove 17, a PN junction is formed at the interface between the first substrate layer 11 and the first doped region 12 between the two first protection grooves 17, the longitudinal depletion is increased, and a lateral PN junction is formed in the first substrate layer between the two third doped regions 24, the lateral depletion is increased, thereby improving the electric field distribution, avoiding premature breakdown of the insulating layer, improving the withstand voltage of the device, and at the same time, the manufacturing process is simpler through high-energy implantation.

[0109] Specifically, as one of the better examples of the trench gate semiconductor device manufacturing method, the method further includes, before step S106:

[0110] The bottom of the gate groove 14 is doped to obtain a fifth doped region 26 having a second doping type. Specifically, as shown in Figure 4c That is, before the first insulating layer 151 is formed, boron implantation is performed at the bottom of the gate groove 14 to form the fifth doped region 26. It is worth mentioning that the fifth doped region 26 formed under the gate groove 14 can further protect the gate oxide layer from strong electric field attack.

[0111] Specifically, as one of the better examples of the trench gate semiconductor device manufacturing method, the method further includes, before step S111:

[0112] A contact hole contact is formed on the fourth insulating layer 152, and the contact hole contact is used to contact the source electrode 23 with the second conductive member 20. Specifically, as shown in Figure 4d That is, before the deposition and etching of the source electrode metal layer are performed, etching is performed on the fourth insulating layer 152 respectively to form the contact hole contact.

[0113] Specifically, as one of the better examples of the trench gate semiconductor device manufacturing method 100, the method further includes, before step S101:

[0114] The first substrate layer 11 is formed above the second substrate layer 27, and the doping concentration of the second substrate layer 27 is greater than that of the first substrate layer 11. Specifically, as shown in Figures 4a-4dAs shown, the first substrate layer 11 with a lower doping concentration is obtained by epitaxial growth on the N-type second substrate layer 27. It is worth mentioning that the formation of the epitaxial layer is conducive to ensuring the device withstand voltage while further reducing the on-resistance of the device.

[0115] The embodiments of the present disclosure further provide a manufacturing method of a trench gate semiconductor device. For ease of understanding, the following will be combined with Figure 1 、 Figure 3 、 Figures 5a-5e The circuit is described in detail.

[0116] It should be noted that the manufacturing method of the trench gate semiconductor device provided by the embodiments belongs to the same concept as the manufacturing method of the semiconductor device provided by the above embodiments. Those skilled in the art should understand that the specific circuit structure, implementation process, and technical details in the embodiments can be correspondingly applied to the manufacturing method embodiments, and the repeated parts will not be described again.

[0117] The manufacturing method comprises the following steps:

[0118] S201: Doping is performed on the first sub-substrate layer 111 with a first doping type to obtain two third doped regions 24 with a second doping type, wherein the ratio of the sum of the charge amount in the two third doped regions 24 to the charge amount in the first sub-substrate layer 111 located between the two third doped regions 24 ranges from 0.9 to 1.1.

[0119] Specifically, as shown in Figures 5a-5b , the specific operation of step S201 is, for example, shielding the first sub-substrate layer 111 with photoresist, opening a window, and performing, for example, boron implantation on the N-type first sub-substrate layer 111. After implantation is completed, the photoresist is removed to obtain the two third doped regions 24.

[0120] S202: Forming a second sub-substrate layer 112 with a first doping type above the first sub-substrate layer 111.

[0121] Specifically, as shown in Figure 5c , the specific operation of step S202 is, for example, growing the second sub-substrate layer 112 above the N-type first sub-substrate layer 111 by thermal oxidation growth. Preferably, to further simplify the process, the doping concentration of the second sub-substrate layer 112 and the doping concentration of the first sub-substrate layer 111 can be set to be the same.

[0122] S203: Removing part of the second sub-substrate layer 112 to form two first protection trenches 17, the two first protection trenches 17 correspond to being located above the two third doped regions 24, and the third doped regions 24 are exposed through the first protection trenches 17.

[0123] Specifically, as shown in Figure 5dAs shown, the specific operation of step S203 is, for example, shielding the second sub-substrate layer 112 with photoresist, etching to remove part of the second sub-substrate layer 112 after developing the window to obtain two first protective trenches 17, the depth of the first protective trenches 17 is, for example, 1.8-3.0 um, and the first protective trenches 17 reach the position of the third doped region 24, and then the photoresist is cleaned.

[0124] Preferably, due to the deep depth of the first protective trenches 17, to prevent damage to the photoresist during etching, a layer of about 5000A of oxide layer can be deposited before the photoresist is applied, then the oxide layer is shielded with photoresist, the oxide layer at the window is etched after developing the window, and two first protective trenches 17 are etched, then the photoresist and the oxide layer are cleaned, and then the subsequent steps are performed.

[0125] S204: Corresponding second insulating layers 19 are formed on the inner walls of the two first protective trenches 17.

[0126] S205: Corresponding second conductive members 20 are formed in the two second insulating layers 19, and the second conductive members 20 fill the first protective trenches 17.

[0127] S206: A gate trench 14 is formed in the second sub-substrate layer 112 between the two second conductive members 20, and the depth of the gate trench 14 is less than the depth of the first protective trenches 17.

[0128] S207: A first insulating layer 151 is formed on the inner wall of the gate trench 14.

[0129] S208: A first conductive member 16 is formed in the first insulating layer 151.

[0130] S209: Doping is performed on the second sub-substrate layer 112 between the first conductive member 16 and the second conductive member 20 to obtain a first doped region 12 having a second doping type, and the depth of the first doped region 12 is less than the depth of the gate trench 14.

[0131] S210: Doping is performed on part of the first doped region 12 to obtain a second doped region 13 having a first doping type.

[0132] S211: A fourth insulating layer 152 is formed above the first conductive member 16.

[0133] S212: A source electrode 23 is formed, which respectively contacts the second conductive member 20, the first doped region 12 and the second doped region 13.

[0134] It should be noted that the actual operation of steps S204-S212 is exactly the same as the steps corresponding to steps S103-S111 in the previous manufacturing method, and will not be elaborated here.

[0135] The trench gate semiconductor device manufacturing method provided in this disclosure has the advantage of being superior to the above-mentioned manufacturing methods in that, since a substrate layer growth method is used, only low-energy implantation at the KV level is required to obtain two third doped regions 24, thereby avoiding the formation of the third doped layer 24 through high-energy implantation, improving process yield and saving energy.

[0136] It should be noted that the number of doped pillars contained in the third doped region 24 is not limited to one, and the number of corresponding second sub-substrate layers 112 is not limited to one. When the number of doped pillars contained in the third doped region 24 is multiple, the manufacturing can be achieved by repeating the above steps S201 and S202. The actual operation is basically the same, and will not be described in detail here.

[0137] It should be noted that the trench gate semiconductor device manufacturing method provided in this embodiment belongs to the same concept as the trench gate semiconductor device and the trench gate semiconductor device manufacturing method provided in the above embodiments. Those skilled in the art should understand that the specific circuit structure, implementation process, and technical details in the embodiments can be applied to the embodiments of the manufacturing method, and repeated details will not be repeated. It should also be noted that the process steps of the aforementioned trench gate semiconductor device manufacturing method are not limited to the above order. In some alternative implementations, the functions marked in the boxes in the flowchart may occur in a different order than those marked in the figures. For example, two consecutively indicated boxes can actually be executed in essentially parallel order, and they can sometimes be executed in reverse order, depending on the functions involved.

[0138] It should be understood that "a plurality of" as used herein refers to two or more. Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0139] It should be noted that each of the embodiments of the present specification is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between embodiments can be mutually referred to.

[0140] The above disclosure is only the preferred embodiment of the present application, and of course cannot limit the scope of the right of the present application. Therefore, the equivalent changes made according to the claims of the present application are still within the scope of the present application.

Claims

1. A trench gate semiconductor device, characterized in that, include: A first substrate layer having a first doping type; A first doped region having a second doping type is formed above the first substrate layer; A second doped region having a first doping type is formed above a portion of the first doped region; A first conductive component extends from the surface of the first doped region into the first substrate layer, and a first insulating layer is formed around the first conductive component to isolate the first conductive component from the first substrate layer, the first doped region, and the second doped region. Two second conductive members extend from the surface of the first doped region into the first substrate layer and are located on opposite sides of the first conductive member. The lower surface of the second conductive member is lower than the lower surface of the first conductive member. A second insulating layer is formed around the second conductive member to isolate the second conductive member from the first substrate layer and the first doped region. A source electrode is formed above the first doped region. The source electrode is in contact with two second conductive components, the first doped region, and the second doped region, respectively. A fourth insulating layer is provided between the source electrode and the first conductive component. Two third doped regions are formed on the first substrate layer and are located below the second conductive member. The doping type of the third doped regions is the second doping type, and the ratio of the sum of the charges in the two third doped regions to the charge in the first substrate layer located between them is in the range of 0.9-1.

1.

2. The trench gate semiconductor device according to claim 1, characterized in that, The third doped region includes a plurality of first doped pillars, which are arranged longitudinally, and the doping concentrations of two adjacent first doped pillars are different or the same; or, The third doped region includes a first doped pillar.

3. The trench gate semiconductor device according to claim 1, characterized in that, The doping concentration of the third doped region is greater than that of the first substrate layer.

4. The semiconductor device according to claim 3, characterized in that, The ratio of the difference between the doping concentration of the third doped region and the doping concentration of the first substrate layer to the doping concentration of the first substrate layer ranges from 1% to 10%.

5. The trench gate semiconductor device according to claim 4, characterized in that, The doping concentrations of the two third doped regions are equal, and the ratio of the difference between the doping concentration of the third doped region and the doping concentration of the first substrate layer to the doping concentration of the first substrate layer is less than or equal to 5%.

6. The trench gate semiconductor device according to any one of claims 1-5, characterized in that, The semiconductor device further includes a fifth doped region, which is formed below the first conductive member, and the doping type of the fifth doped region is all of the second doping type.

7. The trench gate semiconductor device according to any one of claims 1-5, characterized in that, The first substrate layer includes a first sub-substrate layer and a second sub-substrate layer, the second sub-substrate layer being formed above the first sub-substrate layer, and the upper surface of the first sub-substrate layer being flush with the upper surface of the third doped region.

8. The trench gate semiconductor device according to any one of claims 1-5, characterized in that, The semiconductor device further includes a second substrate layer having a first doping type, the first substrate layer being formed above the second substrate layer, and the doping concentration of the second substrate layer being greater than that of the first substrate layer; or... The thickness of the second insulating layer is greater than the thickness of the first insulating layer; or, The sum of the charges in the two third doped regions is equal to the charge in the first substrate layer located between them; or, The first doping type is either N-type or P-type, and the second doping type is the other doping type.

9. A method for manufacturing a trench gate semiconductor device, characterized in that, include: Two first protective trenches are formed on a first substrate layer having a first doping type; Doping is performed at the bottom of the two first protective trenches to obtain two third doped regions with a second doping type, wherein the ratio of the sum of the charges in the two third doped regions to the charge in the first substrate layer located between them is in the range of 0.9-1.

1. A second insulating layer is formed on the inner wall of each of the two first protective trenches; A second conductive component is formed within the second insulating layer; A gate trench is formed in a first substrate layer between the two second conductive members, the depth of the gate trench being less than the depth of the first protective trench; A first insulating layer is formed on the inner wall of the gate trench; A first conductive component is formed within the first insulating layer; The first substrate layer between the first conductive member and the second conductive member is doped to obtain a first doped region with a second doping type, wherein the depth of the first doped region is less than the depth of the gate trench. Doping is performed on a portion of the first doped region to obtain a second doped region having the first doping type; A fourth insulating layer is formed above the first conductive component; A source electrode is formed, which is in contact with the second conductive component, the first doped region, and the second doped region, respectively.

10. The method for manufacturing a trench gate semiconductor device according to claim 9, characterized in that, Before forming the first insulating layer on the inner wall of the gate trench, the method further includes: The bottom of the gate trench is doped to obtain a fifth doped region with a second doping type.

11. The method for manufacturing a trench gate semiconductor device according to claim 9, characterized in that, Before the formation of the source electrode, the process also includes: A contact hole is formed on the fourth insulating layer, the contact hole being used to make the source electrode contact the second conductive member.

12. The method for manufacturing a trench gate semiconductor device according to any one of claims 9-11, characterized in that, Before forming two first protective trenches on a first substrate layer having a first doping type, the method further includes: A first substrate layer is formed on top of a second substrate layer, wherein the doping concentration of the second substrate layer is greater than that of the first substrate layer.

13. A method for manufacturing a trench gate semiconductor device, characterized in that, include: Doping is performed on a first sub-substrate layer having a first doping type to obtain two third doped regions having a second doping type, wherein the ratio of the sum of the charges in the two third doped regions to the charge in the first sub-substrate layer located between them is in the range of 0.9-1.

1. A second sub-substrate layer having a first doping type is formed above the first sub-substrate layer; A portion of the second sub-substrate layer is removed to form two first protective trenches, the two first protective trenches being located above the two third doped regions respectively, and the third doped regions being exposed through the first protective trenches; A second insulating layer is formed on the inner walls of the two first protective trenches respectively; A second conductive component is formed correspondingly within the two second insulating layers; A gate trench is formed in a second sub-substrate layer between the two second conductive members, the depth of the gate trench being less than the depth of the first protective trench; A first insulating layer is formed on the inner wall of the gate trench; A first conductive component is formed within the first insulating layer; Doping is performed on a second sub-substrate layer between the first conductive member and the second conductive member to obtain a first doped region having a second doping type, wherein the depth of the first doped region is less than the depth of the gate trench. Doping is performed on a portion of the first doped region to obtain a second doped region having the first doping type; A fourth insulating layer is formed above the first conductive component; A source electrode is formed, which is in contact with the second conductive component, the first doped region, and the second doped region, respectively.

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