Light-emitting diode epitaxial wafer, method for preparing same, and light-emitting diode

Abstract

The present invention discloses a light-emitting diode epitaxial wafer, a preparation method thereof, and a light-emitting diode. The light-emitting diode epitaxial wafer includes a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer that are sequentially stacked on the substrate. The front barrier buffer layer includes Si x N 1‑x layer, Si y In z Ga 1‑x‑y N layer and In b Ga 1‑b N layer, where the value range of x is 0.1-0.3, the value range of y is 0-0.8, the value range of z is 0-0.8, and the value range of b is 0.2-0.6. The light-emitting diode epitaxial wafer provided by the present invention can improve the light efficiency and enhance the ESD resistance of the epitaxial wafer at the same time.

Description

Technical Field

[0001] The present invention relates to the field of optoelectronic technologies, and particularly to a light-emitting diode epitaxial wafer, a preparation method thereof, and a light-emitting diode. Background Art

[0002] At present, GaN-based light-emitting diodes have been widely used in the fields of solid-state lighting and displays, attracting more and more attention. In order to obtain high-quality GaN epitaxial wafers, in addition to using a patterned sapphire substrate as the substrate, a stress release layer is also grown between the bottom layer and the multi-quantum well layer. On the one hand, it can relieve the stress between the bottom layer and the quantum well, and on the other hand, it can reduce the extension of defects and weaken its destructive effect on the quantum well. This stress release layer is equivalent to an insertion layer between the bottom layer and the quantum well, and its structure is mainly obtained by periodically growing GaN layers and In x Ga 1-x N cycles, where the doping concentrations of Si and In are different from those of the quantum wells and quantum barriers in the active regions of the other layers, and during the growth process, the temperature of the stress release layer is constant, usually between 800°C and 900°C.

[0003] For green light, due to the significant increase in the In content in the quantum well layer, the crystal quality of the quantum well deteriorates, the mismatch between the quantum well and the quantum barrier increases, resulting in a decrease in its ESD resistance and a reduction in light efficiency. In conventional green multi-quantum wells and quantum barriers, the temperature of the quantum barrier is usually raised or grown in an H2 atmosphere to improve the crystal quality of the entire quantum barrier, and a low-temperature GaN cap layer is set to increase the well-barrier boundary to jointly improve the crystal quality of the green epitaxial wafer, attempting to comprehensively improve its ESD resistance and light efficiency. However, due to the serious segregation of In in green light and under high current density, its light efficiency will rapidly decrease, which is also called the Stark effect (QCSE). Secondly, in small-size applications, the proportion of side defects of the light-emitting diodes made into die chips increases, resulting in poor current spreading, more non-radiative recombination centers, and rapid decreases in both light efficiency and ESD ability. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer that can improve light efficiency while enhancing the ESD resistance of the epitaxial wafer.

[0005] The technical problem to be solved by the present invention is also to provide a preparation method for a light-emitting diode epitaxial wafer, which has a simple process and can stably produce the above-mentioned light-emitting diode epitaxial wafer with good performance.

[0006] To solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate, and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress relief layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer that are sequentially stacked on the substrate;

[0007] The front barrier buffer layer includes an Si x N 1-x layer, an Si y In z Ga 1-x-y N layer, and an In b Ga 1-b N layer, wherein the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.6.

[0008] In one embodiment, the Si y In z Ga 1-x-y N layer includes a first sub-layer, a second sub-layer, a third sub-layer, and a fourth sub-layer;

[0009] The Si concentration of the second sub-layer is higher than that of the first sub-layer, and the Si concentration of the third sub-layer is higher than that of the fourth sub-layer;

[0010] The In concentration of the second sub-layer is lower than that of the first sub-layer, and the In concentration of the third sub-layer is lower than that of the fourth sub-layer.

[0011] In one embodiment, the value range of y in the first sub-layer is 0 - 0.1, and the value range of z is 0.3 - 0.6;

[0012] The value range of y in the second sub-layer is 0.5 - 0.8, and the value range of z is 0 - 0.1;

[0013] The value range of y in the third sub-layer is 0.4 - 0.7, and the value range of z is 0.1 - 0.2;

[0014] The value range of y in the fourth sub-layer is 0 - 0.2, and the value range of z is 0.5 - 0.8.

[0015] In one embodiment, the Si x N 1-x layer includes a first Si x N 1-x layer and a second Si x N 1-x layer, and the growth temperature of the first Si x N 1-x layer is higher than that of the second Si x N1-x Growth temperature of the layer.

[0016] In one embodiment, the Si x N 1-x layer has a thickness of 3 nm - 15 nm;

[0017] The Si y In z Ga 1-x-y N layer has a thickness of 20 nm - 60 nm;

[0018] The In b Ga 1-b N layer has a thickness of 5 nm - 20 nm.

[0019] In one embodiment, the first Si x N 1-x layer has a thickness of 2 nm - 10 nm; the second Si x N 1-x layer has a thickness of 1 nm - 5 nm.

[0020] To solve the above problems, the present invention also provides a method for preparing a light-emitting diode epitaxial wafer, comprising the following steps:

[0021] Prepare a substrate;

[0022] Deposit a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0023] The front barrier buffer layer includes an Si x N 1-x layer, an Si y In z Ga 1-x-y N layer, and an In b Ga 1-b N layer stacked on the stress release layer in sequence, wherein the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.6.

[0024] In one embodiment, depositing the Si x N 1-x layer on the stress release layer includes the following steps:

[0025] Control the reaction chamber temperature at 920 °C - 980 °C, introduce an N source and an Si source to complete the deposition of the first Si x N 1-x layer;

[0026] Then, control the reaction chamber temperature at 820 °C - 880 °C, and introduce N source and Si source to complete the deposition of the second Si x N 1-x layer.

[0027] In one embodiment, depositing the Si x N 1-x layer on the y In z Ga 1-x-y N layer includes the following steps:

[0028] First, control the reaction chamber temperature at 800 °C - 860 °C, introduce N2 as the carrier gas, and introduce Si source, In source and Ga source to deposit the first sub-layer, the second sub-layer, the third sub-layer and the fourth sub-layer respectively;

[0029] The Si concentration of the second sub-layer is higher than that of the first sub-layer, and the Si concentration of the third sub-layer is higher than that of the fourth sub-layer;

[0030] The In concentration of the second sub-layer is lower than that of the first sub-layer, and the In concentration of the third sub-layer is lower than that of the fourth sub-layer.

[0031] Preferably, the flow rate of Si source is 50 sccm - 400 sccm, the flow rate of In source is 50 sccm - 300 sccm, and the flow rate of Ga source is 300 sccm - 500 sccm. Among them, the flow rate of the Ga source remains unchanged.

[0032] During the growth of the first sub-layer, the flow rate of Si source is 50 sccm - 70 sccm, and the flow rate of In source is 190 sccm - 210 sccm;

[0033] During the growth of the second sub-layer, the flow rate of Si source is 390 sccm - 400 sccm, and the flow rate of In source is 50 sccm - 60 sccm;

[0034] During the growth of the third sub-layer, the flow rate of Si source is 290 sccm - 320 sccm, and the flow rate of In source is 60 sccm - 70 sccm;

[0035] During the growth of the fourth sub-layer, the flow rate of Si source is 50 sccm - 60 sccm, and the flow rate of In source is 290 sccm - 300 sccm.

[0036] In one embodiment, depositing the In y In z Ga 1-x-y N layer on the b Ga 1-b N layer includes the following steps:

[0037] The temperature of the reaction chamber is controlled at 750°C - 800°C, N2 is introduced as the carrier gas, and Ga source, In source and N source are introduced to complete the deposition.

[0038] Correspondingly, the present invention also provides a light-emitting diode, which includes the light-emitting diode epitaxial wafer described above.

[0039] Implementing the present invention has the following beneficial effects:

[0040] In the present invention, a front barrier buffer layer is grown between the stress release layer and the multi-quantum well layer. The front barrier buffer layer includes Si x N 1-x layer, Si y In z Ga 1-x-y N layer and In b Ga 1-b N. Before entering the quantum well, due to the excessive stress between InGaN and GaN, after the stress cancellation effect of SiN / Si-InGaN / InGaN in the present invention, part of the stress can be released again. After the electrons are decelerated, the concentration falling into the quantum well increases, so that the recombination probability of electrons and holes increases, improving the light efficiency. At the same time, the lateral expansion ability of the current is improved, and the light efficiency is improved while the ESD resistance of the epitaxial wafer is enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 is a schematic structural diagram of the light-emitting diode epitaxial wafer provided by the present invention;

[0042] Figure 2 is a schematic structural diagram of the front barrier buffer layer in the light-emitting diode epitaxial wafer provided by the present invention.

[0043] Wherein: substrate 1, buffer layer 2, intrinsic GaN layer 3, N-type GaN layer 4, stress release layer 5, front barrier buffer layer 6, multi-quantum well layer 7, electron blocking layer 8, P-type GaN layer 9, Si x N 1-x layer 61, Si y In z Ga 1-x-y N layer 62, In b Ga 1-b N layer 63, first sub-layer 621, second sub-layer 622, third sub-layer 623, fourth sub-layer 624, first Si x N 1-x layer 611 and second Si x N 1-x layer 612. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0044] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below.

[0045] Unless otherwise stated or there are contradictions, the terms or phrases used herein have the following meanings:

[0046] In the present invention, "its combination", "any combination thereof", "any combination mode thereof", etc. include all suitable combination modes of any two or more than two items in the listed items.

[0047] In the present invention, "preferred" only describes the embodiments or examples with better effects, and it should be understood that it does not constitute a limitation on the protection scope of the present invention.

[0048] In the present invention, among the technical features described in an open-ended manner, it includes a closed technical solution composed of the listed features, and also includes an open technical solution containing the listed features.

[0049] In the present invention, regarding the numerical range, unless otherwise specified, it includes the two endpoints of the numerical range.

[0050] To solve the above problems, the present invention provides a light-emitting diode epitaxial wafer, as Figure 1 - Figure 2 shown, including a substrate 1, and a buffer layer 2, an intrinsic GaN layer 3, an N-type GaN layer 4, a stress release layer 5, a front barrier buffer layer 6, a multi-quantum well layer 7, an electron blocking layer 8, and a P-type GaN layer 9 that are sequentially stacked on the substrate 1;

[0051] The front barrier buffer layer 6 includes an Si x N 1-x layer 61, an Si y In z Ga 1-x- y N layer 62, and an In b Ga 1-b N layer 63, where the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.6.

[0052] Before entering the quantum well, due to the excessive stress between InGaN and GaN, after the stress cancellation effect of SiN / Si-InGaN / InGaN in the present invention, some stress can be released again. After the electrons are decelerated, the concentration of electrons falling into the quantum well increases, so that the recombination probability of electrons and holes increases, and the light efficiency is improved. At the same time, the lateral expansion ability of the current is enhanced, and while improving the light efficiency, the ESD resistance of the epitaxial wafer is enhanced.

[0053] In one embodiment, the Siy In z Ga 1-x-y The N layer 62 includes a first sublayer 621, a second sublayer 622, a third sublayer 623 and a fourth sublayer 624; the Si concentration of the second sublayer 622 is higher than that of the first sublayer 621, and the Si concentration of the third sublayer 623 is higher than that of the fourth sublayer 624; the In concentration of the second sublayer 622 is lower than that of the first sublayer 621, and the In concentration of the third sublayer 623 is lower than that of the fourth sublayer 624. Preferably, the y value range of the first sublayer 621 is 0-0.1, and the z value range is 0.3-0.6; the y value range of the second sublayer 622 is 0.5-0.8, and the z value range is 0-0.1; the y value range of the third sublayer 623 is 0.4-0.7, and the z value range is 0.1-0.2; the y value range of the fourth sublayer 624 is 0-0.2, and the z value range is 0.5-0.8.

[0054] It should be noted that the Si y In z Ga 1-x-y The Si concentration in the N layer 62 shows a low-high-high-low growth pattern, while the In concentration shows a high-low-low-high growth pattern. This can better receive the electrons in the N layer. The incorporation of In will further slow down the electrons. The high-low Si concentration difference can be beneficial to the lateral expansion of the current, further releasing stress while improving the ability to resist ESD. Moreover, the gradual doping of Si-In can further alleviate the piezoelectric polarization strength, which is beneficial to alleviate QCSE.

[0055] In one embodiment, the Si x N 1-x Layer 61 includes a first Si x N 1-x Layer 611 and the second Si x N 1-x Layer 612, the first Si x N 1-x The growth temperature of layer 611 is higher than that of the second Si x N 1-x The growth temperature of the layer 612 is preferably x N 1-x The growth temperature of the layer 611 is 920°C-980°C, and the second Si x N 1-x The growth temperature of layer 612 is 820°C-880°C. x N 1-x The change of the high and low temperature difference of layer 61 can improve the incorporation efficiency of In, so that the Si y Inz Ga 1-x-y N layer 62 and In b Ga 1-b The In point concentration in N layer 63 increases.

[0056] In one embodiment, the Si x N 1-x layer 61 has a thickness of 3 nm - 15 nm; the Si y In z Ga 1-x-y N layer 62 has a thickness of 20 nm - 60 nm; the In b Ga 1-b N layer 63 has a thickness of 5 nm - 20 nm. Preferably, the first Si x N 1-x layer 611 has a thickness of 2 nm - 10 nm; the second Si x N 1-x layer 612 has a thickness of 1 nm - 5 nm.

[0057] It should be noted that in the present invention, the Si x N 1-x layer 61 can serve as a deceleration layer for electron transport. For a thinner Si x N 1-x layer 61, electrons can tunnel through, consuming part of the kinetic energy of carrier transport, enabling more electrons to recombine with holes in the quantum well and increasing the light efficiency.

[0058] In one embodiment, the Si x N 1-x concentration of layer 61 is controlled at 1×10 18 cm -3 -8×10 18 cm -3 ; the Si y In z Ga 1-x-y concentration in N layer 62 is 5×10 17 cm -3 -5×10 18 cm -3 , the In concentration is 2×10 3 cm -3 -2×10 4 cm -3 ; the In b Ga 1-b concentration in N layer 63 is controlled at 6×10 3 cm -3 -1×10 4 cm -3 ;

[0059] In addition to the above composite insertion layer, the characteristics of other layered structures of the present invention are as follows:

[0060] In one embodiment, the substrate 1 is selected from one of sapphire substrate, SiO2 sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate.

[0061] Preferably, the substrate 1 is a sapphire substrate. Sapphire is the most commonly used GaN-based LED substrate material at present. Most GaN-based LEDs on the market use sapphire as the substrate material. The biggest advantage of the sapphire substrate is its mature technology, good stability, and low production cost.

[0062] In one embodiment, the buffer layer 2 is an AlGaN buffer layer or an AlN buffer layer. Preferably, the buffer layer 2 is an AlN buffer layer. Using the AlN buffer layer to control crystal defects can improve the quality of the subsequently grown crystals and relieve the stress caused by lattice mismatch and thermal mismatch between the substrate and the epitaxial layer. In one embodiment, the thickness of the buffer layer 2 is 20 nm - 80 nm.

[0063] The intrinsic GaN layer 3 is an undoped GaN layer. In one embodiment, the thickness of the intrinsic GaN layer 3 is 400 nm - 900 nm.

[0064] In one embodiment, the thickness of the N-type GaN layer 4 is 1.5 μm - 2.5 μm. The N-type GaN layer 4 is doped with Si, and the doping concentration of Si is 6×10 18 cm -3 -2×10 19 cm -3 .

[0065] In one embodiment, the stress release layer 5 is a periodic structure of alternating growth of GaN and InGaN, and the total thickness is controlled within 100 nm - 300 nm. The GaN layer is doped with a small amount of Si, and its concentration is controlled within 6×10 17 cm -3 -3×10 18 cm -3 ; in addition, the In concentration in the InGaN layer is controlled within 1×10 3 cm -3 -8×10 3 cm -3 ;

[0066] In one embodiment, the multi-quantum well layer 7 is a periodic structure formed by alternating stacks of InGaN quantum well layers and GaN quantum barrier layers. The number of periods of the multi-quantum well layer is 5 - 15; the thickness of the InGaN quantum well layer is 1 nm - 4 nm; the thickness of the GaN quantum barrier is 10 nm - 20 nm. The multi-quantum well active region is the area where electrons and holes recombine. A reasonable structural design can significantly increase the overlap degree of the electron and hole wave functions, thereby improving the light-emitting efficiency of the LED device.

[0067] In one embodiment, the electron blocking layer 8 is a periodic structure formed by alternating growth of Al a Ga 1-a N layers and In c Ga 1-c N layers; wherein, the value range of a is 0.1 - 0.3, and the value range of c is 0.06 - 0.3; the thickness of the electron blocking layer is 40 nm - 80 nm.

[0068] In one embodiment, the thickness of the P-type GaN layer 9 is 200 nm - 300 nm; the N-type GaN layer is doped with Mg, and the doping concentration of Mg is 1×10 19 cm -3 -5×10 20 cm -3 。

[0069] Correspondingly, the present invention also provides a method for preparing the above-mentioned light-emitting diode epitaxial wafer, including the following steps:

[0070] S1. Prepare a substrate;

[0071] In one embodiment, the substrate is selected as a sapphire substrate.

[0072] S2. Deposit a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0073] The front barrier buffer layer includes an Si x N 1-x layer, an Si y In z Ga 1-x-y N layer and an In b Ga 1-b N layer stacked in sequence on the stress release layer, wherein the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.6.

[0074] In one embodiment, step S2 includes the following steps:

[0075] S21. Deposit the buffer layer on the front side of the substrate:

[0076] In one embodiment, the substrate is pretreated, including the following steps:

[0077] Control the reaction chamber temperature to 1000 °C - 1250 °C, and perform high-temperature annealing on the substrate for 5 min - 8 min in an H2 atmosphere to clean the particles and oxides on the substrate surface.

[0078] Then, grow a buffer layer on the substrate, and select the buffer layer material as AlGaN or AlN. This layer is mainly used to provide seeds, relieve the lattice mismatch between the substrate and the epitaxial layer, and improve the lattice quality of the epitaxial wafer. In one embodiment, control the reaction chamber temperature to 600 °C - 800 °C, the reaction chamber pressure to 100 torr - 300 torr, and introduce an N source, a Ga source, and an Al source to deposit the AlGaN buffer layer.

[0079] S22. Deposit the intrinsic GaN layer on the buffer layer:

[0080] Control the reaction chamber temperature to 1100 °C - 1200 °C, the pressure to 200 torr - 500 torr, and introduce an N source and a Ga source to complete the deposition.

[0081] S23. Deposit the N-type GaN layer on the intrinsic GaN layer:

[0082] Control the reaction chamber temperature to 1050 °C - 1100 °C, the pressure to 200 torr - 500 torr, and introduce a Si source, an N source, and a Ga source to complete the deposition.

[0083] S24. Deposit the stress release layer on the N-type GaN layer:

[0084] Control the reaction chamber temperature to 750 °C - 950 °C, introduce an N source, a Si source, and a Ga source to complete the deposition of the GaN layer; then control the reaction chamber temperature to 750 °C - 950 °C, introduce an N source, a Si source, an In source, and a Ga source to complete the deposition of the InGaN layer; the GaN layer and the InGaN layer are alternately grown in superposition for 5 - 7 cycles.

[0085] S25. Deposit the Si x N 1-x layer:

[0086] Control the reaction chamber temperature to 920 °C - 980 °C, introduce an N source and a Si source to complete the deposition of the first Si x N 1-x layer;

[0087] Then, control the reaction chamber temperature at 820°C - 880°C, and introduce an N source and an Si source to complete the deposition of the second Si x N 1-x layer.

[0088] S26. Deposit the following Si x N 1-x layer on the Si y In z Ga 1-x-y N layer:

[0089] First, control the reaction chamber temperature at 800°C - 860°C, introduce N2 as the carrier gas, and introduce an Si source, an In source, and a Ga source to deposit the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer respectively;

[0090] The Si concentration in the second sub-layer is higher than that in the first sub-layer, and the Si concentration in the third sub-layer is higher than that in the fourth sub-layer;

[0091] The In concentration in the second sub-layer is lower than that in the first sub-layer, and the In concentration in the third sub-layer is lower than that in the fourth sub-layer.

[0092] Preferably, the flow rate of the Si source is 50 sccm - 400 sccm, the flow rate of the In source is 50 sccm - 300 sccm, and the flow rate of the Ga source is 300 sccm - 500 sccm. Among them, the flow rate of the Ga source remains unchanged.

[0093] During the growth of the first sub-layer, the flow rate of the Si source is 50 sccm - 70 sccm, and the flow rate of the In source is 190 sccm - 210 sccm;

[0094] During the growth of the second sub-layer, the flow rate of the Si source is 390 sccm - 400 sccm, and the flow rate of the In source is 50 sccm - 60 sccm;

[0095] During the growth of the third sub-layer, the flow rate of the Si source is 290 sccm - 320 sccm, and the flow rate of the In source is 60 sccm - 70 sccm;

[0096] During the growth of the fourth sub-layer, the flow rate of the Si source is 50 sccm - 60 sccm, and the flow rate of the In source is 290 sccm - 300 sccm.

[0097] S27. Deposit the following In y In z Ga 1-x-y N layer on the Si b Ga 1-b N layer:

[0098] Control the temperature of the reaction chamber at 750°C - 800°C, introduce N2 as the carrier gas, and introduce Ga source, In source and N source to complete the deposition.

[0099] S28. Deposit the multi-quantum well layer on the In b Ga 1-b N layer:

[0100] First, control the temperature of the reaction chamber at 750°C - 800°C and the pressure at 100 Torr - 400 Torr, introduce N source, Ga source and In source to complete the deposition of the InGaN quantum well layer. Then, turn off the In source, control the temperature at 820°C - 900°C, and continue to introduce N source and Ga source to complete the deposition of the GaN quantum barrier layer. Repeat the lamination for 5 - 15 cycles.

[0101] S29. Deposit the electron blocking layer on the multi-quantum well layer:

[0102] First, control the temperature of the reaction chamber at 850°C - 1050°C and the pressure at 200 Torr - 400 Torr, introduce N source, Ga source and Al source to complete the deposition of the Al a Ga 1-a N layer. Then, turn off the Al source, continue to introduce N source, In source and Ga source to complete the deposition of the In c Ga 1-c N layer. Repeat the lamination for 8 - 12 cycles.

[0103] S30. Deposit the P-type GaN layer on the electron blocking layer:

[0104] In one embodiment, the growth temperature of the P-type GaN layer is 900°C - 1000°C, the growth pressure is 200 torr - 300 torr, and the Mg doping concentration is 1×10 19 cm -3 -5×10 20 cm -3 .

[0105] Correspondingly, the present invention also provides a light-emitting diode, which includes the light-emitting diode epitaxial wafer described above.

[0106] The above deposition process is completed using MOCVD equipment, CVD equipment or PVD equipment. The present invention does not limit the deposition method. High-purity N2 (nitrogen) and H2 (hydrogen) are used as the carrier gas. High-purity NH3 (ammonia) provides the N (nitrogen) source. The aluminum source is TMAl (trimethylaluminum), the magnesium source is Cp2Mg (bis(cyclopentadienyl)magnesium), TMGa (trimethylgallium) and TEGa (triethylgallium) are respectively used as the gallium source, the indium source is TMIn (trimethylindium), and silane (SiH4) is used as the N-type dopant, which is not limited to the above examples.

[0107] The present invention will be further described below with specific embodiments:

[0108] Embodiment 1

[0109] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer that are sequentially stacked on the substrate;

[0110] The front barrier buffer layer includes an Si x N 1-x layer, an Si y In z Ga 1-x-y N layer, and an In b Ga 1-b N layer, where x is 0.2 and b is 0.5.

[0111] The Si y In z Ga 1-x-y N layer includes a first sub-layer, a second sub-layer, a third sub-layer, and a fourth sub-layer. For the first sub-layer, y is 0.05 and z is 0.4; for the second sub-layer, y is 0.7 and z is 0.05; for the third sub-layer, y is 0.6 and z is 0.15; for the fourth sub-layer, y is 0.1 and z is 0.7.

[0112] The preparation method of the above light-emitting diode epitaxial wafer includes the following steps:

[0113] S1. Prepare a substrate;

[0114] The substrate is selected as a sapphire substrate.

[0115] S2. Deposit a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress release layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0116] Step S2 includes the following steps:

[0117] S21. Deposit the buffer layer on the front surface of the substrate:

[0118] Control the reaction chamber temperature to 1100 °C, perform high-temperature annealing on the substrate for 6 minutes in an H2 atmosphere to clean the particles and oxides on the substrate surface. Then, control the reaction chamber temperature to 700 °C, the reaction chamber pressure to 200 torr, introduce an N source, a Ga source, and an Al source, and deposit an AlGaN buffer layer with a thickness of 50 nm.

[0119] S22. Deposit the intrinsic GaN layer on the buffer layer:

[0120] The reaction chamber temperature is controlled at 1150 °C, the pressure is 300 torr, and the N source and Ga source are introduced to complete the deposition, obtaining the intrinsic GaN layer with a thickness of 800 nm.

[0121] S23. Deposit the N-type GaN layer on the intrinsic GaN layer:

[0122] The reaction chamber temperature is controlled at 1100 °C, the pressure is 300 torr, and the Si source, N source, and Ga source are introduced to complete the deposition, with a thickness of 2 μm and a Si doping concentration of 1×10 19 cm -3

[0123] S24. Deposit the stress release layer on the N-type GaN layer:

[0124] The reaction chamber temperature is controlled at 800 °C, and the N source, Si source, and Ga source are introduced to complete the deposition of the GaN layer; then the reaction chamber temperature is controlled at 800 °C, and the N source, Si source, In source, and Ga source are introduced to complete the deposition of the InGaN layer; the GaN layer and the InGaN layer are alternately grown in 6 cycles. The total thickness is 200 nm, the Si concentration in the GaN layer is 2×10 18 cm -3 and the In concentration in the InGaN layer is 5×10 3 cm -3 .

[0125] S25. Deposit the Si x N 1-x layer on the N-type GaN layer:

[0126] The reaction chamber temperature is controlled at 950 °C, and the N source and Si source are introduced to complete the deposition of the first Si x N 1-x layer with a thickness of 4 nm;

[0127] Then the reaction chamber temperature is controlled at 860 °C, and the N source and Si source are introduced to complete the deposition of the second Si x N 1-x layer with a thickness of 2 nm.

[0128] S26. Deposit the Si x N 1-x layer on the Si y In z Ga 1-x-y N layer:

[0129] First, the reaction chamber temperature is controlled at 830 °C, N2 is introduced as the carrier gas, and the Si source, In source, and Ga source are introduced to deposit the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer respectively;

[0130] During the growth of the first sub-layer, the flow rate of the Si source is 60 sccm, and the flow rate of the In source is 200 sccm;

[0131] During the growth of the second sub-layer, the flow rate of the Si source is 400 sccm, and the flow rate of the In source is 50 sccm;

[0132] During the growth of the third sub-layer, the flow rate of the Si source is 300 sccm, and the flow rate of the In source is 60 sccm;

[0133] During the growth of the fourth sub-layer, the flow rate of the Si source is 50 sccm, and the flow rate of the In source is 300 sccm.

[0134] S27. On the Si y In z Ga 1-x-y Deposit the In b Ga 1-b N layer on the N layer:

[0135] Control the reaction chamber pressure at 780 °C, introduce N2 as the carrier gas, introduce the Ga source, In source and N source to complete the deposition and control the thickness to 15 nm.

[0136] S28. Deposit the multi-quantum well layer on the In b Ga 1-b N layer:

[0137] First, control the reaction chamber temperature at 780 °C and the pressure at 200 Torr, introduce the N source, Ga source and In source to complete the deposition of the InGaN quantum well layer, then turn off the In source, control the temperature at 890 °C, and continue to introduce the N source and Ga source to complete the deposition of the GaN quantum barrier layer, and repeat the stacking for 10 cycles.

[0138] S29. Deposit the electron blocking layer on the multi-quantum well layer:

[0139] First, control the reaction chamber temperature at 950 °C and the pressure at 300 Torr, introduce the N source, Ga source and Al source to complete the deposition of the Al a Ga 1-a N layer, then turn off the Al source, continue to introduce the N source, In source and Ga source to complete the deposition of the In c Ga 1-c N layer, and repeat the stacking for 9 cycles. a is 0.2, c is 0.3, and the thickness is 50 nm.

[0140] S30. Deposit the p-type GaN layer on the electron blocking layer:

[0141] The growth temperature of the P-type GaN layer is 950 °C, the growth pressure is 200 torr, and the Mg doping concentration is 2×10 20 cm -3 .

[0142] Example 2

[0143] This example provides a light-emitting diode epitaxial wafer, which is different from Example 1 in that: the Si y In z Ga 1-x-y N layer includes a first sub-layer, a second sub-layer, a third sub-layer and a fourth sub-layer. For the first sub-layer, y is 0.1 and z is 0.3; for the second sub-layer, y is 0.5 and z is 0.1; for the third sub-layer, y is 0.4 and z is 0.2; for the fourth sub-layer, y is 0.2 and z is 0.5. For the rest, refer to Example 1.

[0144] Example 3

[0145] This example provides a light-emitting diode epitaxial wafer, which is different from Example 1 in that: the growth temperature of the first Si x N 1-x layer is 920 °C, and the growth temperature of the second Si x N 1-x layer is 880 °C. For the rest, refer to Example 1.

[0146] Comparative Example 1

[0147] This comparative example provides a light-emitting diode epitaxial wafer, which is different from Example 1 in that it does not have a front barrier buffer layer, and the rest are the same as Example 1.

[0148] The light-emitting diode epitaxial wafers prepared in Examples 1 - 3 and Comparative Example 1 were used to fabricate chips for performance testing. The testing method was to prepare the above-mentioned light-emitting diode epitaxial wafers into 03 mil × 07 mil chips under the same chip process conditions for luminous intensity testing. The specific test results are shown in Table 1.

[0149] Table 1 shows the performance test results of the light-emitting diode epitaxial wafers prepared in Examples 1 - 3 and Comparative Example 1

[0150]

[0151] From the above results, it can be seen that in the present invention, a front barrier buffer layer is grown between the stress release layer and the multi-quantum well layer, the Si x N 1-x layer, the Si y In z Ga 1-x-y N layer and the In b Ga 1-bIt plays a role in offsetting the stress between Ns, and then releases part of the stress. After the electrons are decelerated, the concentration of electrons falling into the quantum well increases, which increases the recombination probability of electrons and holes and improves the light efficiency. At the same time, it enhances the lateral expansion ability of the current, improves the light efficiency and enhances the ESD resistance of the epitaxial wafer.

[0152] The above is the preferred embodiment of the invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements are also regarded as the protection scope of the present invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate and a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress relaxation layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer that are sequentially stacked on the substrate; The front buffer layer includes Si stacked on the stress release layer in sequence x N 1-x layer, Si y In z Ga 1-x-y N layer and In b Ga 1-b N layer, where the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.6; The Si y In z Ga 1-x-y The N layer includes a first sub-layer, a second sub-layer, a third sub-layer, and a fourth sub-layer; The Si concentration of the second sub-layer is higher than that of the first sub-layer, and the Si concentration of the third sub-layer is higher than that of the fourth sub-layer; The In concentration of the second sub-layer is lower than that of the first sub-layer, and the In concentration of the third sub-layer is lower than that of the fourth sub-layer; The value range of y in the first sub-layer is 0 - 0.1, and the value range of z is 0.3 - 0.6; The value range of y in the second sub-layer is 0.5 - 0.8, and the value range of z is 0 - 0.1; The value range of y in the third sub-layer is 0.4 - 0.7, and the value range of z is 0.1 - 0.2; The value range of y in the fourth sub-layer is 0 - 0.2, and the value range of z is 0.5 - 0.

8.

2. The light-emitting diode epitaxial wafer according to claim 1, wherein The Si x N 1-x layer includes a first Si x N 1-x layer and a second Si x N 1-x layer, and the growth temperature of the first Si x N 1-x layer is higher than that of the second Si x N 1-x layer.

3. The light-emitting diode epitaxial wafer according to claim 1, wherein, The said Si x N 1-x layer has a thickness of 3 nm - 15 nm; The Si y In z Ga 1-x-y layer has a thickness of 20 nm to 60 nm; The In b Ga 1-b layer has a thickness of 5 nm to 20 nm.

4. A method for preparing a light-emitting diode epitaxial wafer according to any one of claims 1-3, characterized in that, It includes the following steps: Prepare a substrate; Deposit a buffer layer, an intrinsic GaN layer, an N-type GaN layer, a stress relaxation layer, a front barrier buffer layer, a multi-quantum well layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence; The front buffer layer includes Si stacked on the stress release layer in sequence x N 1-x layer, Si y In z Ga 1-x-y N layer and In b Ga 1-b N layer, where the value range of x is 0.1 - 0.3, the value range of y is 0 - 0.8, the value range of z is 0 - 0.8, and the value range of b is 0.2 - 0.

6.

5. The method for preparing a light-emitting diode epitaxial wafer according to claim 4, wherein Depositing the Si on the stress release layer x N 1-x layer includes the following steps: Control the reaction chamber temperature at 920°C - 980°C, and introduce N source and Si source to complete the deposition of the first Si x N 1-x layer; Then, control the reaction chamber temperature at 820°C - 880°C, and introduce the N source and Si source to complete the deposition of the second Si x N 1-x layer.

6. The manufacturing method of the light-emitting diode epitaxial wafer as described in claim 4, characterized in that, Depositing the Si x N 1-x layer on the Si y In z Ga 1-x-y The N layer includes the following steps: First, control the reaction chamber temperature at 800°C - 860°C, introduce N2 as the carrier gas, introduce Si source, In source, and Ga source, and deposit the first sub-layer, the second sub-layer, the third sub-layer, and the fourth sub-layer respectively; The Si concentration of the second sub-layer is higher than that of the first sub-layer, and the Si concentration of the third sub-layer is higher than that of the fourth sub-layer; The In concentration of the second sub-layer is lower than that of the first sub-layer, and the In concentration of the third sub-layer is lower than that of the fourth sub-layer.

7. The method for preparing a light-emitting diode epitaxial wafer according to claim 4, wherein, On the Si y In z Ga 1-x- y Depositing the In b Ga 1-b N layer includes the following steps: Control the reaction chamber temperature at 750°C - 800°C, introduce N2 as the carrier gas, and introduce Ga source, In source, and N source to complete the deposition.

8. A light-emitting diode, characterized in that, The light-emitting diode includes the light-emitting diode epitaxial wafer according to any one of claims 1 - 3.

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