Voltage selection circuit, voltage selection system, and electronic device

Abstract

Provided are a voltage selection circuit, a voltage selection system and an electronic device, and belong to the technical field of electronics. The voltage selection circuit comprises two switching circuits and two output circuits. Each switching circuit can control the potential of the node coupled thereto under the dual control of the node coupled thereto and the node coupled to the other switching circuit. The two output circuits can control the on-off between the voltage input end and the voltage output end coupled thereto based on the potential of the node coupled to the two switching circuits. In this way, the switching control logic can be used to ensure that only one voltage input end and the voltage output end are reliably connected in the same period, that is, only the input voltage provided by one voltage input end is supplied to the voltage output end, so that voltage selection is quickly realized, voltage transmission to the voltage output end is avoided, and the entire circuit structure is relatively simple.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a voltage selection circuit, a voltage selection system, and an electronic device. Background Technology

[0002] In multi-voltage power supply scenarios, it is often necessary to set up a voltage selection circuit to select a suitable voltage from multiple different voltages provided by the front-end power supply circuit to supply power to the downstream load.

[0003] In related technologies, voltage selection circuits generally include: a sampling circuit, a comparator circuit, a level shifting circuit, and multiple output transistors. The sampling circuit is coupled to multiple voltage input terminals and the comparator circuit. The comparator circuit is also coupled to the level shifting circuit, which is further coupled to the multiple output transistors. The multiple output transistors are also coupled to multiple voltage input terminals and voltage output terminals. The sampling circuit collects the voltages provided by the multiple voltage input terminals and transmits the collected voltages to the level shifting circuit. The comparator circuit compares the magnitudes of the multiple voltages and, based on the comparison result, controls the level shifting circuit to turn on one of the output transistors. This connects one of the voltage input terminals coupled to that output transistor to the voltage output terminal, thereby enabling voltage selection by transmitting voltage from that input terminal to the voltage output terminal.

[0004] However, the voltage selection circuit in the related technology is not only relatively complex in structure, but also requires a series of processes such as sampling, comparison and level shifting to complete the voltage selection, which results in a long voltage selection time, making it easy for the voltage transmitted to the voltage output terminal to drop. Summary of the Invention

[0005] A voltage selection circuit, a voltage selection system, and an electronic device are provided, which can solve the problem that the voltage selection circuit in related technologies is complex in structure and has a long voltage selection time, resulting in the voltage transmitted to the voltage output terminal being prone to power loss. The technical solution is as follows:

[0006] On one hand, a voltage selection circuit is provided, the voltage selection circuit comprising:

[0007] A first switching circuit is coupled to a first voltage input terminal, a first node, a second node, and a third node, respectively, and is used to control the on / off state of the first voltage input terminal and the first node based on the potential of the third node and the potential of the first node, and to control the on / off state of the first node and the second node based on the potential of the second node.

[0008] The second switching circuit is coupled to the second voltage input terminal, the fourth node, the third node and the second node respectively, and is used to control the on / off state of the second voltage input terminal and the fourth node based on the potential of the second node and the potential of the fourth node, and to control the on / off state of the fourth node and the third node based on the potential of the third node.

[0009] The first output circuit is coupled to the fourth node, the first voltage input terminal and the voltage output terminal respectively, and is used to control the on / off state of the first voltage input terminal and the voltage output terminal based on the potential of the fourth node.

[0010] The second output circuit is coupled to the first node, the second voltage input terminal, and the voltage output terminal respectively, and is used to control the on / off state of the second voltage input terminal and the voltage output terminal based on the potential of the first node.

[0011] Optionally, the first switching circuit includes:

[0012] The first switching sub-circuit is coupled to the first voltage input terminal, the first node and the third node respectively, and is used to control the on / off state of the first voltage input terminal and the first node based on the potential of the third node and the potential of the first node.

[0013] The second switch sub-circuit is coupled to the first node and the second node respectively, and is used to control the on / off state of the first node and the second node based on the potential of the second node.

[0014] Optionally, the first switching sub-circuit includes: a first transistor and a second transistor; the second switching sub-circuit includes: a third transistor;

[0015] The gate and the second terminal of the first transistor are both coupled to the first node, and the first terminal of the first transistor is coupled to the first voltage input terminal.

[0016] The gate of the second transistor is coupled to the third node, the first terminal of the second transistor is coupled to the first voltage input terminal, and the second terminal of the second transistor is coupled to the first node;

[0017] The gate and second electrode of the third transistor are both coupled to the second node, and the first electrode of the third transistor is coupled to the first node.

[0018] Optionally, the first switching circuit further includes:

[0019] The first current generating sub-circuit is coupled to the second node and the pull-down power supply terminal respectively, and is used to generate a bias current based on the potential of the second node and the pull-down power supply signal provided by the pull-down power supply terminal.

[0020] Optionally, the first current generating sub-circuit includes: a first current source;

[0021] The input terminal of the first current source is coupled to the second node, and the output terminal of the first current source is coupled to the pull-down power supply terminal.

[0022] Optionally, the second switching circuit includes:

[0023] The third switching sub-circuit is coupled to the second voltage input terminal, the fourth node, and the second node respectively, and is used to control the on / off state of the second voltage input terminal and the fourth node based on the potential of the fourth node and the potential of the second node;

[0024] The fourth switch sub-circuit is coupled to the fourth node and the third node respectively, and is used to control the on / off state of the fourth node and the third node based on the potential of the third node.

[0025] Optionally, the third switching sub-circuit includes a fourth transistor and a fifth transistor; the fourth switching sub-circuit includes a sixth transistor.

[0026] The gate and the second terminal of the fourth transistor are both coupled to the fourth node, and the first terminal of the fourth transistor is coupled to the second voltage input terminal.

[0027] The gate of the fifth transistor is coupled to the second node, the first terminal of the fifth transistor is coupled to the second voltage input terminal, and the second terminal of the fifth transistor is coupled to the fourth node;

[0028] The gate and second terminal of the sixth transistor are both coupled to the third node, and the first terminal of the sixth transistor is coupled to the fourth node.

[0029] Optionally, the second switching circuit further includes:

[0030] The second current generating sub-circuit is coupled to the third node and the pull-down power supply terminal respectively, and is used to generate a bias current based on the potential of the third node and the pull-down power supply signal provided by the pull-down power supply terminal.

[0031] Optionally, the second current generating sub-circuit includes: a second current source;

[0032] The input terminal of the second current source is coupled to the third node, and the output terminal of the second current source is coupled to the pull-down power supply terminal.

[0033] Optionally, the first output circuit includes: a seventh transistor and a first substrate diode formed between the substrate and drain of the seventh transistor; the second output circuit includes: an eighth transistor and a second substrate diode formed between the substrate and drain of the eighth transistor.

[0034] The gate of the seventh transistor is coupled to the fourth node, the drain of the seventh transistor is coupled to the first voltage input terminal, and the source of the seventh transistor is coupled to the voltage output terminal.

[0035] The positive terminal of the first substrate diode is coupled to the drain of the seventh transistor, and the negative terminal is coupled to the substrate of the seventh transistor.

[0036] The gate of the eighth transistor is coupled to the first node, the drain of the eighth transistor is coupled to the second voltage input terminal, and the source of the eighth transistor is coupled to the voltage output terminal.

[0037] The positive terminal of the second substrate diode is coupled to the drain of the eighth transistor, and the negative terminal is coupled to the substrate of the eighth transistor.

[0038] Optionally, the voltage selection circuit further includes:

[0039] A bias voltage generation circuit is coupled to the voltage output terminal, the pull-down power supply terminal and the control node respectively, and is used to transmit an enable bias voltage to the control node based on the voltage output signal provided by the voltage output terminal and the pull-down power supply signal provided by the pull-down power supply terminal.

[0040] A first protection circuit is coupled to the control node, the first node, the fourth node, the first output circuit, and the second output circuit, respectively, and is used to control the first node to conduct and the second output circuit to conduct based on the turn-on bias voltage.

[0041] Optionally, the bias voltage generating circuit includes a diode and a resistor; the first protection circuit includes a ninth transistor and a tenth transistor.

[0042] The positive terminal of the diode and one end of the resistor are both coupled to the control node, the negative terminal of the diode is coupled to the voltage output terminal, and the other end of the resistor is coupled to the pull-down power supply terminal.

[0043] The gate of the ninth transistor is coupled to the control node, the first terminal of the ninth transistor is coupled to the first node, and the second terminal of the ninth transistor is coupled to the second output circuit.

[0044] The gate of the tenth transistor is coupled to the control node, the first terminal of the tenth transistor is coupled to the fourth node, and the second terminal of the tenth transistor is coupled to the first output circuit.

[0045] Optionally, the voltage selection circuit further includes:

[0046] The second protection circuit is coupled to the control node, the second node, the third node, the first switch circuit, and the second switch circuit, respectively, and is used to control the second node to conduct with the two switch circuits and to control the third node to conduct with the first switch circuit based on the turn-on bias voltage.

[0047] Optionally, the second protection circuit includes an eleventh transistor and a twelfth transistor;

[0048] The gate of the eleventh transistor is coupled to the control node, the first terminal of the eleventh transistor is coupled to the second node, and the second terminal of the eleventh transistor is coupled to the second switching circuit.

[0049] The gate of the twelfth transistor is coupled to the control node, the first terminal of the twelfth transistor is coupled to the third node, and the second terminal of the twelfth transistor is coupled to the first switching circuit.

[0050] Optionally, the transistors included in the voltage selection circuit are all P-type transistors.

[0051] On the other hand, a voltage selection system is provided, the voltage selection system comprising: a plurality of cascaded voltage selection circuits as described above, wherein the voltage output terminal of the preceding voltage selection circuit is coupled to the first voltage input terminal or the second voltage input terminal of the following voltage selection circuit.

[0052] In another aspect, an electronic device is provided, comprising: a front-end power supply circuit, a rear-end load, and a voltage selection system as described above;

[0053] The front-end power supply circuit is coupled to the voltage selection system, and the voltage selection system is coupled to the downstream load. The front-end power supply circuit is used to transmit multiple input voltages of different magnitudes to the voltage selection system. The voltage selection system is used to select one input voltage from the multiple input voltages as the output voltage and transmit it to the downstream load to power the downstream load.

[0054] In summary, the beneficial effects of the technical solutions provided by the embodiments of this disclosure can at least include:

[0055] A voltage selection circuit, a voltage selection system, and an electronic device are provided. The voltage selection circuit includes two switching circuits and two output circuits. Each switching circuit can control the potential of its coupled node under the dual control of the node coupled to it and the node coupled to the other switching circuit. The two output circuits can control the on / off connection between their coupled voltage input terminals and voltage output terminals based on the potential of the nodes coupled to their respective switching circuits. Thus, through switching control logic, only one voltage input terminal and voltage output terminal can be reliably connected at any given time, allowing only one voltage input terminal to supply the voltage output terminal, thereby quickly achieving voltage selection, preventing voltage loss during transmission to the voltage output terminal, and simplifying the overall circuit structure. Attached Figure Description

[0056] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0057] Figure 1 This is a schematic diagram of the structure of a voltage selection circuit provided in an embodiment of this disclosure;

[0058] Figure 2 This is a schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure;

[0059] Figure 3 This is a schematic diagram of another voltage selection circuit provided in the embodiments of this disclosure;

[0060] Figure 4 This is a schematic diagram of another voltage selection circuit provided in the embodiments of this disclosure;

[0061] Figure 5 This is a schematic diagram of another voltage selection circuit provided in the embodiments of this disclosure;

[0062] Figure 6 This is a schematic diagram of another voltage selection circuit provided in the embodiments of this disclosure;

[0063] Figure 7 This is a timing diagram of a voltage selection circuit provided in an embodiment of the present disclosure;

[0064] Figure 8 This is a schematic diagram of the structure of a voltage selection system provided in an embodiment of this disclosure;

[0065] Figure 9This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0067] In direct current (DC) converters, i.e., DCDC circuits, or chips that use multiple voltages to power the system, the voltage thresholds involved are quite complex. Therefore, voltage selection circuits are often required to select the voltage from multiple voltages supplied by the power supply, which also involves switching voltage thresholds. However, as described in the background section, current voltage selection circuits require sampling circuits to sample each input voltage, comparison circuits to compare each input voltage, and level shift circuits to control the on / off state of the output transistors, thus enabling or disabling the corresponding input-output branch. The structure of voltage selection circuits is relatively complex, each circuit occupies a large area, consumes a lot of power, and the entire selection process is lengthy, easily causing the output voltage transmitted to the voltage output terminal to drop during voltage selection switching. To address this, another voltage selection circuit has been proposed, mainly by replacing the comparison circuit with a switching transistor to achieve voltage comparison. However, when the input voltages provided by multiple voltage input terminals are close or even equal, under the control of the switching transistor, multiple output transistors will be in a conducting state, causing leakage between different voltage input terminals and resulting in efficiency loss.

[0068] This disclosure provides a voltage selection circuit with a simple structure, which can solve a series of problems such as complex structure, high power consumption, large area occupation, and leakage of current voltage selection circuits.

[0069] Figure 1 This is a schematic diagram of a voltage selection circuit provided in an embodiment of this disclosure. Figure 1 As shown, the voltage selection circuit includes: a first switching circuit 01, a second switching circuit 02, a first output circuit 03, and a second output circuit 04.

[0070] The first switching circuit 01 is coupled (i.e., electrically connected) to the first voltage input terminal VIN1, the first node A, the second node B, and the third node C. The first switching circuit 01 is used to control the on / off state of the first voltage input terminal VIN1 and the first node A based on the potential of the third node C and the potential of the first node A, and to control the on / off state of the first node A and the second node B based on the potential of the second node B.

[0071] For example, the first switching circuit 01 can control the first voltage input terminal VIN1 to conduct with the first node A when the potential of the third node C and / or the potential of the first node A is a first potential. Furthermore, the first switching circuit 01 can control the first voltage input terminal VIN1 to disconnect from the first node A when the potentials of the third node C and the first node A are both a second potential.

[0072] For example, the first switching circuit 01 can control the first node A and the second node B to conduct when the potential of the second node B is the first potential. Also, the first switching circuit 01 can control the first node A and the second node B to disconnect when the potential of the second node B is the second potential.

[0073] Optionally, in this embodiment of the disclosure, the first potential can be an effective potential, and the second potential can be an ineffective potential. Furthermore, the first potential can be a lower potential relative to the second potential. Of course, in some other embodiments, the first potential can also be a higher potential relative to the second potential.

[0074] The second switching circuit 02 is coupled to the second voltage input terminal VIN2, the fourth node D, the third node C, and the second node B, respectively. The second switching circuit 02 is used to control the on / off state of the second voltage input terminal VIN2 and the fourth node D based on the potential of the second node B and the fourth node D, and to control the on / off state of the fourth node D and the third node C based on the potential of the third node C.

[0075] For example, the second switching circuit 02 can control the second voltage input terminal VIN2 to conduct with the fourth node D when the potential of the second node B and / or the potential of the fourth node D is the first potential. Also, the second switching circuit 02 can control the second voltage input terminal VIN2 to disconnect from the fourth node D when the potentials of both the second node B and the fourth node D are the second potential.

[0076] For example, the second switching circuit 02 can control the fourth node D to be connected to the third node C when the potential of the third node C is the first potential. Also, the second switching circuit 02 can control the fourth node D to be disconnected from the third node C when the potential of the third node C is the second potential.

[0077] The first output circuit 03 is coupled to the fourth node D, the first voltage input terminal VIN1, and the voltage output terminal VCOM, respectively. The first output circuit 03 is used to control the on / off state of the first voltage input terminal VIN1 and the voltage output terminal VCOM based on the potential of the fourth node D.

[0078] For example, the first output circuit 03 can control the first voltage input terminal VIN1 and the voltage output terminal VCOM to conduct when the potential of the fourth node D is the first potential. At this time, the first input voltage provided by the first voltage input terminal VIN1 can be transmitted to the voltage output terminal VCOM, that is, the first input voltage can be selected as the output voltage. Furthermore, the first output circuit 03 can control the first voltage input terminal VIN1 and the voltage output terminal VCOM to disconnect when the potential of the fourth node D is the second potential.

[0079] The second output circuit 04 is coupled to the first node A, the second voltage input terminal VIN2, and the voltage output terminal VCOM, respectively. The second output circuit 04 is used to control the on / off state of the second voltage input terminal VIN2 and the voltage output terminal VCOM based on the potential of the first node A.

[0080] For example, the second output circuit 04 can control the second voltage input terminal VIN2 and the voltage output terminal VCOM to conduct when the potential of the first node A is the first potential. At this time, the second input voltage provided by the second voltage input terminal VIN2 can be transmitted to the voltage output terminal VCOM, that is, the second input voltage can be selected as the output voltage. Furthermore, the second output circuit 04 can also control the second voltage input terminal VIN2 and the voltage output terminal VCOM to disconnect when the potential of the first node A is the second potential.

[0081] As described in the above embodiments, in the first switching circuit 01 and the second switching circuit 02, either switching circuit can control the on / off state of the coupled voltage input terminal and the coupled node under the control of its own coupled node and the node coupled to the other switching circuit. Thus, one switching circuit can clamp the other, ensuring that at the same time, based on the first input voltage provided by the first voltage input terminal VIN1 and the second input voltage provided by the second voltage input terminal VIN2, only one of the first node A and the fourth node D has the first potential. Consequently, only one of the first output circuits 03 and 04 controls the coupled voltage input terminal to conduct with the voltage output terminal VCOM, thereby achieving reliable voltage selection. Furthermore, it avoids leakage problems caused by both the first output circuit 03 and the second output circuit 04 being connected to the voltage output terminal VCOM.

[0082] Furthermore, in this embodiment, with the cooperation of each circuit, when the first input voltage is greater than the second input voltage, the potential of the first node A can be the second potential, and the potential of the fourth node D can be the first potential. At this time, the first output circuit 03 can control the first voltage input terminal VIN1 to conduct with the voltage output terminal VCOM based on the first potential of the fourth node D. The second output circuit 04 can control the second voltage input terminal VIN2 to disconnect from the voltage output terminal VCOM based on the second potential of the first node A. This allows the larger first input voltage to be reliably transmitted to the voltage output terminal VCOM. When the second input voltage is greater than the first input voltage, the potential of the first node A can be the first potential, and the potential of the fourth node D can be the second potential. At this time, the second output circuit 04 can control the second voltage input terminal VIN2 to conduct with the voltage output terminal VCOM based on the first potential of the first node A. The first output circuit 03 can control the first voltage input terminal VIN1 to disconnect from the voltage output terminal VCOM based on the second potential of the fourth node D. This allows the larger second input voltage to be reliably transmitted to the voltage output terminal VCOM. When the first input voltage is equal to or close to the second input voltage, the potentials of the first node A and the fourth node D can both be the second potential. The first output circuit 03 can, based on the second potential of the fourth node D, control the disconnection of the first voltage input terminal VIN1 from the voltage output terminal VCOM. The second output circuit 04 can, based on the second potential of the first node A, control the disconnection of the second voltage input terminal VIN2 from the voltage output terminal VCOM. That is, this voltage selection circuit can select the higher voltage from the two input voltages to transmit to the voltage output terminal VCOM; correspondingly, it can also be called a high-voltage selection circuit.

[0083] In summary, the embodiments of this disclosure provide a voltage selection circuit. This voltage selection circuit includes two switching circuits and two output circuits. Each switching circuit can control the potential of its coupled node under the dual control of the node it is coupled to and the node coupled to the other switching circuit. The two output circuits can control the on / off connection between their coupled voltage input terminals and voltage output terminals based on the potential of the nodes coupled to the two switching circuits. Thus, through the switching control logic, only one voltage input terminal and voltage output terminal can be reliably connected at any given time, allowing only one voltage input terminal to provide the voltage output terminal, thereby quickly achieving voltage selection, avoiding voltage loss during transmission to the voltage output terminal, and simplifying the overall circuit structure.

[0084] Figure 2 This is a schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure. For example... Figure 2As shown, the first switching circuit 01 described in this embodiment may include: a first switching sub-circuit 011 and a second switching sub-circuit 012.

[0085] The first switch sub-circuit 011 can be coupled to the first voltage input terminal VIN1, the first node A, and the third node C, respectively. The first switch sub-circuit 011 can be used to control the on / off state of the first voltage input terminal VIN1 and the first node A based on the potential of the third node C and the potential of the first node A.

[0086] For example, the first switch sub-circuit 011 can control the first voltage input terminal VIN1 to conduct with the first node A when the potential of the third node C and / or the potential of the first node A is a first potential. Furthermore, the first switch sub-circuit 011 can control the first voltage input terminal VIN1 to disconnect from the first node A when the potentials of the third node C and the first node A are both a second potential.

[0087] The second switch sub-circuit 012 can be coupled to the first node A and the second node B respectively. The second switch sub-circuit 012 can be used to control the on / off state of the first node A and the second node B based on the potential of the second node B.

[0088] For example, the second switch sub-circuit 012 can control the first node A and the second node B to be connected when the potential of the second node B is the first potential. Also, the second switch sub-circuit 012 can control the first node A and the second node B to be disconnected when the potential of the second node B is the second potential.

[0089] Optional, continue to refer to Figure 2 It can be seen that the second switching circuit 02 described in the embodiments of this disclosure may include: a third switching sub-circuit 021 and a fourth switching sub-circuit 022.

[0090] The third switch sub-circuit 021 can be coupled to the second voltage input terminal VIN2, the fourth node D, and the second node B, respectively. The third switch sub-circuit 021 can be used to control the on / off state of the second voltage input terminal VIN2 and the fourth node D based on the potential of the fourth node D and the potential of the second node B.

[0091] For example, the third switch sub-circuit 021 can control the second voltage input terminal VIN2 to conduct with the fourth node D when the potential of the second node B and / or the potential of the fourth node D is the first potential. Also, the third switch sub-circuit 021 can control the second voltage input terminal VIN2 to decouple from the fourth node D when the potentials of the second node B and the fourth node D are both the second potential.

[0092] The fourth switch sub-circuit 022 can be coupled to the fourth node D and the third node C respectively. The fourth switch sub-circuit 022 can be used to control the on / off state of the fourth node D and the third node C based on the potential of the third node C.

[0093] For example, the fourth switch sub-circuit 022 can control the fourth node D to be connected to the third node C when the potential of the third node C is the first potential. Also, the fourth switch sub-circuit 022 can control the fourth node D to be disconnected from the third node C when the potential of the third node C is the second potential.

[0094] Optional, continue to refer to Figure 2 It can also be seen that the first switching circuit 01 described in the embodiments of this disclosure may further include: a first current generating sub-circuit 013.

[0095] The first current generating sub-circuit 013 can be coupled to the second node B and the pull-down power supply terminal GND, respectively. The first current generating sub-circuit 013 can be used to generate a bias current based on the potential of the second node B and the pull-down power supply signal provided by the pull-down power supply terminal GND.

[0096] Optional, continue to refer to Figure 2 It can also be seen that the second switching circuit 02 described in the embodiments of this disclosure may further include: a second current generating sub-circuit 023.

[0097] The second current generating sub-circuit 023 can be coupled to the third node C and the pull-down power supply terminal GND, respectively. The second current generating sub-circuit 023 can be used to generate a bias current based on the potential of the third node C and the pull-down power supply signal provided by the pull-down power supply terminal GND.

[0098] Here, ground (GND) represents the pull-down power supply terminal. In some other embodiments, the pull-down power supply terminal can also be other power supply terminals capable of providing a low potential, such as the VGL power supply terminal. (Combined with...) Figure 2 , Figure 1 It is also schematically shown that both the first switching circuit 01 and the second switching circuit 02 are grounded.

[0099] Figure 3 This is a schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure. For example... Figure 3 As shown, the first switching sub-circuit 011 described in this embodiment may include: a first transistor MP1 and a second transistor MP2. The second switching sub-circuit 012 may include: a third transistor MP3.

[0100] The gate and the second terminal of the first transistor MP1 can both be coupled to the first node A, and the first terminal of the first transistor MP1 can be coupled to the first voltage input terminal VIN1.

[0101] The gate of the second transistor MP2 can be coupled to the third node C, the first terminal of the second transistor MP2 can be coupled to the first voltage input terminal VIN1, and the second terminal of the second transistor MP2 can be coupled to the first node A.

[0102] The gate and second terminal of the third transistor MP3 can both be coupled to the second node B, and the first terminal of the third transistor MP3 can be coupled to the first node A.

[0103] Optional, continue to refer to Figure 3 It can be seen that the third switch sub-circuit 021 may include: the fourth transistor MP4 and the fifth transistor MP5. The fourth switch sub-circuit 022 may include: the sixth transistor MP6.

[0104] The gate and second terminal of the fourth transistor MP4 can both be coupled to the fourth node D, and the first terminal of the fourth transistor MP4 can be coupled to the second voltage input terminal VIN2.

[0105] The gate of the fifth transistor MP5 can be coupled to the second node B, the first terminal of the fifth transistor MP5 can be coupled to the second voltage input terminal VIN2, and the second terminal of the fifth transistor MP5 can be coupled to the fourth node D.

[0106] The gate and second terminal of the sixth transistor MP6 can both be coupled to the third node C, and the first terminal of the sixth transistor MP6 can be coupled to the fourth node D.

[0107] Optional, continue to refer to Figure 3 It can be seen that the first current generating sub-circuit 013 may include: the first current source IB1.

[0108] The input terminal of the first current source IB1 can be coupled to the second node B, and the output terminal of the first current source IB1 can be coupled to the pull-down power supply terminal GND.

[0109] Optional, continue to refer to Figure 3 It can be seen that the second current generating sub-circuit 023 may include: the second current source IB2.

[0110] The input of the second current source IB2 can be coupled to the third node C, and the output of the second current source IB2 can be coupled to the pull-down power supply GND.

[0111] Of course, in some other embodiments, the first current generating sub-circuit 013 and / or the second current generating sub-circuit 023 may also include a resistor. That is, the current source can be replaced by a resistor to generate the bias current.

[0112] It should be noted that, in the embodiments of this disclosure, the first terminal of the transistor can refer to the input stage of the transistor, such as the source. The second terminal can refer to the output stage of the transistor, such as the drain.

[0113] Optional, continue to refer to Figure 3 As can be seen, the first output circuit 03 described in this embodiment may include: a seventh transistor MP7, and a first substrate diode D1 formed between the substrate and drain of the seventh transistor MP7. The second output circuit 04 may include: an eighth transistor MP8, and a second substrate diode D2 formed between the substrate and drain of the eighth transistor MP8.

[0114] The gate of the seventh transistor MP7 can be coupled to the fourth node D, the drain of the seventh transistor MP7 can be coupled to the first voltage input terminal VIN1, and the source of the seventh transistor MP7 can be coupled to the voltage output terminal VCOM.

[0115] The positive terminal of the first substrate diode D1 can be coupled to the drain of the seventh transistor MP7, and the negative terminal of the first substrate diode D1 can be coupled to the substrate of the seventh transistor MP7.

[0116] The gate of the eighth transistor MP8 can be coupled to the first node A, the drain of the eighth transistor MP8 can be coupled to the second voltage input terminal VIN2, and the source of the eighth transistor MP8 can be coupled to the voltage output terminal VCOM.

[0117] The positive terminal of the second substrate diode D2 can be coupled to the drain of the eighth transistor MP8, and the negative terminal of the second substrate diode D2 can be coupled to the substrate of the eighth transistor MP8.

[0118] Optionally, in this embodiment of the disclosure, the seventh transistor MP7 and the eighth transistor MP8 can both be P-type metal-oxide-semiconductor (MOS) transistors fabricated on substrate B using an N-well process. The N-well process refers to a process that uses a lightly doped P-type silicon wafer as substrate B and creates an N-well on substrate B for fabricating PMOS transistors.

[0119] It should be noted that the first substrate diode D1 and the second substrate diode D2 here can refer to a parasitic diode formed on the substrate and the drain terminal, and do not represent a structure with such a substrate diode.

[0120] exist Figure 2 Based on the block diagram structure shown, Figure 4 A schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure is shown. For example... Figure 4 As shown, the voltage selection circuit described in this embodiment may further include: a bias voltage generation circuit 05 and a first protection circuit 06.

[0121] The bias voltage generation circuit 05 can be coupled to the voltage output terminal VCOM, the pull-down power supply terminal GND, and the control node S1, respectively. The bias voltage generation circuit 05 can be used to transmit the start-up bias voltage to the control node S1 based on the voltage output signal provided by the voltage output terminal VCOM and the pull-down power supply signal provided by the pull-down power supply terminal GND.

[0122] The first protection circuit 06 can be coupled to control node S1, first node A, fourth node D, first output circuit 03, and second output circuit 04, respectively. The first protection circuit 06 can be used to control the conduction of first node A and second output circuit 04, and the conduction of fourth node D and first output circuit 03, based on the turn-on bias voltage. Thus, when the voltage difference between the first input voltage provided at the first voltage input terminal VIN1 and the second input voltage provided at the second voltage input terminal VIN2 is too large, the first output circuit 03 and second output circuit 04 are protected; that is, the gates of the seventh transistor MP7 and the eighth transistor MP8 are protected, preventing damage to the first output circuit 03 and second output circuit 04.

[0123] exist Figure 4 Based on the block diagram structure shown, Figure 5 A schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure is shown. For example... Figure 5 As shown, the voltage selection circuit described in this embodiment may further include a second protection circuit 07.

[0124] The second protection circuit 07 can be coupled to control node S1, second node B, third node C, first switch circuit 01, and second switch circuit 02, respectively. The second protection circuit 07 can be used to control the second node B to conduct with the second switch circuit 02, and to control the third node C to conduct with the first switch circuit 01, based on the turn-on bias voltage. Optionally, in combination with... Figure 2 The first switch circuit 01 and the second switch circuit 02 shown here, the second protection circuit 07 may be coupled to the first switch sub-circuit 011 in the first switch circuit 01, and may be coupled to the third switch sub-circuit 021 in the second switch circuit 02.

[0125] Similar to the first protection circuit 06, by setting the second protection circuit 07, when the voltage difference between the first input voltage provided at the first voltage input terminal VIN1 and the second input voltage provided at the second voltage input terminal VIN2 is too large, the first switching sub-circuit 011 in the first switching circuit 01 and the third switching sub-circuit 021 in the second switching circuit 02 are protected, that is, the gates of the second transistor MP2 and the fifth transistor MP5 are protected, preventing damage to the first switching sub-circuit 011 and the third switching sub-circuit 021. In other words, by setting the bias voltage generating circuit 05, the first protection circuit 06, and the second protection circuit 07, protection can be achieved for each circuit in the voltage selection circuit, ensuring good operational reliability of the voltage selection circuit.

[0126] Optional, Figure 6 This is a schematic diagram of another voltage selection circuit provided in an embodiment of this disclosure. For example... Figure 6 As shown, the bias voltage generating circuit 05 described in this embodiment may include a diode D0 and a resistor R0. The first protection circuit 06 may include a ninth transistor MP9 and a tenth transistor MP10.

[0127] In this configuration, the positive terminal of diode D0 and one end of resistor R0 can both be coupled to control node S1, the negative terminal of diode D0 can be coupled to voltage output terminal VCOM, and the other end of resistor R0 can be coupled to pull-down power supply terminal GND.

[0128] The gate of the ninth transistor MP9 can be coupled to the control node S1, the first terminal of the ninth transistor MP9 can be coupled to the first node A, and the second terminal of the ninth transistor MP9 can be coupled to the second output circuit O4. That is, combined with Figure 3 The second terminal of the ninth transistor MP9 can be coupled to the gate of the eighth transistor MP8.

[0129] The gate of the tenth transistor MP10 can be coupled to the control node S1, the first terminal of the tenth transistor MP10 can be coupled to the fourth node D, and the second terminal of the tenth transistor MP10 can be coupled to the first output circuit O3. That is, combined with Figure 3 The second terminal of the tenth transistor MP10 can be coupled to the gate of the seventh transistor MP7.

[0130] That is, in this embodiment of the present disclosure, a ninth transistor MP9 can be connected in series between the gate of the eighth transistor MP8 included in the first node A and the second output circuit 04, and a tenth transistor MP10 can be connected in series between the gate of the seventh transistor MP7 included in the first output circuit 03 and the fourth node D, so that the gate of the eighth transistor MP8 is indirectly coupled to the first node A, and the gate of the seventh transistor MP7 is indirectly coupled to the fourth node D. Furthermore, a turn-on bias voltage can be generated by a diode D0 and a resistor R0 connected in series between the voltage output terminal VCOM and the ground terminal GND, ensuring that the ninth transistor MP9 and the tenth transistor MP10 are in a normally conducting state. This ensures reliable connection between the gate of the first node A and the gate of the eighth transistor MP8, and reliable connection between the gate of the fourth node D and the gate of the seventh transistor MP7. Additionally, the high voltage tolerance of the second terminals of the ninth transistor MP9 and the tenth transistor MP10 protects the gates of the seventh transistor MP7 and the eighth transistor MP8, preventing gate damage.

[0131] Of course, in some other embodiments, diode D0 can be replaced by other structures, such as multiple transistors connected in series. Resistor R0 can also be replaced by other structures, such as a current source. That is, the bias voltage generating circuit 05 may include, in addition to, other components such as... Figure 6 In addition to the series-connected diode D0 and resistor R0 shown, multiple transistors and resistors can also be included in series. This is as long as the turn-on bias voltage can be generated based on the output voltage provided by the voltage output terminal VCOM.

[0132] Optional, continue to refer to Figure 6 It can be seen that the second protection circuit 07 described in this embodiment may include: an eleventh transistor MP11 and a twelfth transistor MP12.

[0133] Specifically, the gate of the eleventh transistor MP11 can be coupled to the control node S1, the first terminal of the eleventh transistor MP11 can be coupled to the second node B, and the second terminal of the eleventh transistor MP11 can be coupled to the second switching circuit O2. That is, combined with Figure 3 The second terminal of the eleventh transistor MP11 can be coupled to the gate of the fifth transistor MP5.

[0134] The gate of the twelfth transistor MP12 can be coupled to the control node S1, the first terminal of the twelfth transistor MP12 can be coupled to the third node C, and the second terminal of the twelfth transistor MP12 can be coupled to the first switching circuit O1. That is, combined with Figure 3 The second terminal of the twelfth transistor MP12 can be coupled to the gate of the second transistor MP2.

[0135] That is, in this embodiment of the present disclosure, an eleventh transistor MP11 can be connected in series between the second node B and the gate of the fifth transistor MP5 included in the second switching circuit 02, and a twelfth transistor MP12 can be connected in series between the third node C and the gate of the second transistor MP2 included in the first switching circuit 01, so that the gate of the fifth transistor MP5 is indirectly coupled to the second node B, and the gate of the second transistor MP2 is indirectly coupled to the third node C. Furthermore, a turn-on bias voltage can be generated by a diode D0 and a resistor R0 connected in series between the voltage output terminal VCOM and the ground terminal, ensuring that the eleventh transistor MP11 and the twelfth transistor MP12 are in a normally conducting state. This ensures reliable connection between the gate of the second node B and the gate of the fifth transistor MP5, and reliable connection between the third node C and the gate of the second transistor MP2. Additionally, the high voltage tolerance of the second terminals of the eleventh transistor MP11 and the twelfth transistor MP12 protects the gates of the second transistor MP2 and the fifth transistor MP5, preventing gate damage. For example, the gate-source voltage difference Vgs of the fifth transistor MP5 can be clamped within the voltage range of Vcom - Vd0 + VgsMP11. Here, Vcom refers to the output voltage, Vd0 is the voltage drop across diode D0, and VgsMP11 is the gate-source voltage difference of the eleventh transistor MP11. The gate-source voltage difference Vgs of the second transistor MP2 can be handled similarly.

[0136] Optional, combined Figure 6 In the voltage selection circuit described in this embodiment, the transistors (i.e., the first transistor MP1 to the twelfth transistor MP12) can all be P-type transistors, such as PMOS transistors. Accordingly, considering the operating characteristics of P-type transistors, the first potential (i.e., the effective potential) described in this embodiment can be a low potential, and the second potential (i.e., the ineffective potential) can be a high potential.

[0137] It should be noted that the above is only a schematic illustration of two voltage input terminals, VIN1 and VIN2, as input voltage supply terminals. In multi-voltage power supply systems, a greater number of voltage input terminals may be involved. The selection principle can be referred to the above embodiments and will not be repeated here. Figure 6 Taking the structure shown as an example, the working principle of the voltage selection circuit described in the embodiments of this disclosure is introduced as follows:

[0138] Example, reference Figure 7 It shows a schematic diagram of a potential. Combined with... Figure 6 and Figure 7It can be seen that the potential VB of the second node B satisfies: VB = VA - VgsMP3, where VA refers to the potential of the first node A, and VgsMP3 refers to the gate-source voltage difference of the third transistor MP3. Since the gate-source voltage difference VgsMP3 of the third transistor MP3 is generally a constant, it can be seen that the potential VB of the second node B can change with the potential VA of the first node A. Similarly, the potential VC of the third node C satisfies: VC = VD - VgsMP6, where VD refers to the potential of the fourth node D, and VgsMP6 refers to the gate-source voltage difference of the sixth transistor MP6. Since the gate-source voltage difference VgsMP6 of the sixth transistor MP6 is generally a constant, it can be seen that the potential VC of the third node C can change with the potential VD of the fourth node D.

[0139] Initially, the first input voltage Vin1 provided by the first voltage input terminal VIN1 can be high, and the second input voltage Vin2 provided by the second voltage input terminal VIN2 can be low; that is, the first input voltage Vin1 can be much greater than the second input voltage Vin2. At this time, the potential VD of the fourth node D and the potential VC of the third node C are both much lower than the first input voltage Vin1. Correspondingly, the potential VD of the fourth node D can be transmitted to the gate of the seventh transistor MP7 through the normally conducting tenth transistor MP10, causing the seventh transistor MP7 to turn on. This allows the first input voltage Vin1 to be transmitted to the voltage output terminal VCOM via the seventh transistor MP7, meaning that the output voltage Vcom of the voltage output terminal VCOM is equal to Vin1 (i.e., Vcom = Vin1). Furthermore, the potential VC of the third node C can be transmitted to the gate of the second transistor MP2 through the normally conducting twelfth transistor MP12, causing the second transistor MP2 to turn on. This allows the first input voltage Vin1 to be transmitted to the first node A via the second transistor MP2, meaning the potential VA of the first node A can be equal to Vin1 (i.e., VA = Vin1). Referring to the above embodiment, the potential VB of the second node B at this time is VB = VA - VgsMP3 = Vin1 - VgsMP3. Correspondingly, although the potential VA of the first node A can be transmitted to the gate of the eighth transistor MP8 through the normally conducting ninth transistor MP9, the eighth transistor MP8 cannot be turned on. Similarly, although the potential VB of the second node B can be transmitted to the gate of the fifth transistor MP5 through the normally conducting eleventh transistor MP11, the fifth transistor MP5 also cannot be turned on. That is, when the first input voltage Vin1 is much greater than the second input voltage Vin2, only the seventh transistor MP7 coupled to the first voltage input terminal VIN1 can be controlled to turn on, so that the first input voltage Vin1 is transmitted to the voltage output terminal VCOM. In other words, the first input voltage Vin1 with the higher voltage is selected at this time.

[0140] Continue to refer to Figure 7It can be seen that as the second input voltage Vin2 gradually increases, until the potential of the second node B is transmitted to the gate of the fifth transistor MP5 through the normally conducting eleventh transistor MP11, making the fifth transistor MP5 turn on, the potential VD of the fourth node D can be equal to the second input voltage Vin2 (i.e., VD = Vin2). At this time, the potential VD of the fourth node D is transmitted to the gate of the seventh transistor MP7 through the normally conducting tenth transistor MP10, which can turn off the seventh transistor MP7. When the potential VA of the first node A, transmitted to the gate of the eighth transistor MP8 through the normally conducting ninth transistor MP9, is still low and cannot control the eighth transistor MP8 to turn on, if the first input voltage Vin1 is greater than the second input voltage Vin2 (i.e., Vin1 > Vin2), then the output voltage Vcom transmitted to the voltage output terminal VCOM can satisfy: Vcom = Vin1 - VdMP7, where VdMP7 can refer to the voltage drop on the first substrate diode D1 formed between the substrate and drain of the seventh transistor MP7. Conversely, if the second input voltage Vin2 is greater than the first input voltage Vin1 (i.e., Vin2>Vin1), then the output voltage Vcom transmitted to the voltage output terminal VCOM can satisfy: Vcom=Vin2-VdMP8, where VdMP8 can refer to the voltage drop on the second substrate diode D2 formed between the substrate and drain of the eighth transistor MP8.

[0141] Continue to refer to Figure 7It can be seen that when the second input voltage Vin2 is greater than the first input voltage Vin1, and the second input voltage Vin2 is even higher, until the potential VC of the third node C > Vin1 - VthMP2, the potential VC of the third node C is transmitted to the gate of the second transistor MP2 through the normally conducting twelfth transistor MP12, which can turn off the second transistor MP2, where VthMP2 refers to the threshold voltage of the second transistor MP2. At this time, the potential VA of the first node A can satisfy: VA = Vin1 - VgsMP1, where VgsMP1 refers to the gate-source voltage difference of the first transistor MP1. And because the second input voltage Vin2 is higher, the seventh transistor MP7 can remain off. The potential VA of the first node A is transmitted to the gate of the eighth transistor MP8 through the normally conducting ninth transistor MP9, which can turn on the eighth transistor MP8, and thus the second input voltage Vin2 can be transmitted to the voltage output terminal VCOM through the eighth transistor MP12. That is, at this time, the output voltage Vcom of the voltage output terminal VCOM is equal to Vin2 (i.e., Vcom = Vin2). In other words, when the second input voltage Vin2 is much greater than the first input voltage Vin1, only the eighth transistor MP8 coupled to the second voltage input terminal VIN2 can be controlled to turn on, so that the second input voltage Vin2 is transmitted to the voltage output terminal VCOM. That is, the second input voltage Vin2 with the higher voltage is selected at this time.

[0142] Based on the above description, in this embodiment, each transistor can mutually drive the transistors in the two output circuits to turn on or off based on its own generated gate-source voltage difference Vgs and the received potential, without needing to judge the voltage. When the voltage magnitude changes, the output voltage can also switch seamlessly without voltage drop, thus avoiding impact on the downstream load. Furthermore, because the voltage selection circuit provided in this embodiment does not require sampling circuits, comparison circuits, and level shifting circuits to achieve voltage selection, it is not only simple in structure and occupies a small area for each transistor, but the entire voltage selection process does not involve a series of operations such as sampling and comparison, and the voltage selection time can be short, thereby preventing power loss of the output voltage transmitted to the voltage output terminal VCOM. Moreover, by using a node controlled by one switching circuit to clamp the operation of another switching circuit, this embodiment can prevent the transistors in the two output circuits from turning on simultaneously, thereby avoiding leakage and improving operational reliability.

[0143] In summary, the embodiments of this disclosure provide a voltage selection circuit. This voltage selection circuit includes two switching circuits and two output circuits. Each switching circuit can control the potential of its coupled node under the dual control of the node it is coupled to and the node coupled to the other switching circuit. The two output circuits can control the on / off connection between their coupled voltage input terminals and voltage output terminals based on the potential of the nodes coupled to the two switching circuits. Thus, through the switching control logic, only one voltage input terminal and voltage output terminal can be reliably connected at any given time, allowing only one voltage input terminal to provide the voltage output terminal, thereby quickly achieving voltage selection, avoiding voltage loss during transmission to the voltage output terminal, and simplifying the overall circuit structure.

[0144] Figure 8 This is a schematic diagram of a voltage selection system provided in an embodiment of this disclosure. Figure 8 As shown, the voltage selection system may include: multiple cascaded systems such as... Figures 1 to 6 Any of the voltage selection circuits 00 shown, wherein the voltage output terminal VCOM of the preceding voltage selection circuit 00 can be coupled to the first voltage input terminal VIN1 or the second voltage input terminal VIN2 of the following voltage selection circuit 00.

[0145] Figure 9 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. For example... Figure 9 As shown, the electronic device includes: a front-end power supply circuit 100, a rear-end load 200, and as shown in the figure. Figure 8 The voltage selection system shown is 000.

[0146] The front-end power supply circuit 100 can be coupled to the voltage selection system 000, and the voltage selection system 000 can be coupled to the downstream load 200. The front-end power supply circuit 100 can be used to transmit multiple input voltages of different magnitudes to the voltage selection system 000, and the voltage selection system 000 can be used to select one input voltage from the multiple input voltages as the output voltage to be transmitted to the downstream load 200 to power the downstream load 200.

[0147] For example, the front-end power supply circuit 100 can be coupled to a voltage input terminal (e.g., a first voltage input terminal VIN1 and a second voltage input terminal VIN2) in the voltage selection system 000 to transmit the input voltage to that voltage input terminal. The voltage selection system 000 can be coupled to the downstream load 200 through the voltage output terminal VCOM to select one input voltage from multiple input voltages and transmit it to the downstream load 200 via the voltage output terminal VCOM.

[0148] Optionally, the electronic device described in this disclosure embodiment can be a display device including a display panel, and correspondingly, the downstream load 200 can be a load in the display device. That is, the voltage selection circuit provided in this disclosure embodiment can be applied to a display device. For example, the display device can be any product or component with display function, such as an organic light-emitting diode (OLED) display device, a mobile phone, a tablet computer, a flexible display device, a television, and a monitor.

[0149] The terminology used in the embodiments of this disclosure is for the purpose of explaining the embodiments of this disclosure only and is not intended to limit this disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should be understood in their ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0150] For example, the terms “first,” “second,” or “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components.

[0151] Similarly, words like "one" or "one" do not indicate a quantity limit, but rather that there is at least one.

[0152] The word “includes” or similar terms means that the elements or objects preceding “includes” or “include” cover the elements or objects listed after “includes” or “include” or their equivalents, and do not exclude other elements or objects.

[0153] Terms like "up," "down," "left," or "right" are used only to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly. "Connection" or "coupled" refers to an electrical connection.

[0154] The "and / or" signifies that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0155] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A voltage selection circuit, characterized in that, The voltage selection circuit includes: The first switching circuit (01) is coupled to the first voltage input terminal (VIN1), the first node (A), the second node (B) and the third node (C) respectively, and is used to control the on / off state of the first voltage input terminal (VIN1) and the first node (A) based on the potential of the third node (C) and the potential of the first node (A), and to control the on / off state of the first node (A) and the second node (B) based on the potential of the second node (B); The second switching circuit (02) is coupled to the second voltage input terminal (VIN2), the fourth node (D), the third node (C), and the second node (B) respectively. It is used to control the on / off state of the second voltage input terminal (VIN2) and the fourth node (D) based on the potential of the second node (B) and the potential of the fourth node (D), and to control the on / off state of the fourth node (D) and the third node (C) based on the potential of the third node (C). The first output circuit (03) is coupled to the fourth node (D), the first voltage input terminal (VIN1) and the voltage output terminal (VCOM) respectively, and is used to control the on / off state of the first voltage input terminal (VIN1) and the voltage output terminal (VCOM) based on the potential of the fourth node (D). The second output circuit (04) is coupled to the first node (A), the second voltage input terminal (VIN2) and the voltage output terminal (VCOM) respectively, and is used to control the on / off state of the second voltage input terminal (VIN2) and the voltage output terminal (VCOM) based on the potential of the first node (A); The first switching circuit (01) includes a first switching sub-circuit (011) and a second switching sub-circuit (012); the second switching circuit (02) includes a third switching sub-circuit (021) and a fourth switching sub-circuit (022). The first switch sub-circuit (011) is coupled to the first voltage input terminal (VIN1), the first node (A) and the third node (C) respectively, and is used to control the on / off state of the first voltage input terminal (VIN1) and the first node (A) based on the potential of the third node (C) and the potential of the first node (A); The second switch sub-circuit (012) is coupled to the first node (A) and the second node (B) respectively, and is used to control the on / off state of the first node (A) and the second node (B) based on the potential of the second node (B); The third switch sub-circuit (021) is coupled to the second voltage input terminal (VIN2), the fourth node (D) and the second node (B) respectively, and is used to control the on / off state of the second voltage input terminal (VIN2) and the fourth node (D) based on the potential of the fourth node (D) and the potential of the second node (B); The fourth switch sub-circuit (022) is coupled to the fourth node (D) and the third node (C) respectively, and is used to control the on / off state of the fourth node (D) and the third node (C) based on the potential of the third node (C).

2. The voltage selection circuit according to claim 1, characterized in that, The first switching sub-circuit (011) includes: a first transistor (MP1) and a second transistor (MP2); the second switching sub-circuit (012) includes: a third transistor (MP3); The gate and the second terminal of the first transistor (MP1) are both coupled to the first node (A), and the first terminal of the first transistor (MP1) is coupled to the first voltage input terminal (VIN1). The gate of the second transistor (MP2) is coupled to the third node (C), the first terminal of the second transistor (MP2) is coupled to the first voltage input terminal (VIN1), and the second terminal of the second transistor (MP2) is coupled to the first node (A). The gate and second electrode of the third transistor (MP3) are both coupled to the second node (B), and the first electrode of the third transistor (MP3) is coupled to the first node (A).

3. The voltage selection circuit according to claim 1, wherein the first switching circuit (01) further comprises: The first current generating sub-circuit (013) is coupled to the second node (B) and the pull-down power supply terminal (GND) respectively, and is used to generate a bias current based on the potential of the second node (B) and the pull-down power supply signal provided by the pull-down power supply terminal (GND).

4. The voltage selection circuit according to claim 3, characterized in that, The first current generating sub-circuit (013) includes: a first current source (IB1); The input terminal of the first current source (IB1) is coupled to the second node (B), and the output terminal of the first current source (IB1) is coupled to the pull-down power supply terminal (GND).

5. The voltage selection circuit according to any one of claims 1 to 4, characterized in that, The third switch sub-circuit (021) includes: a fourth transistor (MP4) and a fifth transistor (MP5); the fourth switch sub-circuit (022) includes: a sixth transistor (MP6); The gate and the second terminal of the fourth transistor (MP4) are both coupled to the fourth node (D), and the first terminal of the fourth transistor (MP4) is coupled to the second voltage input terminal (VIN2). The gate of the fifth transistor (MP5) is coupled to the second node (B), the first terminal of the fifth transistor (MP5) is coupled to the second voltage input terminal (VIN2), and the second terminal of the fifth transistor (MP5) is coupled to the fourth node (D). The gate and second terminal of the sixth transistor (MP6) are both coupled to the third node (C), and the first terminal of the sixth transistor (MP6) is coupled to the fourth node (D).

6. The voltage selection circuit according to any one of claims 1 to 4, characterized in that, The second switching circuit (02) also includes: The second current generating sub-circuit (023) is coupled to the third node (C) and the pull-down power supply terminal (GND) respectively, and is used to generate a bias current based on the potential of the third node (C) and the pull-down power supply signal provided by the pull-down power supply terminal (GND).

7. The voltage selection circuit according to claim 6, characterized in that, The second current generating sub-circuit (023) includes: a second current source (IB2); The input terminal of the second current source (IB2) is coupled to the third node (C), and the output terminal of the second current source (IB2) is coupled to the pull-down power supply terminal (GND).

8. The voltage selection circuit according to any one of claims 1 to 4, characterized in that, The first output circuit (03) includes: a seventh transistor (MP7) and a first substrate diode (D1) formed between the substrate and drain of the seventh transistor (MP7); the second output circuit (04) includes: an eighth transistor (MP8) and a second substrate diode (D2) formed between the substrate and drain of the eighth transistor (MP8). The gate of the seventh transistor (MP7) is coupled to the fourth node (D), the drain of the seventh transistor (MP7) is coupled to the first voltage input terminal (VIN1), and the source of the seventh transistor (MP7) is coupled to the voltage output terminal (VCOM). The positive terminal of the first substrate diode (D1) is coupled to the drain of the seventh transistor (MP7), and the negative terminal is coupled to the substrate of the seventh transistor (MP7). The gate of the eighth transistor (MP8) is coupled to the first node (A), the drain of the eighth transistor (MP8) is coupled to the second voltage input terminal (VIN2), and the source of the eighth transistor (MP8) is coupled to the voltage output terminal (VCOM). The positive terminal of the second substrate diode (D2) is coupled to the drain of the eighth transistor (MP8), and the negative terminal is coupled to the substrate of the eighth transistor (MP8).

9. The voltage selection circuit according to any one of claims 1 to 4, characterized in that, The voltage selection circuit further includes: The bias voltage generation circuit (05) is coupled to the voltage output terminal (VCOM), the pull-down power supply terminal (GND) and the control node (S1) respectively, and is used to transmit the start bias voltage to the control node (S1) based on the voltage output signal provided by the voltage output terminal (VCOM) and the pull-down power supply signal provided by the pull-down power supply terminal (GND). The first protection circuit (06) is coupled to the control node (S1), the first node (A), the fourth node (D), the first output circuit (03), and the second output circuit (04) respectively, and is used to control the first node (A) to conduct with the second output circuit (04) and the fourth node (D) to conduct with the first output circuit (03) based on the turn-on bias voltage.

10. The voltage selection circuit according to claim 9, characterized in that, The bias voltage generating circuit (05) includes a diode (D0) and a resistor (R0); the first protection circuit (06) includes a ninth transistor (MP9) and a tenth transistor (MP10). The positive terminal of the diode (D0) and one end of the resistor (R0) are both coupled to the control node (S1), the negative terminal of the diode (D0) is coupled to the voltage output terminal (VCOM), and the other end of the resistor (R0) is coupled to the pull-down power supply terminal (GND). The gate of the ninth transistor (MP9) is coupled to the control node (S1), the first terminal of the ninth transistor (MP9) is coupled to the first node (A), and the second terminal of the ninth transistor (MP9) is coupled to the second output circuit (04). The gate of the tenth transistor (MP10) is coupled to the control node (S1), the first terminal of the tenth transistor (MP10) is coupled to the fourth node (D), and the second terminal of the tenth transistor (MP10) is coupled to the first output circuit (03).

11. The voltage selection circuit according to claim 9, characterized in that, The voltage selection circuit further includes: The second protection circuit (07) is coupled to the control node (S1), the second node (B), the third node (C), the first switch circuit (01), and the second switch circuit (02) respectively, and is used to control the second node (B) to be connected to the second switch circuit (02) and to control the third node (C) to be connected to the first switch circuit (01) based on the turn-on bias voltage.

12. The voltage selection circuit according to claim 11, characterized in that, The second protection circuit (07) includes: an eleventh transistor (MP11) and a twelfth transistor (MP12); The gate of the eleventh transistor (MP11) is coupled to the control node (S1), the first terminal of the eleventh transistor (MP11) is coupled to the second node (B), and the second terminal of the eleventh transistor (MP11) is coupled to the second switching circuit (02). The gate of the twelfth transistor (MP12) is coupled to the control node (S1), the first terminal of the twelfth transistor (MP12) is coupled to the third node (C), and the second terminal of the twelfth transistor (MP12) is coupled to the first switching circuit (01).

13. The voltage selection circuit according to any one of claims 1 to 4, characterized in that, The voltage selection circuit includes P-type transistors.

14. A voltage selection system, characterized in that, The voltage selection system includes: a plurality of cascaded voltage selection circuits (00) as described in any one of claims 1 to 13, wherein the voltage output terminal (VCOM) of the preceding voltage selection circuit (00) is coupled to the first voltage input terminal (VIN1) or the second voltage input terminal (VIN2) of the following voltage selection circuit (00).

15. An electronic device, characterized in that, The electronic device includes: a front-end power supply circuit (100), a rear-end load (200), and a voltage selection system (000) as described in claim 14. The pre-stage power supply circuit (100) is coupled to the voltage selection system (000), and the voltage selection system (000) is coupled to the downstream load (200). The pre-stage power supply circuit (100) is used to transmit multiple input voltages of different magnitudes to the voltage selection system (000), and the voltage selection system (000) is used to select one input voltage from the multiple input voltages as the output voltage and transmit it to the downstream load (200) to supply power to the downstream load (200).

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